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c00b5f85 WD |
1 | /*----------------------------------------------------------------------------+ |
2 | | | |
ba56f625 WD |
3 | | This source code has been made available to you by IBM on an AS-IS |
4 | | basis. Anyone receiving this source is licensed under IBM | |
5 | | copyrights to use it in any way he or she deems fit, including | |
6 | | copying it, modifying it, compiling it, and redistributing it either | |
7 | | with or without modifications. No license under IBM patents or | |
8 | | patent applications is to be implied by the copyright license. | |
c00b5f85 | 9 | | |
ba56f625 WD |
10 | | Any user of this software should understand that IBM cannot provide |
11 | | technical support for this software and will not be responsible for | |
12 | | any consequences resulting from the use of this software. | |
c00b5f85 | 13 | | |
ba56f625 WD |
14 | | Any person who transfers this source code or any derivative work |
15 | | must include the IBM copyright notice, this paragraph, and the | |
16 | | preceding two paragraphs in the transferred software. | |
c00b5f85 | 17 | | |
ba56f625 WD |
18 | | COPYRIGHT I B M CORPORATION 1999 |
19 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
c00b5f85 WD |
20 | +----------------------------------------------------------------------------*/ |
21 | ||
ba56f625 | 22 | #ifndef __PPC440_H__ |
c00b5f85 WD |
23 | #define __PPC440_H__ |
24 | ||
25 | /*--------------------------------------------------------------------- */ | |
26 | /* Special Purpose Registers */ | |
27 | /*--------------------------------------------------------------------- */ | |
ba56f625 WD |
28 | #define dec 0x016 /* decrementer */ |
29 | #define srr0 0x01a /* save/restore register 0 */ | |
30 | #define srr1 0x01b /* save/restore register 1 */ | |
31 | #define pid 0x030 /* process id */ | |
32 | #define decar 0x036 /* decrementer auto-reload */ | |
33 | #define csrr0 0x03a /* critical save/restore register 0 */ | |
34 | #define csrr1 0x03b /* critical save/restore register 1 */ | |
35 | #define dear 0x03d /* data exception address register */ | |
36 | #define esr 0x03e /* exception syndrome register */ | |
37 | #define ivpr 0x03f /* interrupt prefix register */ | |
38 | #define usprg0 0x100 /* user special purpose register general 0 */ | |
39 | #define usprg1 0x110 /* user special purpose register general 1 */ | |
40 | #define sprg1 0x111 /* special purpose register general 1 */ | |
41 | #define sprg2 0x112 /* special purpose register general 2 */ | |
42 | #define sprg3 0x113 /* special purpose register general 3 */ | |
43 | #define sprg4 0x114 /* special purpose register general 4 */ | |
44 | #define sprg5 0x115 /* special purpose register general 5 */ | |
45 | #define sprg6 0x116 /* special purpose register general 6 */ | |
46 | #define sprg7 0x117 /* special purpose register general 7 */ | |
47 | #define tbl 0x11c /* time base lower (supervisor)*/ | |
48 | #define tbu 0x11d /* time base upper (supervisor)*/ | |
49 | #define pir 0x11e /* processor id register */ | |
50 | /*#define pvr 0x11f processor version register */ | |
51 | #define dbsr 0x130 /* debug status register */ | |
52 | #define dbcr0 0x134 /* debug control register 0 */ | |
53 | #define dbcr1 0x135 /* debug control register 1 */ | |
54 | #define dbcr2 0x136 /* debug control register 2 */ | |
55 | #define iac1 0x138 /* instruction address compare 1 */ | |
56 | #define iac2 0x139 /* instruction address compare 2 */ | |
57 | #define iac3 0x13a /* instruction address compare 3 */ | |
58 | #define iac4 0x13b /* instruction address compare 4 */ | |
59 | #define dac1 0x13c /* data address compare 1 */ | |
60 | #define dac2 0x13d /* data address compare 2 */ | |
61 | #define dvc1 0x13e /* data value compare 1 */ | |
62 | #define dvc2 0x13f /* data value compare 2 */ | |
63 | #define tsr 0x150 /* timer status register */ | |
64 | #define tcr 0x154 /* timer control register */ | |
65 | #define ivor0 0x190 /* interrupt vector offset register 0 */ | |
66 | #define ivor1 0x191 /* interrupt vector offset register 1 */ | |
67 | #define ivor2 0x192 /* interrupt vector offset register 2 */ | |
68 | #define ivor3 0x193 /* interrupt vector offset register 3 */ | |
69 | #define ivor4 0x194 /* interrupt vector offset register 4 */ | |
70 | #define ivor5 0x195 /* interrupt vector offset register 5 */ | |
71 | #define ivor6 0x196 /* interrupt vector offset register 6 */ | |
72 | #define ivor7 0x197 /* interrupt vector offset register 7 */ | |
73 | #define ivor8 0x198 /* interrupt vector offset register 8 */ | |
74 | #define ivor9 0x199 /* interrupt vector offset register 9 */ | |
75 | #define ivor10 0x19a /* interrupt vector offset register 10 */ | |
76 | #define ivor11 0x19b /* interrupt vector offset register 11 */ | |
77 | #define ivor12 0x19c /* interrupt vector offset register 12 */ | |
78 | #define ivor13 0x19d /* interrupt vector offset register 13 */ | |
79 | #define ivor14 0x19e /* interrupt vector offset register 14 */ | |
80 | #define ivor15 0x19f /* interrupt vector offset register 15 */ | |
c157d8e2 | 81 | #if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR) |
ba56f625 WD |
82 | #define mcsrr0 0x23a /* machine check save/restore register 0 */ |
83 | #define mcsrr1 0x23b /* mahcine check save/restore register 1 */ | |
84 | #define mcsr 0x23c /* machine check status register */ | |
85 | #endif | |
86 | #define inv0 0x370 /* instruction cache normal victim 0 */ | |
87 | #define inv1 0x371 /* instruction cache normal victim 1 */ | |
88 | #define inv2 0x372 /* instruction cache normal victim 2 */ | |
89 | #define inv3 0x373 /* instruction cache normal victim 3 */ | |
90 | #define itv0 0x374 /* instruction cache transient victim 0 */ | |
91 | #define itv1 0x375 /* instruction cache transient victim 1 */ | |
92 | #define itv2 0x376 /* instruction cache transient victim 2 */ | |
93 | #define itv3 0x377 /* instruction cache transient victim 3 */ | |
94 | #define dnv0 0x390 /* data cache normal victim 0 */ | |
95 | #define dnv1 0x391 /* data cache normal victim 1 */ | |
96 | #define dnv2 0x392 /* data cache normal victim 2 */ | |
97 | #define dnv3 0x393 /* data cache normal victim 3 */ | |
98 | #define dtv0 0x394 /* data cache transient victim 0 */ | |
99 | #define dtv1 0x395 /* data cache transient victim 1 */ | |
100 | #define dtv2 0x396 /* data cache transient victim 2 */ | |
101 | #define dtv3 0x397 /* data cache transient victim 3 */ | |
102 | #define dvlim 0x398 /* data cache victim limit */ | |
103 | #define ivlim 0x399 /* instruction cache victim limit */ | |
104 | #define rstcfg 0x39b /* reset configuration */ | |
105 | #define dcdbtrl 0x39c /* data cache debug tag register low */ | |
106 | #define dcdbtrh 0x39d /* data cache debug tag register high */ | |
107 | #define icdbtrl 0x39e /* instruction cache debug tag register low */ | |
108 | #define icdbtrh 0x39f /* instruction cache debug tag register high */ | |
109 | #define mmucr 0x3b2 /* mmu control register */ | |
110 | #define ccr0 0x3b3 /* core configuration register 0 */ | |
c157d8e2 | 111 | #define ccr1 0x378 /* core configuration for 440x5 only */ |
ba56f625 WD |
112 | #define icdbdr 0x3d3 /* instruction cache debug data register */ |
113 | #define dbdr 0x3f3 /* debug data register */ | |
c00b5f85 WD |
114 | |
115 | /****************************************************************************** | |
116 | * DCRs & Related | |
117 | ******************************************************************************/ | |
118 | ||
ba56f625 WD |
119 | /*----------------------------------------------------------------------------- |
120 | | Clocking Controller | |
121 | +----------------------------------------------------------------------------*/ | |
122 | #define CLOCKING_DCR_BASE 0x0c | |
123 | #define clkcfga (CLOCKING_DCR_BASE+0x0) | |
124 | #define clkcfgd (CLOCKING_DCR_BASE+0x1) | |
125 | ||
126 | /* values for clkcfga register - indirect addressing of these regs */ | |
127 | #define clk_clkukpd 0x0020 | |
128 | #define clk_pllc 0x0040 | |
129 | #define clk_plld 0x0060 | |
130 | #define clk_primad 0x0080 | |
131 | #define clk_primbd 0x00a0 | |
132 | #define clk_opbd 0x00c0 | |
133 | #define clk_perd 0x00e0 | |
134 | #define clk_mald 0x0100 | |
c157d8e2 | 135 | #define clk_spcid 0x0120 |
ba56f625 WD |
136 | #define clk_icfg 0x0140 |
137 | ||
138 | /* 440gx sdr register definations */ | |
139 | #define SDR_DCR_BASE 0x0e | |
140 | #define sdrcfga (SDR_DCR_BASE+0x0) | |
141 | #define sdrcfgd (SDR_DCR_BASE+0x1) | |
142 | #define sdr_sdstp0 0x0020 /* */ | |
143 | #define sdr_sdstp1 0x0021 /* */ | |
144 | #define sdr_pinstp 0x0040 | |
145 | #define sdr_sdcs 0x0060 | |
146 | #define sdr_ecid0 0x0080 | |
147 | #define sdr_ecid1 0x0081 | |
148 | #define sdr_ecid2 0x0082 | |
149 | #define sdr_jtag 0x00c0 | |
150 | #define sdr_ddrdl 0x00e0 | |
151 | #define sdr_ebc 0x0100 | |
152 | #define sdr_uart0 0x0120 /* UART0 Config */ | |
153 | #define sdr_uart1 0x0121 /* UART1 Config */ | |
c157d8e2 SR |
154 | #define sdr_uart2 0x0122 /* UART2 Config */ |
155 | #define sdr_uart3 0x0123 /* UART3 Config */ | |
ba56f625 WD |
156 | #define sdr_cp440 0x0180 |
157 | #define sdr_xcr 0x01c0 | |
158 | #define sdr_xpllc 0x01c1 | |
159 | #define sdr_xplld 0x01c2 | |
160 | #define sdr_srst 0x0200 | |
161 | #define sdr_slpipe 0x0220 | |
c157d8e2 SR |
162 | #define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ |
163 | #define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ | |
ba56f625 WD |
164 | #define sdr_mirq0 0x0260 |
165 | #define sdr_mirq1 0x0261 | |
166 | #define sdr_maltbl 0x0280 | |
167 | #define sdr_malrbl 0x02a0 | |
168 | #define sdr_maltbs 0x02c0 | |
169 | #define sdr_malrbs 0x02e0 | |
c157d8e2 SR |
170 | #define sdr_pci0 0x0300 |
171 | #define sdr_usb0 0x0320 | |
ba56f625 WD |
172 | #define sdr_cust0 0x4000 |
173 | #define sdr_sdstp2 0x4001 | |
174 | #define sdr_cust1 0x4002 | |
175 | #define sdr_sdstp3 0x4003 | |
176 | #define sdr_pfc0 0x4100 /* Pin Function 0 */ | |
177 | #define sdr_pfc1 0x4101 /* Pin Function 1 */ | |
178 | #define sdr_plbtr 0x4200 | |
179 | #define sdr_mfr 0x4300 /* SDR0_MFR reg */ | |
180 | ||
181 | ||
c00b5f85 WD |
182 | /*----------------------------------------------------------------------------- |
183 | | SDRAM Controller | |
184 | +----------------------------------------------------------------------------*/ | |
185 | #define SDRAM_DCR_BASE 0x10 | |
ba56f625 WD |
186 | #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ |
187 | #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ | |
188 | ||
189 | /* values for memcfga register - indirect addressing of these regs */ | |
190 | #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ | |
191 | #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ | |
192 | #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */ | |
193 | #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */ | |
194 | #define mem_bear 0x0010 /* bus error address reg */ | |
195 | #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */ | |
196 | #define mem_mirq_set 0x0012 /* bus master interrupt (set) */ | |
197 | #define mem_slio 0x0018 /* ddr sdram slave interface options */ | |
198 | #define mem_cfg0 0x0020 /* ddr sdram options 0 */ | |
199 | #define mem_cfg1 0x0021 /* ddr sdram options 1 */ | |
200 | #define mem_devopt 0x0022 /* ddr sdram device options */ | |
201 | #define mem_mcsts 0x0024 /* memory controller status */ | |
202 | #define mem_rtr 0x0030 /* refresh timer register */ | |
203 | #define mem_pmit 0x0034 /* power management idle timer */ | |
204 | #define mem_uabba 0x0038 /* plb UABus base address */ | |
205 | #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */ | |
206 | #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */ | |
207 | #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */ | |
208 | #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */ | |
209 | #define mem_tr0 0x0080 /* sdram timing register 0 */ | |
210 | #define mem_tr1 0x0081 /* sdram timing register 1 */ | |
211 | #define mem_clktr 0x0082 /* ddr clock timing register */ | |
212 | #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */ | |
213 | #define mem_dlycal 0x0084 /* delay line calibration register */ | |
214 | #define mem_eccesr 0x0098 /* ECC error status */ | |
c00b5f85 WD |
215 | |
216 | /*----------------------------------------------------------------------------- | |
217 | | Extrnal Bus Controller | |
218 | +----------------------------------------------------------------------------*/ | |
219 | #define EBC_DCR_BASE 0x12 | |
220 | #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ | |
221 | #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ | |
ba56f625 WD |
222 | /* values for ebccfga register - indirect addressing of these regs */ |
223 | #define pb0cr 0x00 /* periph bank 0 config reg */ | |
224 | #define pb1cr 0x01 /* periph bank 1 config reg */ | |
225 | #define pb2cr 0x02 /* periph bank 2 config reg */ | |
226 | #define pb3cr 0x03 /* periph bank 3 config reg */ | |
227 | #define pb4cr 0x04 /* periph bank 4 config reg */ | |
228 | #define pb5cr 0x05 /* periph bank 5 config reg */ | |
229 | #define pb6cr 0x06 /* periph bank 6 config reg */ | |
230 | #define pb7cr 0x07 /* periph bank 7 config reg */ | |
231 | #define pb0ap 0x10 /* periph bank 0 access parameters */ | |
232 | #define pb1ap 0x11 /* periph bank 1 access parameters */ | |
233 | #define pb2ap 0x12 /* periph bank 2 access parameters */ | |
234 | #define pb3ap 0x13 /* periph bank 3 access parameters */ | |
235 | #define pb4ap 0x14 /* periph bank 4 access parameters */ | |
236 | #define pb5ap 0x15 /* periph bank 5 access parameters */ | |
237 | #define pb6ap 0x16 /* periph bank 6 access parameters */ | |
238 | #define pb7ap 0x17 /* periph bank 7 access parameters */ | |
239 | #define pbear 0x20 /* periph bus error addr reg */ | |
240 | #define pbesr 0x21 /* periph bus error status reg */ | |
241 | #define xbcfg 0x23 /* external bus configuration reg */ | |
242 | #define xbcid 0x23 /* external bus core id reg */ | |
c00b5f85 | 243 | |
c157d8e2 SR |
244 | #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) |
245 | ||
246 | /* PLB4 to PLB3 Bridge OUT */ | |
247 | #define P4P3_DCR_BASE 0x020 | |
248 | #define p4p3_esr0_read (P4P3_DCR_BASE+0x0) | |
249 | #define p4p3_esr0_write (P4P3_DCR_BASE+0x1) | |
250 | #define p4p3_eadr (P4P3_DCR_BASE+0x2) | |
251 | #define p4p3_euadr (P4P3_DCR_BASE+0x3) | |
252 | #define p4p3_esr1_read (P4P3_DCR_BASE+0x4) | |
253 | #define p4p3_esr1_write (P4P3_DCR_BASE+0x5) | |
254 | #define p4p3_confg (P4P3_DCR_BASE+0x6) | |
255 | #define p4p3_pic (P4P3_DCR_BASE+0x7) | |
256 | #define p4p3_peir (P4P3_DCR_BASE+0x8) | |
257 | #define p4p3_rev (P4P3_DCR_BASE+0xA) | |
258 | ||
259 | /* PLB3 to PLB4 Bridge IN */ | |
260 | #define P3P4_DCR_BASE 0x030 | |
261 | #define p3p4_esr0_read (P3P4_DCR_BASE+0x0) | |
262 | #define p3p4_esr0_write (P3P4_DCR_BASE+0x1) | |
263 | #define p3p4_eadr (P3P4_DCR_BASE+0x2) | |
264 | #define p3p4_euadr (P3P4_DCR_BASE+0x3) | |
265 | #define p3p4_esr1_read (P3P4_DCR_BASE+0x4) | |
266 | #define p3p4_esr1_write (P3P4_DCR_BASE+0x5) | |
267 | #define p3p4_confg (P3P4_DCR_BASE+0x6) | |
268 | #define p3p4_pic (P3P4_DCR_BASE+0x7) | |
269 | #define p3p4_peir (P3P4_DCR_BASE+0x8) | |
270 | #define p3p4_rev (P3P4_DCR_BASE+0xA) | |
271 | ||
272 | /* PLB3 Arbiter */ | |
273 | #define PLB3_DCR_BASE 0x070 | |
274 | #define plb3_revid (PLB3_DCR_BASE+0x2) | |
275 | #define plb3_besr (PLB3_DCR_BASE+0x3) | |
276 | #define plb3_bear (PLB3_DCR_BASE+0x6) | |
277 | #define plb3_acr (PLB3_DCR_BASE+0x7) | |
278 | ||
279 | /* PLB4 Arbiter - PowerPC440EP Pass1 */ | |
280 | #define PLB4_DCR_BASE 0x080 | |
281 | #define plb4_revid (PLB4_DCR_BASE+0x2) | |
282 | #define plb4_acr (PLB4_DCR_BASE+0x3) | |
283 | #define plb4_besr (PLB4_DCR_BASE+0x4) | |
284 | #define plb4_bearl (PLB4_DCR_BASE+0x6) | |
285 | #define plb4_bearh (PLB4_DCR_BASE+0x7) | |
286 | ||
287 | /* Nebula PLB4 Arbiter - PowerPC440EP */ | |
288 | #define PLB_ARBITER_BASE 0x80 | |
289 | ||
290 | #define plb0_revid (PLB_ARBITER_BASE+ 0x00) | |
291 | #define plb0_acr (PLB_ARBITER_BASE+ 0x01) | |
292 | #define plb0_acr_ppm_mask 0xF0000000 | |
293 | #define plb0_acr_ppm_fixed 0x00000000 | |
294 | #define plb0_acr_ppm_fair 0xD0000000 | |
295 | #define plb0_acr_hbu_mask 0x08000000 | |
296 | #define plb0_acr_hbu_disabled 0x00000000 | |
297 | #define plb0_acr_hbu_enabled 0x08000000 | |
298 | #define plb0_acr_rdp_mask 0x06000000 | |
299 | #define plb0_acr_rdp_disabled 0x00000000 | |
300 | #define plb0_acr_rdp_2deep 0x02000000 | |
301 | #define plb0_acr_rdp_3deep 0x04000000 | |
302 | #define plb0_acr_rdp_4deep 0x06000000 | |
303 | #define plb0_acr_wrp_mask 0x01000000 | |
304 | #define plb0_acr_wrp_disabled 0x00000000 | |
305 | #define plb0_acr_wrp_2deep 0x01000000 | |
306 | ||
307 | #define plb0_besrl (PLB_ARBITER_BASE+ 0x02) | |
308 | #define plb0_besrh (PLB_ARBITER_BASE+ 0x03) | |
309 | #define plb0_bearl (PLB_ARBITER_BASE+ 0x04) | |
310 | #define plb0_bearh (PLB_ARBITER_BASE+ 0x05) | |
311 | #define plb0_ccr (PLB_ARBITER_BASE+ 0x08) | |
312 | ||
313 | #define plb1_acr (PLB_ARBITER_BASE+ 0x09) | |
314 | #define plb1_acr_ppm_mask 0xF0000000 | |
315 | #define plb1_acr_ppm_fixed 0x00000000 | |
316 | #define plb1_acr_ppm_fair 0xD0000000 | |
317 | #define plb1_acr_hbu_mask 0x08000000 | |
318 | #define plb1_acr_hbu_disabled 0x00000000 | |
319 | #define plb1_acr_hbu_enabled 0x08000000 | |
320 | #define plb1_acr_rdp_mask 0x06000000 | |
321 | #define plb1_acr_rdp_disabled 0x00000000 | |
322 | #define plb1_acr_rdp_2deep 0x02000000 | |
323 | #define plb1_acr_rdp_3deep 0x04000000 | |
324 | #define plb1_acr_rdp_4deep 0x06000000 | |
325 | #define plb1_acr_wrp_mask 0x01000000 | |
326 | #define plb1_acr_wrp_disabled 0x00000000 | |
327 | #define plb1_acr_wrp_2deep 0x01000000 | |
328 | ||
329 | #define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) | |
330 | #define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) | |
331 | #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) | |
332 | #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) | |
333 | ||
334 | #else | |
335 | ||
c00b5f85 WD |
336 | /*----------------------------------------------------------------------------- |
337 | | Internal SRAM | |
338 | +----------------------------------------------------------------------------*/ | |
339 | #define ISRAM0_DCR_BASE 0x020 | |
ba56f625 WD |
340 | #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ |
341 | #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ | |
342 | #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ | |
343 | #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ | |
344 | #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ | |
345 | #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ | |
346 | #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ | |
347 | #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ | |
348 | #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ | |
349 | #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ | |
350 | #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ | |
351 | ||
352 | /*----------------------------------------------------------------------------- | |
353 | | L2 Cache | |
354 | +----------------------------------------------------------------------------*/ | |
355 | #if defined (CONFIG_440_GX) | |
356 | #define L2_CACHE_BASE 0x030 | |
357 | #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ | |
358 | #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ | |
359 | #define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */ | |
360 | #define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */ | |
361 | #define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */ | |
362 | #define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ | |
363 | #define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ | |
364 | #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ | |
365 | ||
366 | #endif /* CONFIG_440_GX */ | |
c157d8e2 | 367 | #endif /* !CONFIG_440_EP !CONFIG_440_GR*/ |
c00b5f85 WD |
368 | |
369 | /*----------------------------------------------------------------------------- | |
370 | | On-Chip Buses | |
371 | +----------------------------------------------------------------------------*/ | |
372 | /* TODO: as needed */ | |
373 | ||
374 | /*----------------------------------------------------------------------------- | |
375 | | Clocking, Power Management and Chip Control | |
376 | +----------------------------------------------------------------------------*/ | |
377 | #define CNTRL_DCR_BASE 0x0b0 | |
ba56f625 | 378 | #if defined (CONFIG_440_GX) |
63153492 WD |
379 | #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ |
380 | #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ | |
381 | #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ | |
ba56f625 | 382 | #else |
63153492 WD |
383 | #define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */ |
384 | #define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */ | |
385 | #define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */ | |
ba56f625 | 386 | #endif |
c00b5f85 | 387 | |
63153492 WD |
388 | #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ |
389 | #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ | |
390 | #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */ | |
391 | #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */ | |
c00b5f85 WD |
392 | |
393 | #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ | |
394 | #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ | |
395 | #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */ | |
396 | #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */ | |
397 | ||
63153492 WD |
398 | #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ |
399 | #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ | |
c00b5f85 WD |
400 | |
401 | /*----------------------------------------------------------------------------- | |
402 | | Universal interrupt controller | |
403 | +----------------------------------------------------------------------------*/ | |
404 | #define UIC0_DCR_BASE 0xc0 | |
ba56f625 WD |
405 | #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ |
406 | #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ | |
407 | #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ | |
408 | #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ | |
409 | #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ | |
410 | #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ | |
411 | #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ | |
412 | #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ | |
c00b5f85 WD |
413 | |
414 | #define UIC1_DCR_BASE 0xd0 | |
ba56f625 WD |
415 | #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ |
416 | #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ | |
417 | #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ | |
418 | #define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ | |
419 | #define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ | |
420 | #define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ | |
421 | #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ | |
422 | #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ | |
423 | ||
424 | #if defined(CONFIG_440_GX) | |
425 | #define UIC2_DCR_BASE 0x210 | |
426 | #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */ | |
427 | #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ | |
428 | #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ | |
429 | #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ | |
430 | #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ | |
431 | #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ | |
432 | #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ | |
433 | #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ | |
434 | ||
435 | ||
436 | #define UIC_DCR_BASE 0x200 | |
437 | #define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */ | |
438 | #define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */ | |
439 | #define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */ | |
440 | #define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */ | |
441 | #define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */ | |
442 | #define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */ | |
443 | #define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */ | |
444 | #define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */ | |
445 | #endif /* CONFIG_440_GX */ | |
c00b5f85 WD |
446 | |
447 | /* The following is for compatibility with 405 code */ | |
448 | #define uicsr uic0sr | |
449 | #define uicer uic0er | |
450 | #define uiccr uic0cr | |
451 | #define uicpr uic0pr | |
452 | #define uictr uic0tr | |
453 | #define uicmsr uic0msr | |
454 | #define uicvr uic0vr | |
455 | #define uicvcr uic0vcr | |
456 | ||
457 | /*----------------------------------------------------------------------------- | |
458 | | DMA | |
459 | +----------------------------------------------------------------------------*/ | |
460 | #define DMA_DCR_BASE 0x100 | |
ba56f625 WD |
461 | #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ |
462 | #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ | |
463 | #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */ | |
464 | #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */ | |
465 | #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */ | |
466 | #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */ | |
c00b5f85 WD |
467 | #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */ |
468 | #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */ | |
ba56f625 WD |
469 | #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ |
470 | #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ | |
471 | #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */ | |
472 | #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */ | |
473 | #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */ | |
474 | #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */ | |
c00b5f85 WD |
475 | #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */ |
476 | #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */ | |
ba56f625 WD |
477 | #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ |
478 | #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ | |
479 | #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */ | |
480 | #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */ | |
481 | #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */ | |
482 | #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */ | |
c00b5f85 WD |
483 | #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */ |
484 | #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */ | |
ba56f625 WD |
485 | #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ |
486 | #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */ | |
487 | #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */ | |
488 | #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */ | |
489 | #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */ | |
490 | #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */ | |
c00b5f85 WD |
491 | #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */ |
492 | #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */ | |
ba56f625 WD |
493 | #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ |
494 | #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ | |
495 | #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */ | |
496 | #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */ | |
c00b5f85 WD |
497 | |
498 | /*----------------------------------------------------------------------------- | |
499 | | Memory Access Layer | |
500 | +----------------------------------------------------------------------------*/ | |
501 | #define MAL_DCR_BASE 0x180 | |
ba56f625 WD |
502 | #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ |
503 | #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ | |
504 | #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ | |
505 | #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ | |
506 | #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ | |
c00b5f85 WD |
507 | #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ |
508 | #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ | |
ba56f625 WD |
509 | #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ |
510 | #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */ | |
511 | #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */ | |
512 | #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ | |
c00b5f85 WD |
513 | #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ |
514 | #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ | |
ba56f625 WD |
515 | #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ |
516 | #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */ | |
517 | #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */ | |
c00b5f85 WD |
518 | #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ |
519 | #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ | |
ba56f625 WD |
520 | #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ |
521 | #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */ | |
c00b5f85 WD |
522 | #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ |
523 | #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ | |
ba56f625 WD |
524 | #if defined(CONFIG_440_GX) |
525 | #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */ | |
526 | #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */ | |
527 | #endif /* CONFIG_440_GX */ | |
528 | #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ | |
529 | #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ | |
530 | #if defined(CONFIG_440_GX) | |
531 | #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ | |
532 | #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ | |
533 | #endif /* CONFIG_440_GX */ | |
534 | ||
c00b5f85 WD |
535 | |
536 | /*---------------------------------------------------------------------------+ | |
537 | | Universal interrupt controller 0 interrupts (UIC0) | |
538 | +---------------------------------------------------------------------------*/ | |
ba56f625 WD |
539 | #define UIC_U0 0x80000000 /* UART 0 */ |
540 | #define UIC_U1 0x40000000 /* UART 1 */ | |
541 | #define UIC_IIC0 0x20000000 /* IIC */ | |
542 | #define UIC_IIC1 0x10000000 /* IIC */ | |
543 | #define UIC_PIM 0x08000000 /* PCI inbound message */ | |
544 | #define UIC_PCRW 0x04000000 /* PCI command register write */ | |
545 | #define UIC_PPM 0x02000000 /* PCI power management */ | |
546 | #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ | |
547 | #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ | |
548 | #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ | |
549 | #define UIC_MTE 0x00200000 /* MAL TXEOB */ | |
550 | #define UIC_MRE 0x00100000 /* MAL RXEOB */ | |
551 | #define UIC_D0 0x00080000 /* DMA channel 0 */ | |
552 | #define UIC_D1 0x00040000 /* DMA channel 1 */ | |
553 | #define UIC_D2 0x00020000 /* DMA channel 2 */ | |
554 | #define UIC_D3 0x00010000 /* DMA channel 3 */ | |
555 | #define UIC_RSVD0 0x00008000 /* Reserved */ | |
556 | #define UIC_RSVD1 0x00004000 /* Reserved */ | |
557 | #define UIC_CT0 0x00002000 /* GPT compare timer 0 */ | |
558 | #define UIC_CT1 0x00001000 /* GPT compare timer 1 */ | |
559 | #define UIC_CT2 0x00000800 /* GPT compare timer 2 */ | |
560 | #define UIC_CT3 0x00000400 /* GPT compare timer 3 */ | |
561 | #define UIC_CT4 0x00000200 /* GPT compare timer 4 */ | |
562 | #define UIC_EIR0 0x00000100 /* External interrupt 0 */ | |
563 | #define UIC_EIR1 0x00000080 /* External interrupt 1 */ | |
564 | #define UIC_EIR2 0x00000040 /* External interrupt 2 */ | |
565 | #define UIC_EIR3 0x00000020 /* External interrupt 3 */ | |
566 | #define UIC_EIR4 0x00000010 /* External interrupt 4 */ | |
567 | #define UIC_EIR5 0x00000008 /* External interrupt 5 */ | |
568 | #define UIC_EIR6 0x00000004 /* External interrupt 6 */ | |
569 | #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ | |
570 | #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ | |
c00b5f85 WD |
571 | |
572 | /* For compatibility with 405 code */ | |
ba56f625 WD |
573 | #define UIC_MAL_TXEOB UIC_MTE |
574 | #define UIC_MAL_RXEOB UIC_MRE | |
c00b5f85 WD |
575 | |
576 | /*---------------------------------------------------------------------------+ | |
577 | | Universal interrupt controller 1 interrupts (UIC1) | |
578 | +---------------------------------------------------------------------------*/ | |
ba56f625 WD |
579 | #define UIC_MS 0x80000000 /* MAL SERR */ |
580 | #define UIC_MTDE 0x40000000 /* MAL TXDE */ | |
581 | #define UIC_MRDE 0x20000000 /* MAL RXDE */ | |
582 | #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ | |
583 | #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ | |
584 | #define UIC_EBCO 0x04000000 /* EBCO interrupt status */ | |
585 | #define UIC_EBMI 0x02000000 /* EBMI interrupt status */ | |
586 | #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ | |
587 | #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ | |
588 | #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ | |
589 | #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ | |
590 | #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ | |
591 | #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ | |
592 | #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ | |
593 | #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ | |
594 | #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ | |
595 | #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ | |
596 | #define UIC_PPMI 0x00004000 /* PPM interrupt status */ | |
597 | #define UIC_EIR7 0x00002000 /* External interrupt 7 */ | |
598 | #define UIC_EIR8 0x00001000 /* External interrupt 8 */ | |
599 | #define UIC_EIR9 0x00000800 /* External interrupt 9 */ | |
600 | #define UIC_EIR10 0x00000400 /* External interrupt 10 */ | |
601 | #define UIC_EIR11 0x00000200 /* External interrupt 11 */ | |
602 | #define UIC_EIR12 0x00000100 /* External interrupt 12 */ | |
603 | #define UIC_SRE 0x00000080 /* Serial ROM error */ | |
604 | #define UIC_RSVD2 0x00000040 /* Reserved */ | |
605 | #define UIC_RSVD3 0x00000020 /* Reserved */ | |
606 | #define UIC_PAE 0x00000010 /* PCI asynchronous error */ | |
607 | #define UIC_ETH0 0x00000008 /* Ethernet 0 */ | |
608 | #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ | |
609 | #define UIC_ETH1 0x00000002 /* Ethernet 1 */ | |
610 | #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ | |
c00b5f85 WD |
611 | |
612 | /* For compatibility with 405 code */ | |
ba56f625 WD |
613 | #define UIC_MAL_SERR UIC_MS |
614 | #define UIC_MAL_TXDE UIC_MTDE | |
615 | #define UIC_MAL_RXDE UIC_MRDE | |
616 | #define UIC_ENET UIC_ETH0 | |
617 | ||
618 | /*---------------------------------------------------------------------------+ | |
619 | | Universal interrupt controller 2 interrupts (UIC2) | |
620 | +---------------------------------------------------------------------------*/ | |
621 | #if defined(CONFIG_440_GX) | |
622 | #define UIC_ETH2 0x80000000 /* Ethernet 2 */ | |
623 | #define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */ | |
624 | #define UIC_ETH3 0x20000000 /* Ethernet 3 */ | |
625 | #define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */ | |
626 | #define UIC_TAH0 0x08000000 /* TAH 0 */ | |
627 | #define UIC_TAH1 0x04000000 /* TAH 1 */ | |
628 | #define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */ | |
629 | #define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */ | |
630 | #define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */ | |
631 | #define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */ | |
632 | #define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */ | |
633 | #define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */ | |
634 | #define UIC_IMUTO 0x00080000 /* IMU timeout */ | |
635 | #define UIC_MSI12 0x00040000 /* PCI MSI level 12 */ | |
636 | #define UIC_MSI13 0x00020000 /* PCI MSI level 13 */ | |
637 | #define UIC_MSI14 0x00010000 /* PCI MSI level 14 */ | |
638 | #define UIC_MSI15 0x00008000 /* PCI MSI level 15 */ | |
639 | #define UIC_EIR13 0x00004000 /* External interrupt 13 */ | |
640 | #define UIC_EIR14 0x00002000 /* External interrupt 14 */ | |
641 | #define UIC_EIR15 0x00001000 /* External interrupt 15 */ | |
642 | #define UIC_EIR16 0x00000800 /* External interrupt 16 */ | |
643 | #define UIC_EIR17 0x00000400 /* External interrupt 17 */ | |
644 | #define UIC_PCIVPD 0x00000200 /* PCI VPD */ | |
645 | #define UIC_L2C 0x00000100 /* L2 Cache */ | |
646 | #define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */ | |
647 | #define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */ | |
648 | #define UIC_RSVD26 0x00000020 /* Reserved */ | |
649 | #define UIC_RSVD27 0x00000010 /* Reserved */ | |
650 | #define UIC_RSVD28 0x00000008 /* Reserved */ | |
651 | #define UIC_RSVD29 0x00000004 /* Reserved */ | |
652 | #define UIC_RSVD30 0x00000002 /* Reserved */ | |
653 | #define UIC_RSVD31 0x00000001 /* Reserved */ | |
654 | #endif /* CONFIG_440_GX */ | |
655 | ||
656 | /*---------------------------------------------------------------------------+ | |
657 | | Universal interrupt controller Base 0 interrupts (UICB0) | |
658 | +---------------------------------------------------------------------------*/ | |
659 | #if defined(CONFIG_440_GX) | |
660 | #define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */ | |
661 | #define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */ | |
662 | #define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */ | |
663 | #define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */ | |
664 | #define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */ | |
665 | #define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */ | |
666 | ||
667 | #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ | |
668 | UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) | |
669 | #endif /* CONFIG_440_GX */ | |
c00b5f85 | 670 | |
0e6d798c WD |
671 | /*-----------------------------------------------------------------------------+ |
672 | | External Bus Controller Bit Settings | |
673 | +-----------------------------------------------------------------------------*/ | |
63153492 WD |
674 | #define EBC_CFGADDR_MASK 0x0000003F |
675 | ||
676 | #define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) | |
677 | #define EBC_BXCR_BS_MASK 0x000E0000 | |
678 | #define EBC_BXCR_BS_1MB 0x00000000 | |
679 | #define EBC_BXCR_BS_2MB 0x00020000 | |
680 | #define EBC_BXCR_BS_4MB 0x00040000 | |
681 | #define EBC_BXCR_BS_8MB 0x00060000 | |
682 | #define EBC_BXCR_BS_16MB 0x00080000 | |
683 | #define EBC_BXCR_BS_32MB 0x000A0000 | |
684 | #define EBC_BXCR_BS_64MB 0x000C0000 | |
685 | #define EBC_BXCR_BS_128MB 0x000E0000 | |
686 | #define EBC_BXCR_BU_MASK 0x00018000 | |
687 | #define EBC_BXCR_BU_R 0x00008000 | |
688 | #define EBC_BXCR_BU_W 0x00010000 | |
689 | #define EBC_BXCR_BU_RW 0x00018000 | |
690 | #define EBC_BXCR_BW_MASK 0x00006000 | |
691 | #define EBC_BXCR_BW_8BIT 0x00000000 | |
692 | #define EBC_BXCR_BW_16BIT 0x00002000 | |
693 | ||
694 | #define EBC_BXAP_BME_ENABLED 0x80000000 | |
695 | #define EBC_BXAP_BME_DISABLED 0x00000000 | |
696 | #define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) | |
697 | #define EBC_BXAP_BCE_DISABLE 0x00000000 | |
698 | #define EBC_BXAP_BCE_ENABLE 0x00400000 | |
699 | #define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) | |
700 | #define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) | |
701 | #define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) | |
702 | #define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) | |
703 | #define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) | |
704 | #define EBC_BXAP_RE_ENABLED 0x00000100 | |
705 | #define EBC_BXAP_RE_DISABLED 0x00000000 | |
706 | #define EBC_BXAP_SOR_DELAYED 0x00000000 | |
707 | #define EBC_BXAP_SOR_NONDELAYED 0x00000080 | |
708 | #define EBC_BXAP_BEM_WRITEONLY 0x00000000 | |
709 | #define EBC_BXAP_BEM_RW 0x00000040 | |
710 | #define EBC_BXAP_PEN_DISABLED 0x00000000 | |
711 | ||
712 | #define EBC_CFG_LE_MASK 0x80000000 | |
713 | #define EBC_CFG_LE_UNLOCK 0x00000000 | |
714 | #define EBC_CFG_LE_LOCK 0x80000000 | |
715 | #define EBC_CFG_PTD_MASK 0x40000000 | |
716 | #define EBC_CFG_PTD_ENABLE 0x00000000 | |
717 | #define EBC_CFG_PTD_DISABLE 0x40000000 | |
718 | #define EBC_CFG_RTC_MASK 0x38000000 | |
719 | #define EBC_CFG_RTC_16PERCLK 0x00000000 | |
720 | #define EBC_CFG_RTC_32PERCLK 0x08000000 | |
721 | #define EBC_CFG_RTC_64PERCLK 0x10000000 | |
722 | #define EBC_CFG_RTC_128PERCLK 0x18000000 | |
723 | #define EBC_CFG_RTC_256PERCLK 0x20000000 | |
724 | #define EBC_CFG_RTC_512PERCLK 0x28000000 | |
725 | #define EBC_CFG_RTC_1024PERCLK 0x30000000 | |
726 | #define EBC_CFG_RTC_2048PERCLK 0x38000000 | |
727 | #define EBC_CFG_ATC_MASK 0x04000000 | |
728 | #define EBC_CFG_ATC_HI 0x00000000 | |
729 | #define EBC_CFG_ATC_PREVIOUS 0x04000000 | |
730 | #define EBC_CFG_DTC_MASK 0x02000000 | |
731 | #define EBC_CFG_DTC_HI 0x00000000 | |
732 | #define EBC_CFG_DTC_PREVIOUS 0x02000000 | |
733 | #define EBC_CFG_CTC_MASK 0x01000000 | |
734 | #define EBC_CFG_CTC_HI 0x00000000 | |
735 | #define EBC_CFG_CTC_PREVIOUS 0x01000000 | |
736 | #define EBC_CFG_OEO_MASK 0x00800000 | |
737 | #define EBC_CFG_OEO_HI 0x00000000 | |
738 | #define EBC_CFG_OEO_PREVIOUS 0x00800000 | |
739 | #define EBC_CFG_EMC_MASK 0x00400000 | |
740 | #define EBC_CFG_EMC_NONDEFAULT 0x00000000 | |
741 | #define EBC_CFG_EMC_DEFAULT 0x00400000 | |
742 | #define EBC_CFG_PME_MASK 0x00200000 | |
743 | #define EBC_CFG_PME_DISABLE 0x00000000 | |
744 | #define EBC_CFG_PME_ENABLE 0x00200000 | |
745 | #define EBC_CFG_PMT_MASK 0x001F0000 | |
746 | #define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) | |
747 | #define EBC_CFG_PR_MASK 0x0000C000 | |
748 | #define EBC_CFG_PR_16 0x00000000 | |
749 | #define EBC_CFG_PR_32 0x00004000 | |
750 | #define EBC_CFG_PR_64 0x00008000 | |
751 | #define EBC_CFG_PR_128 0x0000C000 | |
0e6d798c WD |
752 | |
753 | /*-----------------------------------------------------------------------------+ | |
754 | | SDR 0 Bit Settings | |
755 | +-----------------------------------------------------------------------------*/ | |
63153492 WD |
756 | #define SDR0_SDSTP0_ENG_MASK 0x80000000 |
757 | #define SDR0_SDSTP0_ENG_PLLDIS 0x00000000 | |
758 | #define SDR0_SDSTP0_ENG_PLLENAB 0x80000000 | |
759 | #define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | |
760 | #define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | |
761 | #define SDR0_SDSTP0_SRC_MASK 0x40000000 | |
762 | #define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000 | |
763 | #define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000 | |
764 | #define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | |
765 | #define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | |
766 | #define SDR0_SDSTP0_SEL_MASK 0x38000000 | |
767 | #define SDR0_SDSTP0_SEL_PLLOUT 0x00000000 | |
768 | #define SDR0_SDSTP0_SEL_CPU 0x08000000 | |
769 | #define SDR0_SDSTP0_SEL_EBC 0x28000000 | |
770 | #define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27) | |
771 | #define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07) | |
772 | #define SDR0_SDSTP0_TUNE_MASK 0x07FE0000 | |
773 | #define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17) | |
774 | #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF) | |
775 | #define SDR0_SDSTP0_FBDV_MASK 0x0001F000 | |
776 | #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) | |
777 | #define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1) | |
778 | #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00 | |
779 | #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8) | |
780 | #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1) | |
781 | #define SDR0_SDSTP0_FWDVB_MASK 0x000000E0 | |
782 | #define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5) | |
783 | #define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1) | |
784 | #define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C | |
785 | #define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2) | |
786 | #define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1) | |
787 | #define SDR0_SDSTP0_OPBDV0_MASK 0x00000003 | |
788 | #define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0) | |
789 | #define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1) | |
790 | ||
791 | #define SDR0_SDSTP1_LFBDV_MASK 0xFC000000 | |
792 | #define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26) | |
793 | #define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F) | |
794 | #define SDR0_SDSTP1_EBCDV0_MASK 0x03000000 | |
795 | #define SDR0_SDSTP1_EBCDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) | |
796 | #define SDR0_SDSTP1_EBCDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03) | |
797 | #define SDR0_SDSTP1_MALDV0_MASK 0x00C00000 | |
798 | #define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22) | |
799 | #define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03) | |
800 | #define SDR0_SDSTP1_RW_MASK 0x00300000 | |
801 | #define SDR0_SDSTP1_RW_8BIT 0x00000000 | |
802 | #define SDR0_SDSTP1_RW_16BIT 0x00100000 | |
803 | #define SDR0_SDSTP1_RW_32BIT 0x00200000 | |
804 | #define SDR0_SDSTP1_RW_ENCODE(n) ((((unsigned long)(n))&0x03)<<20) | |
805 | #define SDR0_SDSTP1_RW_DECODE(n) ((((unsigned long)(n))>>20)&0x03) | |
806 | #define SDR0_SDSTP1_EARV_MASK 0x00080000 | |
807 | #define SDR0_SDSTP1_EARV_EBC 0x00000000 | |
808 | #define SDR0_SDSTP1_EARV_PCI 0x00080000 | |
809 | #define SDR0_SDSTP1_PAE_MASK 0x00040000 | |
810 | #define SDR0_SDSTP1_PAE_DISABLE 0x00000000 | |
811 | #define SDR0_SDSTP1_PAE_ENABLE 0x00040000 | |
812 | #define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) | |
813 | #define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) | |
814 | #define SDR0_SDSTP1_PHCE_MASK 0x00020000 | |
815 | #define SDR0_SDSTP1_PHCE_DISABLE 0x00000000 | |
816 | #define SDR0_SDSTP1_PHCE_ENABLE 0x00020000 | |
817 | #define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) | |
818 | #define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) | |
819 | #define SDR0_SDSTP1_PISE_MASK 0x00010000 | |
820 | #define SDR0_SDSTP1_PISE_DISABLE 0x00000000 | |
821 | #define SDR0_SDSTP1_PISE_ENABLE 0x00010000 | |
822 | #define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) | |
823 | #define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) | |
824 | #define SDR0_SDSTP1_PCWE_MASK 0x00008000 | |
825 | #define SDR0_SDSTP1_PCWE_DISABLE 0x00000000 | |
826 | #define SDR0_SDSTP1_PCWE_ENABLE 0x00008000 | |
827 | #define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) | |
828 | #define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) | |
829 | #define SDR0_SDSTP1_PPIM_MASK 0x00008000 | |
830 | #define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) | |
831 | #define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) | |
832 | #define SDR0_SDSTP1_PR64E_MASK 0x00000400 | |
833 | #define SDR0_SDSTP1_PR64E_DISABLE 0x00000000 | |
834 | #define SDR0_SDSTP1_PR64E_ENABLE 0x00000400 | |
835 | #define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10) | |
836 | #define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01) | |
837 | #define SDR0_SDSTP1_PXFS_MASK 0x00000300 | |
838 | #define SDR0_SDSTP1_PXFS_HIGH 0x00000000 | |
839 | #define SDR0_SDSTP1_PXFS_MED 0x00000100 | |
840 | #define SDR0_SDSTP1_PXFS_LOW 0x00000200 | |
841 | #define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) | |
842 | #define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) | |
843 | #define SDR0_SDSTP1_PDM_MASK 0x00000040 | |
844 | #define SDR0_SDSTP1_PDM_MULTIPOINT 0x00000000 | |
845 | #define SDR0_SDSTP1_PDM_P2P 0x00000040 | |
846 | #define SDR0_SDSTP1_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<6) | |
847 | #define SDR0_SDSTP1_PDM_DECODE(n) ((((unsigned long)(n))>>6)&0x01) | |
848 | #define SDR0_SDSTP1_EPS_MASK 0x00000038 | |
849 | #define SDR0_SDSTP1_EPS_GROUP0 0x00000000 | |
850 | #define SDR0_SDSTP1_EPS_GROUP1 0x00000008 | |
851 | #define SDR0_SDSTP1_EPS_GROUP2 0x00000010 | |
852 | #define SDR0_SDSTP1_EPS_GROUP3 0x00000018 | |
853 | #define SDR0_SDSTP1_EPS_GROUP4 0x00000020 | |
854 | #define SDR0_SDSTP1_EPS_GROUP5 0x00000028 | |
855 | #define SDR0_SDSTP1_EPS_GROUP6 0x00000030 | |
856 | #define SDR0_SDSTP1_EPS_GROUP7 0x00000038 | |
857 | #define SDR0_SDSTP1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<3) | |
858 | #define SDR0_SDSTP1_EPS_DECODE(n) ((((unsigned long)(n))>>3)&0x07) | |
859 | #define SDR0_SDSTP1_RMII_MASK 0x00000004 | |
860 | #define SDR0_SDSTP1_RMII_100MBIT 0x00000000 | |
861 | #define SDR0_SDSTP1_RMII_10MBIT 0x00000004 | |
862 | #define SDR0_SDSTP1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<2) | |
863 | #define SDR0_SDSTP1_RMII_DECODE(n) ((((unsigned long)(n))>>2)&0x01) | |
864 | #define SDR0_SDSTP1_TRE_MASK 0x00000002 | |
865 | #define SDR0_SDSTP1_TRE_DISABLE 0x00000000 | |
866 | #define SDR0_SDSTP1_TRE_ENABLE 0x00000002 | |
867 | #define SDR0_SDSTP1_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) | |
868 | #define SDR0_SDSTP1_TRE_DECODE(n) ((((unsigned long)(n))>>1)&0x01) | |
869 | #define SDR0_SDSTP1_NTO1_MASK 0x00000001 | |
870 | #define SDR0_SDSTP1_NTO1_DISABLE 0x00000000 | |
871 | #define SDR0_SDSTP1_NTO1_ENABLE 0x00000001 | |
872 | #define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0) | |
873 | #define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01) | |
874 | ||
875 | #define SDR0_EBC_RW_MASK 0x30000000 | |
876 | #define SDR0_EBC_RW_8BIT 0x00000000 | |
877 | #define SDR0_EBC_RW_16BIT 0x10000000 | |
878 | #define SDR0_EBC_RW_32BIT 0x20000000 | |
879 | #define SDR0_EBC_RW_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) | |
880 | #define SDR0_EBC_RW_DECODE(n) ((((unsigned long)(n))>>28)&0x03) | |
881 | ||
882 | #define SDR0_UARTX_UXICS_MASK 0xF0000000 | |
883 | #define SDR0_UARTX_UXICS_PLB 0x20000000 | |
884 | #define SDR0_UARTX_UXEC_MASK 0x00800000 | |
885 | #define SDR0_UARTX_UXEC_INT 0x00000000 | |
886 | #define SDR0_UARTX_UXEC_EXT 0x00800000 | |
887 | #define SDR0_UARTX_UXDTE_MASK 0x00400000 | |
888 | #define SDR0_UARTX_UXDTE_DISABLE 0x00000000 | |
889 | #define SDR0_UARTX_UXDTE_ENABLE 0x00400000 | |
890 | #define SDR0_UARTX_UXDRE_MASK 0x00200000 | |
891 | #define SDR0_UARTX_UXDRE_DISABLE 0x00000000 | |
892 | #define SDR0_UARTX_UXDRE_ENABLE 0x00200000 | |
893 | #define SDR0_UARTX_UXDC_MASK 0x00100000 | |
894 | #define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000 | |
895 | #define SDR0_UARTX_UXDC_CLEARED 0x00100000 | |
896 | #define SDR0_UARTX_UXDIV_MASK 0x000000FF | |
897 | #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) | |
898 | #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) | |
899 | ||
900 | #define SDR0_CPU440_EARV_MASK 0x30000000 | |
901 | #define SDR0_CPU440_EARV_EBC 0x10000000 | |
902 | #define SDR0_CPU440_EARV_PCI 0x20000000 | |
903 | #define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) | |
904 | #define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03) | |
905 | #define SDR0_CPU440_NTO1_MASK 0x00000002 | |
906 | #define SDR0_CPU440_NTO1_NTOP 0x00000000 | |
907 | #define SDR0_CPU440_NTO1_NTO1 0x00000002 | |
908 | #define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) | |
909 | #define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) | |
910 | ||
911 | #define SDR0_XCR_PAE_MASK 0x80000000 | |
912 | #define SDR0_XCR_PAE_DISABLE 0x00000000 | |
913 | #define SDR0_XCR_PAE_ENABLE 0x80000000 | |
914 | #define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | |
915 | #define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | |
916 | #define SDR0_XCR_PHCE_MASK 0x40000000 | |
917 | #define SDR0_XCR_PHCE_DISABLE 0x00000000 | |
918 | #define SDR0_XCR_PHCE_ENABLE 0x40000000 | |
919 | #define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | |
920 | #define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | |
921 | #define SDR0_XCR_PISE_MASK 0x20000000 | |
922 | #define SDR0_XCR_PISE_DISABLE 0x00000000 | |
923 | #define SDR0_XCR_PISE_ENABLE 0x20000000 | |
924 | #define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | |
925 | #define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | |
926 | #define SDR0_XCR_PCWE_MASK 0x10000000 | |
927 | #define SDR0_XCR_PCWE_DISABLE 0x00000000 | |
928 | #define SDR0_XCR_PCWE_ENABLE 0x10000000 | |
929 | #define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) | |
930 | #define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) | |
931 | #define SDR0_XCR_PPIM_MASK 0x0F000000 | |
932 | #define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) | |
933 | #define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | |
934 | #define SDR0_XCR_PR64E_MASK 0x00800000 | |
935 | #define SDR0_XCR_PR64E_DISABLE 0x00000000 | |
936 | #define SDR0_XCR_PR64E_ENABLE 0x00800000 | |
937 | #define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) | |
938 | #define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) | |
939 | #define SDR0_XCR_PXFS_MASK 0x00600000 | |
940 | #define SDR0_XCR_PXFS_HIGH 0x00000000 | |
941 | #define SDR0_XCR_PXFS_MED 0x00200000 | |
942 | #define SDR0_XCR_PXFS_LOW 0x00400000 | |
943 | #define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) | |
944 | #define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) | |
945 | #define SDR0_XCR_PDM_MASK 0x00000040 | |
946 | #define SDR0_XCR_PDM_MULTIPOINT 0x00000000 | |
947 | #define SDR0_XCR_PDM_P2P 0x00000040 | |
948 | #define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19) | |
949 | #define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01) | |
0e6d798c WD |
950 | |
951 | #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000 | |
63153492 WD |
952 | #define SDR0_PFC0_GEIE_MASK 0x00003E00 |
953 | #define SDR0_PFC0_GEIE_TRE 0x00003E00 | |
954 | #define SDR0_PFC0_GEIE_NOTRE 0x00000000 | |
955 | #define SDR0_PFC0_TRE_MASK 0x00000100 | |
956 | #define SDR0_PFC0_TRE_DISABLE 0x00000000 | |
957 | #define SDR0_PFC0_TRE_ENABLE 0x00000100 | |
958 | #define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) | |
959 | #define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) | |
960 | ||
961 | #define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000 | |
962 | #define SDR0_PFC1_EPS_MASK 0x01C00000 | |
963 | #define SDR0_PFC1_EPS_GROUP0 0x00000000 | |
964 | #define SDR0_PFC1_EPS_GROUP1 0x00400000 | |
965 | #define SDR0_PFC1_EPS_GROUP2 0x00800000 | |
966 | #define SDR0_PFC1_EPS_GROUP3 0x00C00000 | |
967 | #define SDR0_PFC1_EPS_GROUP4 0x01000000 | |
968 | #define SDR0_PFC1_EPS_GROUP5 0x01400000 | |
969 | #define SDR0_PFC1_EPS_GROUP6 0x01800000 | |
970 | #define SDR0_PFC1_EPS_GROUP7 0x01C00000 | |
971 | #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) | |
972 | #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) | |
973 | #define SDR0_PFC1_RMII_MASK 0x00200000 | |
974 | #define SDR0_PFC1_RMII_100MBIT 0x00000000 | |
975 | #define SDR0_PFC1_RMII_10MBIT 0x00200000 | |
976 | #define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21) | |
977 | #define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01) | |
978 | #define SDR0_PFC1_CTEMS_MASK 0x00100000 | |
979 | #define SDR0_PFC1_CTEMS_EMS 0x00000000 | |
980 | #define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000 | |
981 | ||
982 | #define SDR0_MFR_TAH0_MASK 0x80000000 | |
983 | #define SDR0_MFR_TAH0_ENABLE 0x00000000 | |
984 | #define SDR0_MFR_TAH0_DISABLE 0x80000000 | |
985 | #define SDR0_MFR_TAH1_MASK 0x40000000 | |
986 | #define SDR0_MFR_TAH1_ENABLE 0x00000000 | |
987 | #define SDR0_MFR_TAH1_DISABLE 0x40000000 | |
988 | #define SDR0_MFR_PCM_MASK 0x20000000 | |
989 | #define SDR0_MFR_PCM_PPC440GX 0x00000000 | |
990 | #define SDR0_MFR_PCM_PPC440GP 0x20000000 | |
991 | #define SDR0_MFR_ECS_MASK 0x10000000 | |
992 | #define SDR0_MFR_ECS_INTERNAL 0x10000000 | |
993 | ||
c157d8e2 SR |
994 | #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ |
995 | #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ | |
996 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | |
997 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | |
998 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | |
999 | #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ | |
1000 | #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ | |
1001 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | |
1002 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | |
1003 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | |
1004 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | |
1005 | #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ | |
1006 | #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */ | |
1007 | #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ | |
1008 | #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ | |
1009 | #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ | |
1010 | ||
63153492 WD |
1011 | #define SDR0_SRST_BGO 0x80000000 |
1012 | #define SDR0_SRST_PLB 0x40000000 | |
1013 | #define SDR0_SRST_EBC 0x20000000 | |
1014 | #define SDR0_SRST_OPB 0x10000000 | |
1015 | #define SDR0_SRST_UART0 0x08000000 | |
1016 | #define SDR0_SRST_UART1 0x04000000 | |
1017 | #define SDR0_SRST_IIC0 0x02000000 | |
1018 | #define SDR0_SRST_IIC1 0x01000000 | |
1019 | #define SDR0_SRST_GPIO 0x00800000 | |
1020 | #define SDR0_SRST_GPT 0x00400000 | |
1021 | #define SDR0_SRST_DMC 0x00200000 | |
1022 | #define SDR0_SRST_PCI 0x00100000 | |
1023 | #define SDR0_SRST_EMAC0 0x00080000 | |
1024 | #define SDR0_SRST_EMAC1 0x00040000 | |
1025 | #define SDR0_SRST_CPM 0x00020000 | |
1026 | #define SDR0_SRST_IMU 0x00010000 | |
1027 | #define SDR0_SRST_UIC01 0x00008000 | |
1028 | #define SDR0_SRST_UICB2 0x00004000 | |
1029 | #define SDR0_SRST_SRAM 0x00002000 | |
1030 | #define SDR0_SRST_EBM 0x00001000 | |
1031 | #define SDR0_SRST_BGI 0x00000800 | |
1032 | #define SDR0_SRST_DMA 0x00000400 | |
1033 | #define SDR0_SRST_DMAC 0x00000200 | |
1034 | #define SDR0_SRST_MAL 0x00000100 | |
1035 | #define SDR0_SRST_ZMII 0x00000080 | |
1036 | #define SDR0_SRST_GPTR 0x00000040 | |
1037 | #define SDR0_SRST_PPM 0x00000020 | |
1038 | #define SDR0_SRST_EMAC2 0x00000010 | |
1039 | #define SDR0_SRST_EMAC3 0x00000008 | |
1040 | #define SDR0_SRST_RGMII 0x00000001 | |
0e6d798c | 1041 | |
c00b5f85 WD |
1042 | /*-----------------------------------------------------------------------------+ |
1043 | | Clocking | |
1044 | +-----------------------------------------------------------------------------*/ | |
c157d8e2 | 1045 | #if !defined (CONFIG_440_GX) && !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR) |
ba56f625 WD |
1046 | #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ |
1047 | #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ | |
1048 | #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ | |
1049 | #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */ | |
1050 | #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */ | |
1051 | #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ | |
1052 | #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ | |
1053 | #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */ | |
1054 | #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */ | |
1055 | #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */ | |
1056 | #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */ | |
1057 | #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ | |
1058 | ||
1059 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ | |
1060 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ | |
1061 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ | |
1062 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ | |
c157d8e2 | 1063 | #else /* !CONFIG_440_GX or CONFIG_440_EP or CONFIG_440_GR */ |
ba56f625 WD |
1064 | #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ |
1065 | #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ | |
1066 | #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ | |
1067 | #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ | |
1068 | #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ | |
1069 | #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ | |
1070 | #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ | |
1071 | #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ | |
1072 | #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ | |
1073 | ||
c157d8e2 SR |
1074 | #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ |
1075 | #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ | |
1076 | #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ | |
1077 | #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ | |
1078 | #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ | |
1079 | #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ | |
1080 | ||
1081 | #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ | |
1082 | #define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ | |
1083 | #define PRADV_MASK 0x07000000 /* Primary Divisor A */ | |
1084 | #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ | |
1085 | #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ | |
1086 | ||
ba56f625 WD |
1087 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ |
1088 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ | |
1089 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ | |
1090 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ | |
1091 | ||
1092 | /* Strap 1 Register */ | |
1093 | #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ | |
1094 | #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ | |
1095 | #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ | |
1096 | #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ | |
1097 | #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ | |
1098 | #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ | |
1099 | #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ | |
1100 | #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ | |
1101 | #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ | |
1102 | #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ | |
1103 | #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ | |
1104 | #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ | |
1105 | #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ | |
1106 | #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ | |
1107 | #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ | |
1108 | #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ | |
1109 | #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ | |
1110 | #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ | |
1111 | #endif /* CONFIG_440_GX */ | |
c00b5f85 WD |
1112 | |
1113 | /*----------------------------------------------------------------------------- | |
1114 | | IIC Register Offsets | |
1115 | '----------------------------------------------------------------------------*/ | |
63153492 WD |
1116 | #define IICMDBUF 0x00 |
1117 | #define IICSDBUF 0x02 | |
1118 | #define IICLMADR 0x04 | |
1119 | #define IICHMADR 0x05 | |
1120 | #define IICCNTL 0x06 | |
1121 | #define IICMDCNTL 0x07 | |
1122 | #define IICSTS 0x08 | |
1123 | #define IICEXTSTS 0x09 | |
1124 | #define IICLSADR 0x0A | |
1125 | #define IICHSADR 0x0B | |
1126 | #define IICCLKDIV 0x0C | |
1127 | #define IICINTRMSK 0x0D | |
1128 | #define IICXFRCNT 0x0E | |
1129 | #define IICXTCNTLSS 0x0F | |
1130 | #define IICDIRECTCNTL 0x10 | |
c00b5f85 WD |
1131 | |
1132 | /*----------------------------------------------------------------------------- | |
1133 | | UART Register Offsets | |
1134 | '----------------------------------------------------------------------------*/ | |
63153492 WD |
1135 | #define DATA_REG 0x00 |
1136 | #define DL_LSB 0x00 | |
1137 | #define DL_MSB 0x01 | |
1138 | #define INT_ENABLE 0x01 | |
1139 | #define FIFO_CONTROL 0x02 | |
1140 | #define LINE_CONTROL 0x03 | |
1141 | #define MODEM_CONTROL 0x04 | |
1142 | #define LINE_STATUS 0x05 | |
1143 | #define MODEM_STATUS 0x06 | |
1144 | #define SCRATCH 0x07 | |
c00b5f85 WD |
1145 | |
1146 | /*----------------------------------------------------------------------------- | |
1147 | | PCI Internal Registers et. al. (accessed via plb) | |
1148 | +----------------------------------------------------------------------------*/ | |
0e6d798c WD |
1149 | #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000) |
1150 | #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004) | |
1151 | #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000) | |
1152 | #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000) | |
1153 | ||
c157d8e2 SR |
1154 | #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) |
1155 | ||
1156 | /* PCI Local Configuration Registers | |
1157 | --------------------------------- */ | |
1158 | #define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */ | |
1159 | ||
1160 | /* PCI Master Local Configuration Registers */ | |
1161 | #define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ | |
1162 | #define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ | |
1163 | #define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ | |
1164 | #define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ | |
1165 | #define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ | |
1166 | #define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ | |
1167 | #define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ | |
1168 | #define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ | |
1169 | #define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ | |
1170 | #define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ | |
1171 | #define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ | |
1172 | #define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ | |
1173 | ||
1174 | /* PCI Target Local Configuration Registers */ | |
1175 | #define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */ | |
1176 | #define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ | |
1177 | #define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */ | |
1178 | #define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ | |
1179 | ||
1180 | #else | |
1181 | ||
0e6d798c WD |
1182 | #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID ) |
1183 | #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID ) | |
1184 | #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND ) | |
1185 | #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS ) | |
1186 | #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID ) | |
1187 | #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE) | |
1188 | #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE ) | |
1189 | #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER ) | |
1190 | #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE ) | |
1191 | #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST ) | |
1192 | #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 ) | |
1193 | #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 ) | |
1194 | #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 ) | |
1195 | #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 ) | |
1196 | #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 ) | |
1197 | #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 ) | |
1198 | #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS ) | |
1199 | #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) | |
1200 | #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID ) | |
1201 | #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS ) | |
1202 | #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST ) | |
1203 | #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 ) | |
1204 | #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 ) | |
1205 | #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 ) | |
1206 | #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE ) | |
1207 | #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN ) | |
1208 | #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT ) | |
1209 | #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT ) | |
1210 | ||
63153492 WD |
1211 | #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040) |
1212 | #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044) | |
0e6d798c WD |
1213 | |
1214 | #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068) | |
1215 | #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c) | |
1216 | #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070) | |
63153492 WD |
1217 | #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074) |
1218 | #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078) | |
0e6d798c WD |
1219 | #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c) |
1220 | #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080) | |
1221 | #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084) | |
63153492 WD |
1222 | #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088) |
1223 | #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c) | |
0e6d798c WD |
1224 | #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090) |
1225 | ||
1226 | #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098) | |
1227 | #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c) | |
1228 | #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0) | |
1229 | #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4) | |
1230 | #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8) | |
1231 | #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac) | |
1232 | #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0) | |
1233 | #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4) | |
1234 | #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8) | |
1235 | ||
1236 | #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0) | |
c00b5f85 | 1237 | |
c157d8e2 SR |
1238 | #endif /* !defined(CONFIG_440_EP) !defined(CONFIG_440_GR) */ |
1239 | ||
1240 | /****************************************************************************** | |
1241 | * GPIO macro register defines | |
1242 | ******************************************************************************/ | |
1243 | #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) | |
1244 | #define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00) | |
1245 | #define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00) | |
1246 | ||
1247 | #define GPIO0_OR (GPIO_BASE0+0x0) | |
1248 | #define GPIO0_TCR (GPIO_BASE0+0x4) | |
1249 | #define GPIO0_OSRL (GPIO_BASE0+0x8) | |
1250 | #define GPIO0_OSRH (GPIO_BASE0+0xC) | |
1251 | #define GPIO0_TSRL (GPIO_BASE0+0x10) | |
1252 | #define GPIO0_TSRH (GPIO_BASE0+0x14) | |
1253 | #define GPIO0_ODR (GPIO_BASE0+0x18) | |
1254 | #define GPIO0_IR (GPIO_BASE0+0x1C) | |
1255 | #define GPIO0_RR1 (GPIO_BASE0+0x20) | |
1256 | #define GPIO0_RR2 (GPIO_BASE0+0x24) | |
1257 | #define GPIO0_RR3 (GPIO_BASE0+0x28) | |
1258 | #define GPIO0_ISR1L (GPIO_BASE0+0x30) | |
1259 | #define GPIO0_ISR1H (GPIO_BASE0+0x34) | |
1260 | #define GPIO0_ISR2L (GPIO_BASE0+0x38) | |
1261 | #define GPIO0_ISR2H (GPIO_BASE0+0x3C) | |
1262 | #define GPIO0_ISR3L (GPIO_BASE0+0x40) | |
1263 | #define GPIO0_ISR3H (GPIO_BASE0+0x44) | |
1264 | ||
1265 | #define GPIO1_OR (GPIO_BASE1+0x0) | |
1266 | #define GPIO1_TCR (GPIO_BASE1+0x4) | |
1267 | #define GPIO1_OSRL (GPIO_BASE1+0x8) | |
1268 | #define GPIO1_OSRH (GPIO_BASE1+0xC) | |
1269 | #define GPIO1_TSRL (GPIO_BASE1+0x10) | |
1270 | #define GPIO1_TSRH (GPIO_BASE1+0x14) | |
1271 | #define GPIO1_ODR (GPIO_BASE1+0x18) | |
1272 | #define GPIO1_IR (GPIO_BASE1+0x1C) | |
1273 | #define GPIO1_RR1 (GPIO_BASE1+0x20) | |
1274 | #define GPIO1_RR2 (GPIO_BASE1+0x24) | |
1275 | #define GPIO1_RR3 (GPIO_BASE1+0x28) | |
1276 | #define GPIO1_ISR1L (GPIO_BASE1+0x30) | |
1277 | #define GPIO1_ISR1H (GPIO_BASE1+0x34) | |
1278 | #define GPIO1_ISR2L (GPIO_BASE1+0x38) | |
1279 | #define GPIO1_ISR2H (GPIO_BASE1+0x3C) | |
1280 | #define GPIO1_ISR3L (GPIO_BASE1+0x40) | |
1281 | #define GPIO1_ISR3H (GPIO_BASE1+0x44) | |
1282 | #endif | |
1283 | ||
c00b5f85 WD |
1284 | /* |
1285 | * Macros for accessing the indirect EBC registers | |
1286 | */ | |
63153492 WD |
1287 | #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) |
1288 | #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) | |
c00b5f85 WD |
1289 | |
1290 | /* | |
1291 | * Macros for accessing the indirect SDRAM controller registers | |
1292 | */ | |
63153492 WD |
1293 | #define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) |
1294 | #define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd) | |
c00b5f85 | 1295 | |
ba56f625 WD |
1296 | /* |
1297 | * Macros for accessing the indirect clocking controller registers | |
1298 | */ | |
63153492 WD |
1299 | #define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data) |
1300 | #define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd) | |
ba56f625 WD |
1301 | |
1302 | /* | |
1303 | * Macros for accessing the sdr controller registers | |
1304 | */ | |
63153492 WD |
1305 | #define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data) |
1306 | #define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd) | |
ba56f625 | 1307 | |
c00b5f85 WD |
1308 | |
1309 | #ifndef __ASSEMBLY__ | |
1310 | ||
63153492 WD |
1311 | typedef struct { |
1312 | unsigned long pllFwdDivA; | |
1313 | unsigned long pllFwdDivB; | |
1314 | unsigned long pllFbkDiv; | |
1315 | unsigned long pllOpbDiv; | |
c157d8e2 | 1316 | unsigned long pllPciDiv; |
63153492 WD |
1317 | unsigned long pllExtBusDiv; |
1318 | unsigned long freqVCOMhz; /* in MHz */ | |
1319 | unsigned long freqProcessor; | |
c157d8e2 | 1320 | unsigned long freqTmrClk; |
63153492 WD |
1321 | unsigned long freqPLB; |
1322 | unsigned long freqOPB; | |
1323 | unsigned long freqEPB; | |
c157d8e2 SR |
1324 | unsigned long freqPCI; |
1325 | unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ | |
1326 | unsigned long pciClkSync; /* PCI clock is synchronous */ | |
c00b5f85 WD |
1327 | } PPC440_SYS_INFO; |
1328 | ||
ba56f625 | 1329 | #endif /* _ASMLANGUAGE */ |
c00b5f85 | 1330 | |
63153492 WD |
1331 | #define RESET_VECTOR 0xfffffffc |
1332 | #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */ | |
1333 | /* cache line aligned data. */ | |
c00b5f85 WD |
1334 | |
1335 | #endif /* __PPC440_H__ */ |