[people/ms/u-boot.git] / include / ppc_asm.tmpl

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * This file contains all the macros and symbols which define
 * a PowerPC assembly language environment.
 */
#ifndef	__PPC_ASM_TMPL__
#define __PPC_ASM_TMPL__

/***************************************************************************
 *
 * These definitions simplify the ugly declarations necessary for GOT
 * definitions.
 *
 * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
 *
 * Uses r12 to access the GOT
 */

#define START_GOT			\
	.section	".got2","aw";	\
.LCTOC1 = .+32768

#define END_GOT				\
	.text

#define GET_GOT				\
	bl	1f		;	\
	.text	2		;	\
0:	.long	.LCTOC1-1f	;	\
	.text			;	\
1:	mflr	r12		;	\
	lwz	r0,0b-1b(r12)	;	\
	add	r12,r0,r12	;

#define GOT_ENTRY(NAME)		.L_ ## NAME = . - .LCTOC1 ; .long NAME

#define GOT(NAME)		.L_ ## NAME (r12)


/***************************************************************************
 * Register names
 */
#define	r0	0
#define	r1	1
#define	r2	2
#define	r3	3
#define	r4	4
#define	r5	5
#define	r6	6
#define	r7	7
#define	r8	8
#define	r9	9
#define	r10	10
#define	r11	11
#define	r12	12
#define	r13	13
#define	r14	14
#define	r15	15
#define	r16	16
#define	r17	17
#define	r18	18
#define	r19	19
#define	r20	20
#define	r21	21
#define	r22	22
#define	r23	23
#define	r24	24
#define	r25	25
#define	r26	26
#define	r27	27
#define	r28	28
#define	r29	29
#define	r30	30
#define	r31	31


#if defined(CONFIG_8xx)

/* Some special registers */

#define ICR	148	/* Interrupt Cause Register (37-44) */
#define DER	149
#define COUNTA	150	/* Breakpoint Counter	    (37-44) */
#define COUNTB	151	/* Breakpoint Counter	    (37-44) */
#define LCTRL1	156	/* Load/Store Support	    (37-40) */
#define LCTRL2	157	/* Load/Store Support	    (37-41) */
#define ICTRL	158

#endif	/* CONFIG_8xx */


#if  defined(CONFIG_5xx)
/* Some special purpose registers */
#define DER	149		/* Debug Enable Register		*/
#define COUNTA	150		/* Breakpoint Counter			*/
#define COUNTB	151		/* Breakpoint Counter			*/
#define LCTRL1	156		/* Load/Store Support			*/
#define LCTRL2	157		/* Load/Store Support			*/
#define ICTRL	158		/* I-Bus Support Control Register	*/
#define EID	81
#endif	/* CONFIG_5xx */

#if defined(CONFIG_8xx)

/* Registers in the processor's internal memory map that we use.
*/
#define SYPCR	0x00000004
#define BR0	0x00000100
#define OR0	0x00000104
#define BR1	0x00000108
#define OR1	0x0000010c
#define BR2	0x00000110
#define OR2	0x00000114
#define BR3	0x00000118
#define OR3	0x0000011c
#define BR4	0x00000120
#define OR4	0x00000124

#define MAR	0x00000164
#define MCR	0x00000168
#define MAMR	0x00000170
#define MBMR	0x00000174
#define MSTAT	0x00000178
#define MPTPR	0x0000017a
#define MDR	0x0000017c

#define TBSCR	0x00000200
#define TBREFF0	0x00000204

#define PLPRCR	0x00000284

#elif defined(CONFIG_MPC8260)

#define HID2		1011

#define HID0_IFEM	(1<<7)

#define HID0_ICE_BITPOS	16
#define HID0_DCE_BITPOS	17

#define IM_REGBASE	0x10000
#define IM_SYPCR	(IM_REGBASE+0x0004)
#define IM_SWSR		(IM_REGBASE+0x000e)
#define IM_BR0		(IM_REGBASE+0x0100)
#define IM_OR0		(IM_REGBASE+0x0104)
#define IM_BR1		(IM_REGBASE+0x0108)
#define IM_OR1		(IM_REGBASE+0x010c)
#define IM_BR2		(IM_REGBASE+0x0110)
#define IM_OR2		(IM_REGBASE+0x0114)
#define IM_MPTPR	(IM_REGBASE+0x0184)
#define IM_PSDMR	(IM_REGBASE+0x0190)
#define IM_PSRT		(IM_REGBASE+0x019c)
#define IM_IMMR		(IM_REGBASE+0x01a8)
#define IM_SCCR		(IM_REGBASE+0x0c80)

#elif defined(CONFIG_MPC5xxx)

#define HID0_ICE_BITPOS	16
#define HID0_DCE_BITPOS	17

#endif

#define curptr r2

#define SYNC \
	sync; \
	isync

/*
 * Macros for storing registers into and loading registers from
 * exception frames.
 */
#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)

/*
 * GCC sometimes accesses words at negative offsets from the stack
 * pointer, although the SysV ABI says it shouldn't.  To cope with
 * this, we leave this much untouched space on the stack on exception
 * entry.
 */
#define STACK_UNDERHEAD	64

/*
 * Exception entry code.  This code runs with address translation
 * turned off, i.e. using physical addresses.
 * We assume sprg3 has the physical address of the current
 * task's thread_struct.
 */
#define EXCEPTION_PROLOG(reg1, reg2)	\
	mtspr	SPRG0,r20;	\
	mtspr	SPRG1,r21;	\
	mfcr	r20;		\
	subi	r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD;	/* alloc exc. frame */\
	stw	r20,_CCR(r21);		/* save registers */ \
	stw	r22,GPR22(r21);	\
	stw	r23,GPR23(r21);	\
	mfspr	r20,SPRG0;	\
	stw	r20,GPR20(r21);	\
	mfspr	r22,SPRG1;	\
	stw	r22,GPR21(r21);	\
	mflr	r20;		\
	stw	r20,_LINK(r21);	\
	mfctr	r22;		\
	stw	r22,_CTR(r21);	\
	mfspr	r20,XER;	\
	stw	r20,_XER(r21);	\
	mfspr	r20, DAR_DEAR;	\
	stw	r20,_DAR(r21);	\
	mfspr	r22,reg1;	\
	mfspr	r23,reg2;	\
	stw	r0,GPR0(r21);	\
	stw	r1,GPR1(r21);	\
	stw	r2,GPR2(r21);	\
	stw	r1,0(r21);	\
	mr	r1,r21;			/* set new kernel sp */	\
	SAVE_4GPRS(3, r21);
/*
 * Note: code which follows this uses cr0.eq (set if from kernel),
 * r21, r22 (SRR0), and r23 (SRR1).
 */

/*
 * Exception vectors.
 *
 * The data words for `hdlr' and `int_return' are initialized with
 * OFFSET values only; they must be relocated first before they can
 * be used!
 */
#define COPY_EE(d, s)		rlwimi d,s,0,16,16
#define NOCOPY(d, s)
#define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee)	\
	bl	1f;					\
1:	mflr    r20;					\
	lwz	r20,(.L_ ## label)-1b+8(r20);		\
	mtlr	r20;					\
	li	r20,msr;				\
	copyee(r20,r23);				\
	rlwimi	r20,r23,0,25,25;			\
	blrl;						\
.L_ ## label :						\
	.long	hdlr - _start + _START_OFFSET;		\
	.long	int_return - _start + _START_OFFSET;	\
	.long	transfer_to_handler - _start + _START_OFFSET

#define STD_EXCEPTION(n, label, hdlr)				\
	. = n;							\
label:								\
	EXCEPTION_PROLOG(SRR0, SRR1);				\
	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
	EXC_XFER_TEMPLATE(label, hdlr, MSR_KERNEL, NOCOPY)	\

#define CRIT_EXCEPTION(n, label, hdlr)				\
	. = n;							\
label:								\
	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
	EXC_XFER_TEMPLATE(label, hdlr,				\
	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\

#define MCK_EXCEPTION(n, label, hdlr)				\
	. = n;							\
label:								\
	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
	EXC_XFER_TEMPLATE(label, hdlr,				\
	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\

#endif	/* __PPC_ASM_TMPL__ */
Commit	Line	Data
d62589d5 WD	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
d62589d5 WD	6	*/
	7
	8	/*
	9	* This file contains all the macros and symbols which define
	10	* a PowerPC assembly language environment.
	11	*/
	12	#ifndef __PPC_ASM_TMPL__
	13	#define __PPC_ASM_TMPL__
	14
	15	/***************************************************************************
	16	*
	17	* These definitions simplify the ugly declarations necessary for GOT
	18	* definitions.
	19	*
	20	* Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
	21	*
161e4ae4	22	* Uses r12 to access the GOT
d62589d5 WD	23	*/
	24
	25	#define START_GOT \
	26	.section ".got2","aw"; \
	27	.LCTOC1 = .+32768
	28
	29	#define END_GOT \
	30	.text
	31
	32	#define GET_GOT \
	33	bl 1f ; \
	34	.text 2 ; \
	35	0: .long .LCTOC1-1f ; \
	36	.text ; \
0f8aa159 JT	37	1: mflr r12 ; \
	38	lwz r0,0b-1b(r12) ; \
	39	add r12,r0,r12 ;
d62589d5 WD	40
	41	#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME
	42
0f8aa159	43	#define GOT(NAME) .L_ ## NAME (r12)
d62589d5 WD	44
	45
	46	/***************************************************************************
	47	* Register names
	48	*/
	49	#define r0 0
	50	#define r1 1
	51	#define r2 2
	52	#define r3 3
	53	#define r4 4
	54	#define r5 5
	55	#define r6 6
	56	#define r7 7
	57	#define r8 8
	58	#define r9 9
	59	#define r10 10
	60	#define r11 11
	61	#define r12 12
	62	#define r13 13
	63	#define r14 14
	64	#define r15 15
	65	#define r16 16
	66	#define r17 17
	67	#define r18 18
	68	#define r19 19
	69	#define r20 20
	70	#define r21 21
	71	#define r22 22
	72	#define r23 23
	73	#define r24 24
	74	#define r25 25
	75	#define r26 26
	76	#define r27 27
	77	#define r28 28
	78	#define r29 29
	79	#define r30 30
	80	#define r31 31
	81
	82
d622ac39	83	#if defined(CONFIG_8xx)
d62589d5 WD	84
	85	/* Some special registers */
	86
	87	#define ICR 148 /* Interrupt Cause Register (37-44) */
	88	#define DER 149
	89	#define COUNTA 150 /* Breakpoint Counter (37-44) */
	90	#define COUNTB 151 /* Breakpoint Counter (37-44) */
	91	#define LCTRL1 156 /* Load/Store Support (37-40) */
	92	#define LCTRL2 157 /* Load/Store Support (37-41) */
	93	#define ICTRL 158
	94
d622ac39	95	#endif /* CONFIG_8xx */
d62589d5	96
0db5bca8 WD	97
	98	#if defined(CONFIG_5xx)
	99	/* Some special purpose registers */
83b4cfa3 WD	100	#define DER 149 /* Debug Enable Register */
	101	#define COUNTA 150 /* Breakpoint Counter */
	102	#define COUNTB 151 /* Breakpoint Counter */
	103	#define LCTRL1 156 /* Load/Store Support */
	104	#define LCTRL2 157 /* Load/Store Support */
0db5bca8 WD	105	#define ICTRL 158 /* I-Bus Support Control Register */
	106	#define EID 81
	107	#endif /* CONFIG_5xx */
	108
d62589d5 WD	109	#if defined(CONFIG_8xx)
	110
	111	/* Registers in the processor's internal memory map that we use.
	112	*/
	113	#define SYPCR 0x00000004
	114	#define BR0 0x00000100
	115	#define OR0 0x00000104
	116	#define BR1 0x00000108
	117	#define OR1 0x0000010c
	118	#define BR2 0x00000110
	119	#define OR2 0x00000114
	120	#define BR3 0x00000118
	121	#define OR3 0x0000011c
	122	#define BR4 0x00000120
	123	#define OR4 0x00000124
	124
	125	#define MAR 0x00000164
	126	#define MCR 0x00000168
	127	#define MAMR 0x00000170
	128	#define MBMR 0x00000174
	129	#define MSTAT 0x00000178
	130	#define MPTPR 0x0000017a
	131	#define MDR 0x0000017c
	132
	133	#define TBSCR 0x00000200
	134	#define TBREFF0 0x00000204
	135
	136	#define PLPRCR 0x00000284
	137
58dac327	138	#elif defined(CONFIG_MPC8260)
d62589d5 WD	139
	140	#define HID2 1011
	141
	142	#define HID0_IFEM (1<<7)
	143
	144	#define HID0_ICE_BITPOS 16
	145	#define HID0_DCE_BITPOS 17
	146
	147	#define IM_REGBASE 0x10000
	148	#define IM_SYPCR (IM_REGBASE+0x0004)
	149	#define IM_SWSR (IM_REGBASE+0x000e)
	150	#define IM_BR0 (IM_REGBASE+0x0100)
	151	#define IM_OR0 (IM_REGBASE+0x0104)
	152	#define IM_BR1 (IM_REGBASE+0x0108)
	153	#define IM_OR1 (IM_REGBASE+0x010c)
	154	#define IM_BR2 (IM_REGBASE+0x0110)
	155	#define IM_OR2 (IM_REGBASE+0x0114)
	156	#define IM_MPTPR (IM_REGBASE+0x0184)
	157	#define IM_PSDMR (IM_REGBASE+0x0190)
	158	#define IM_PSRT (IM_REGBASE+0x019c)
	159	#define IM_IMMR (IM_REGBASE+0x01a8)
	160	#define IM_SCCR (IM_REGBASE+0x0c80)
	161
d6ed3222	162	#elif defined(CONFIG_MPC5xxx)
945af8d7 WD	163
	164	#define HID0_ICE_BITPOS 16
	165	#define HID0_DCE_BITPOS 17
	166
d62589d5 WD	167	#endif
	168
	169	#define curptr r2
	170
	171	#define SYNC \
	172	sync; \
	173	isync
	174
	175	/*
	176	* Macros for storing registers into and loading registers from
	177	* exception frames.
	178	*/
	179	#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
	180	#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
	181	#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
	182	#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
	183	#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
	184	#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
	185	#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
	186	#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
	187	#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
	188	#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
	189
	190	/*
	191	* GCC sometimes accesses words at negative offsets from the stack
	192	* pointer, although the SysV ABI says it shouldn't. To cope with
	193	* this, we leave this much untouched space on the stack on exception
	194	* entry.
	195	*/
	196	#define STACK_UNDERHEAD 64
	197
	198	/*
	199	* Exception entry code. This code runs with address translation
	200	* turned off, i.e. using physical addresses.
	201	* We assume sprg3 has the physical address of the current
	202	* task's thread_struct.
	203	*/
efa35cf1	204	#define EXCEPTION_PROLOG(reg1, reg2) \
d62589d5 WD	205	mtspr SPRG0,r20; \
	206	mtspr SPRG1,r21; \
	207	mfcr r20; \
	208	subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
	209	stw r20,_CCR(r21); /* save registers */ \
	210	stw r22,GPR22(r21); \
	211	stw r23,GPR23(r21); \
	212	mfspr r20,SPRG0; \
	213	stw r20,GPR20(r21); \
	214	mfspr r22,SPRG1; \
	215	stw r22,GPR21(r21); \
	216	mflr r20; \
	217	stw r20,_LINK(r21); \
	218	mfctr r22; \
	219	stw r22,_CTR(r21); \
	220	mfspr r20,XER; \
	221	stw r20,_XER(r21); \
cc3023b9	222	mfspr r20, DAR_DEAR; \
efa35cf1 GB	223	stw r20,_DAR(r21); \
	224	mfspr r22,reg1; \
	225	mfspr r23,reg2; \
d62589d5 WD	226	stw r0,GPR0(r21); \
	227	stw r1,GPR1(r21); \
	228	stw r2,GPR2(r21); \
	229	stw r1,0(r21); \
	230	mr r1,r21; /* set new kernel sp */ \
	231	SAVE_4GPRS(3, r21);
	232	/*
	233	* Note: code which follows this uses cr0.eq (set if from kernel),
	234	* r21, r22 (SRR0), and r23 (SRR1).
	235	*/
	236
d62589d5 WD	237	/*
	238	* Exception vectors.
	239	*
	240	* The data words for `hdlr' and `int_return' are initialized with
	241	* OFFSET values only; they must be relocated first before they can
	242	* be used!
	243	*/
fc4e1887 JT	244	#define COPY_EE(d, s) rlwimi d,s,0,16,16
	245	#define NOCOPY(d, s)
	246	#define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee) \
	247	bl 1f; \
	248	1: mflr r20; \
	249	lwz r20,(.L_ ## label)-1b+8(r20); \
	250	mtlr r20; \
	251	li r20,msr; \
	252	copyee(r20,r23); \
d62589d5	253	rlwimi r20,r23,0,25,25; \
83b4cfa3	254	blrl; \
d62589d5	255	.L_ ## label : \
efa35cf1	256	.long hdlr - _start + _START_OFFSET; \
fc4e1887 JT	257	.long int_return - _start + _START_OFFSET; \
	258	.long transfer_to_handler - _start + _START_OFFSET
	259
	260	#define STD_EXCEPTION(n, label, hdlr) \
	261	. = n; \
	262	label: \
	263	EXCEPTION_PROLOG(SRR0, SRR1); \
	264	addi r3,r1,STACK_FRAME_OVERHEAD; \
	265	EXC_XFER_TEMPLATE(label, hdlr, MSR_KERNEL, NOCOPY) \
efa35cf1 GB	266
efa35cf1 GB	267	#define CRIT_EXCEPTION(n, label, hdlr) \
83b4cfa3	268	. = n; \
efa35cf1	269	label: \
02032e8f	270	EXCEPTION_PROLOG(CSRR0, CSRR1); \
83b4cfa3	271	addi r3,r1,STACK_FRAME_OVERHEAD; \
fc4e1887 JT	272	EXC_XFER_TEMPLATE(label, hdlr, \
fc4e1887 JT	273	MSR_KERNEL & ~(MSR_ME\|MSR_DE\|MSR_CE), NOCOPY) \
efa35cf1	274
efa35cf1	275	#define MCK_EXCEPTION(n, label, hdlr) \
83b4cfa3	276	. = n; \
efa35cf1	277	label: \
83b4cfa3	278	EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
83b4cfa3	279	addi r3,r1,STACK_FRAME_OVERHEAD; \
fc4e1887 JT	280	EXC_XFER_TEMPLATE(label, hdlr, \
fc4e1887 JT	281	MSR_KERNEL & ~(MSR_ME\|MSR_DE\|MSR_CE), NOCOPY) \
d62589d5 WD	282
d62589d5 WD	283	#endif /* __PPC_ASM_TMPL__ */