projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 067f54c6 MF |
1 | /* |
| 2 | * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu> | |
| 3 | * | |
| 4 | * SJA1000 register layout for basic CAN mode | |
| 5 | * | |
| 6 | * See file CREDITS for list of people who contributed to this | |
| 7 | * project. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of | |
| 12 | * the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 22 | * MA 02111-1307 USA | |
| 23 | */ | |
| 24 | ||
| 25 | #ifndef _SJA1000_H_ | |
| 26 | #define _SJA1000_H_ | |
| 27 | ||
| 28 | /* | |
| 29 | * SJA1000 register layout in basic can mode | |
| 30 | */ | |
| 31 | struct sja1000_basic_s { | |
| 32 | u8 cr; | |
| 33 | u8 cmr; | |
| 34 | u8 sr; | |
| 35 | u8 ir; | |
| 36 | u8 ac; | |
| 37 | u8 am; | |
| 38 | u8 btr0; | |
| 39 | u8 btr1; | |
| 40 | u8 oc; | |
| 41 | u8 txb[10]; | |
| 42 | u8 rxb[10]; | |
| 43 | u8 unused; | |
| 44 | u8 cdr; | |
| 45 | }; | |
| 46 | ||
| 47 | /* control register */ | |
| 48 | #define CR_RR 0x01 | |
| 49 | ||
| 50 | /* output control register */ | |
| 51 | #define OC_MODE0 0x01 | |
| 52 | #define OC_MODE1 0x02 | |
| 53 | #define OC_POL0 0x04 | |
| 54 | #define OC_TN0 0x08 | |
| 55 | #define OC_TP0 0x10 | |
| 56 | #define OC_POL1 0x20 | |
| 57 | #define OC_TN1 0x40 | |
| 58 | #define OC_TP1 0x80 | |
| 59 | ||
| 60 | #endif |