]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/spartan2.h
powerpc/mpc85xx:Avoid fix address of bootpg section
[people/ms/u-boot.git] / include / spartan2.h
CommitLineData
c609719b
WD
1/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
c609719b
WD
6 */
7
8#ifndef _SPARTAN2_H_
9#define _SPARTAN2_H_
10
11#include <xilinx.h>
12
e6a857da
WD
13extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size);
14extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
15extern int Spartan2_info(Xilinx_desc *desc);
c609719b
WD
16
17/* Slave Parallel Implementation function table */
18typedef struct {
19 Xilinx_pre_fn pre;
20 Xilinx_pgm_fn pgm;
21 Xilinx_init_fn init;
22 Xilinx_err_fn err;
23 Xilinx_done_fn done;
24 Xilinx_clk_fn clk;
25 Xilinx_cs_fn cs;
26 Xilinx_wr_fn wr;
27 Xilinx_rdata_fn rdata;
28 Xilinx_wdata_fn wdata;
29 Xilinx_busy_fn busy;
30 Xilinx_abort_fn abort;
31 Xilinx_post_fn post;
c609719b
WD
32} Xilinx_Spartan2_Slave_Parallel_fns;
33
34/* Slave Serial Implementation function table */
35typedef struct {
7f6c2cbc 36 Xilinx_pre_fn pre;
c609719b
WD
37 Xilinx_pgm_fn pgm;
38 Xilinx_clk_fn clk;
7f6c2cbc
WD
39 Xilinx_init_fn init;
40 Xilinx_done_fn done;
41 Xilinx_wr_fn wr;
21d39d59 42 Xilinx_post_fn post;
c609719b
WD
43} Xilinx_Spartan2_Slave_Serial_fns;
44
45/* Device Image Sizes
46 *********************************************************************/
47/* Spartan-II (2.5V) */
53677ef1
WD
48#define XILINX_XC2S15_SIZE 197728/8
49#define XILINX_XC2S30_SIZE 336800/8
50#define XILINX_XC2S50_SIZE 559232/8
51#define XILINX_XC2S100_SIZE 781248/8
52#define XILINX_XC2S150_SIZE 1040128/8
53#define XILINX_XC2S200_SIZE 1335872/8
c609719b 54
9dd611b8
WD
55/* Spartan-IIE (1.8V) */
56#define XILINX_XC2S50E_SIZE 630048/8
57#define XILINX_XC2S100E_SIZE 863840/8
58#define XILINX_XC2S150E_SIZE 1134496/8
59#define XILINX_XC2S200E_SIZE 1442016/8
60#define XILINX_XC2S300E_SIZE 1875648/8
61
c609719b
WD
62/* Descriptor Macros
63 *********************************************************************/
64/* Spartan-II devices */
65#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
66{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
67
68#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
69{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
70
71#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
72{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
73
74#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
75{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
76
77#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
78{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
79
3bff4ffa
MF
80#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
81{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
82
9dd611b8
WD
83#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
84{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
85
86#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
87{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
88
89#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
90{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
91
92#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
93{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
94
95#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
96{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
97
c609719b 98#endif /* _SPARTAN2_H_ */