[people/ms/u-boot.git] / include / vsc9953.h

/*
 *  vsc9953.h
 *
 *  Driver for the Vitesse VSC9953 L2 Switch
 *
 *  This software may be used and distributed according to the
 *  terms of the GNU Public License, Version 2, incorporated
 *  herein by reference.
 *
 * Copyright 2013  Freescale Semiconductor, Inc.
 *
 */

#ifndef _VSC9953_H_
#define _VSC9953_H_

#include <config.h>
#include <miiphy.h>
#include <asm/types.h>

#define VSC9953_OFFSET			(CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)

#define VSC9953_SYS_OFFSET		0x010000
#define VSC9953_DEV_GMII_OFFSET		0x100000
#define VSC9953_QSYS_OFFSET		0x200000
#define VSC9953_ANA_OFFSET		0x280000
#define VSC9953_DEVCPU_GCB		0x070000
#define VSC9953_ES0			0x040000
#define VSC9953_IS1			0x050000
#define VSC9953_IS2			0x060000

#define T1040_SWITCH_GMII_DEV_OFFSET	0x010000
#define VSC9953_PHY_REGS_OFFST		0x0000AC

/* Macros for vsc9953_chip_regs.soft_rst register */
#define VSC9953_SOFT_SWC_RST_ENA	0x00000001

/* Macros for vsc9953_sys_sys.reset_cfg register */
#define VSC9953_CORE_ENABLE		0x80
#define VSC9953_MEM_ENABLE		0x40
#define VSC9953_MEM_INIT		0x20

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
#define VSC9953_MAC_ENA_CFG		0x00000011

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
#define VSC9953_MAC_MODE_CFG		0x00000011

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
#define VSC9953_MAC_IFG_CFG		0x00000515

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
#define VSC9953_MAC_HDX_CFG		0x00001043

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
#define VSC9953_MAC_MAX_LEN		0x000005ee

/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
#define VSC9953_CLOCK_CFG		0x00000001
#define VSC9953_CLOCK_CFG_1000M		0x00000001

/* Macros for vsc9953_sys_sys.front_port_mode register */
#define VSC9953_FRONT_PORT_MODE	0x00000000

/* Macros for vsc9953_ana_pfc.pfc_cfg register */
#define VSC9953_PFC_FC			0x00000001
#define VSC9953_PFC_FC_QSGMII		0x00000000

/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
#define VSC9953_MAC_FC_CFG		0x04700000
#define VSC9953_MAC_FC_CFG_QSGMII	0x00700000

/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
#define VSC9953_PAUSE_CFG		0x001ffffe

/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
#define VSC9953_TOT_TAIL_DROP_LVL	0x000003ff

/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
#define VSC9953_VCAP_MV_CFG		0x0000ffff
#define VSC9953_VCAP_UPDATE_CTRL	0x01000004

/* Macros for vsc9953_qsys_sys.switch_port_mode register */
#define VSC9953_PORT_ENA		0x00003a00

#define VSC9953_MAX_PORTS		10
#define VSC9953_PORT_CHECK(port)	\
	(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
	( \
		(port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
	) ? 0 : 1 \
)

#define DEFAULT_VSC9953_MDIO_NAME	"VSC9953_MDIO0"

#define MIIMIND_OPR_PEND		0x00000004

struct vsc9953_mdio_info {
	struct vsc9953_mii_mng	*regs;
	char	*name;
};

/* VSC9953 ANA structure */

struct vsc9953_ana_port {
	u32	vlan_cfg;
	u32	drop_cfg;
	u32	qos_cfg;
	u32	vcap_cfg;
	u32	vcap_s1_key_cfg[3];
	u32	vcap_s2_cfg;
	u32	qos_pcp_dei_map_cfg[16];
	u32	cpu_fwd_cfg;
	u32	cpu_fwd_bpdu_cfg;
	u32	cpu_fwd_garp_cfg;
	u32	cpu_fwd_ccm_cfg;
	u32	port_cfg;
	u32	pol_cfg;
	u32	reserved[34];
};

struct vsc9953_ana_pol {
	u32	pol_pir_cfg;
	u32	pol_cir_cfg;
	u32	pol_mode_cfg;
	u32	pol_pir_state;
	u32	pol_cir_state;
	u32	reserved1[3];
};

struct vsc9953_ana_ana_tables {
	u32	entry_lim[11];
	u32	an_moved;
	u32	mach_data;
	u32	macl_data;
	u32	mac_access;
	u32	mact_indx;
	u32	vlan_access;
	u32	vlan_tidx;
};

struct vsc9953_ana_ana {
	u32	adv_learn;
	u32	vlan_mask;
	u32	anag_efil;
	u32	an_events;
	u32	storm_limit_burst;
	u32	storm_limit_cfg[4];
	u32	isolated_prts;
	u32	community_ports;
	u32	auto_age;
	u32	mac_options;
	u32	learn_disc;
	u32	agen_ctrl;
	u32	mirror_ports;
	u32	emirror_ports;
	u32	flooding;
	u32	flooding_ipmc;
	u32	sflow_cfg[11];
	u32	port_mode[12];
};

struct vsc9953_ana_pgid {
	u32	port_grp_id[91];
};

struct vsc9953_ana_pfc {
	u32	pfc_cfg;
	u32	reserved1[15];
};

struct vsc9953_ana_pol_misc {
	u32	pol_flowc[10];
	u32	reserved1[17];
	u32	pol_hyst;
};

struct vsc9953_ana_common {
	u32	aggr_cfg;
	u32	cpuq_cfg;
	u32	cpuq_8021_cfg;
	u32	dscp_cfg;
	u32	dscp_rewr_cfg;
	u32	vcap_rng_type_cfg;
	u32	vcap_rng_val_cfg;
	u32	discard_cfg;
	u32	fid_cfg;
};

struct vsc9953_analyzer {
	struct vsc9953_ana_port	port[11];
	u32	reserved1[9536];
	struct vsc9953_ana_pol	pol[164];
	struct vsc9953_ana_ana_tables	ana_tables;
	u32	reserved2[14];
	struct vsc9953_ana_ana	ana;
	u32	reserved3[22];
	struct vsc9953_ana_pgid	port_id_tbl;
	u32	reserved4[549];
	struct vsc9953_ana_pfc	pfc[10];
	struct vsc9953_ana_pol_misc	pol_misc;
	u32	reserved5[196];
	struct vsc9953_ana_common	common;
};
/* END VSC9953 ANA structure t*/

/* VSC9953 DEV_GMII structure */

struct vsc9953_dev_gmii_port_mode {
	u32	clock_cfg;
	u32	port_misc;
	u32	reserved1;
	u32	eee_cfg;
};

struct vsc9953_dev_gmii_mac_cfg_status {
	u32	mac_ena_cfg;
	u32	mac_mode_cfg;
	u32	mac_maxlen_cfg;
	u32	mac_tags_cfg;
	u32	mac_adv_chk_cfg;
	u32	mac_ifg_cfg;
	u32	mac_hdx_cfg;
	u32	mac_fc_mac_low_cfg;
	u32	mac_fc_mac_high_cfg;
	u32	mac_sticky;
};

struct vsc9953_dev_gmii {
	struct vsc9953_dev_gmii_port_mode	port_mode;
	struct vsc9953_dev_gmii_mac_cfg_status	mac_cfg_status;
};

/* END VSC9953 DEV_GMII structure */

/* VSC9953 QSYS structure */

struct vsc9953_qsys_hsch {
	u32	cir_cfg;
	u32	reserved1;
	u32	se_cfg;
	u32	se_dwrr_cfg[8];
	u32	cir_state;
	u32	reserved2[20];
};

struct vsc9953_qsys_sys {
	u32	port_mode[12];
	u32	switch_port_mode[11];
	u32	stat_cnt_cfg;
	u32	eee_cfg[10];
	u32	eee_thrs;
	u32	igr_no_sharing;
	u32	egr_no_sharing;
	u32	sw_status[11];
	u32	ext_cpu_cfg;
	u32	cpu_group_map;
	u32	reserved1[23];
};

struct vsc9953_qsys_qos_cfg {
	u32	red_profile[16];
	u32	res_qos_mode;
};

struct vsc9953_qsys_drop_cfg {
	u32	egr_drop_mode;
};

struct vsc9953_qsys_mmgt {
	u32	eq_cntrl;
	u32	reserved1;
};

struct vsc9953_qsys_hsch_misc {
	u32	hsch_misc_cfg;
	u32	reserved1[546];
};

struct vsc9953_qsys_res_ctrl {
	u32	res_cfg;
	u32	res_stat;

};

struct vsc9953_qsys_reg {
	struct vsc9953_qsys_hsch	hsch[108];
	struct vsc9953_qsys_sys	sys;
	struct vsc9953_qsys_qos_cfg	qos_cfg;
	struct vsc9953_qsys_drop_cfg	drop_cfg;
	struct vsc9953_qsys_mmgt	mmgt;
	struct vsc9953_qsys_hsch_misc	hsch_misc;
	struct vsc9953_qsys_res_ctrl	res_ctrl[1024];
};

/* END VSC9953 QSYS structure */

/* VSC9953 SYS structure */

struct vsc9953_sys_stat {
	u32	rx_cntrs[64];
	u32	tx_cntrs[64];
	u32	drop_cntrs[64];
	u32	reserved1[6];
};

struct vsc9953_sys_sys {
	u32	reset_cfg;
	u32	reserved1;
	u32	vlan_etype_cfg;
	u32	port_mode[12];
	u32	front_port_mode[10];
	u32	frame_aging;
	u32	stat_cfg;
	u32	reserved2[50];
};

struct vsc9953_sys_pause_cfg {
	u32	pause_cfg[11];
	u32	pause_tot_cfg;
	u32	tail_drop_level[11];
	u32	tot_tail_drop_lvl;
	u32	mac_fc_cfg[10];
};

struct vsc9953_sys_mmgt {
	u16	free_cnt;
};

struct vsc9953_system_reg {
	struct vsc9953_sys_stat	stat;
	struct vsc9953_sys_sys	sys;
	struct vsc9953_sys_pause_cfg	pause_cfg;
	struct vsc9953_sys_mmgt	mmgt;
};

/* END VSC9953 SYS structure */


/* VSC9953 DEVCPU_GCB structure */

struct vsc9953_chip_regs {
	u32	chipd_id;
	u32	gpr;
	u32	soft_rst;
};

struct vsc9953_gpio {
	u32	gpio_out_set[10];
	u32	gpio_out_clr[10];
	u32	gpio_out[10];
	u32	gpio_in[10];
};

struct vsc9953_mii_mng {
	u32	miimstatus;
	u32	reserved1;
	u32	miimcmd;
	u32	miimdata;
	u32	miimcfg;
	u32	miimscan_0;
	u32	miimscan_1;
	u32	miiscan_lst_rslts;
	u32	miiscan_lst_rslts_valid;
};

struct vsc9953_mii_read_scan {
	u32	mii_scan_results_sticky[2];
};

struct vsc9953_devcpu_gcb {
	struct vsc9953_chip_regs	chip_regs;
	struct vsc9953_gpio		gpio;
	struct vsc9953_mii_mng	mii_mng[2];
	struct vsc9953_mii_read_scan	mii_read_scan;
};

/* END VSC9953 DEVCPU_GCB structure */

/* VSC9953 IS* structure */

struct vsc9953_vcap_core_cfg {
	u32	vcap_update_ctrl;
	u32	vcap_mv_cfg;
};

struct vsc9953_vcap {
	struct vsc9953_vcap_core_cfg	vcap_core_cfg;
};

/* END VSC9953 IS* structure */

#define VSC9953_PORT_INFO_INITIALIZER(idx) \
{									\
	.enabled	= 0,						\
	.phyaddr	= 0,						\
	.index		= idx,						\
	.phy_regs	= NULL,						\
	.enet_if	= PHY_INTERFACE_MODE_NONE,			\
	.bus		= NULL,						\
	.phydev		= NULL,						\
}

/* Structure to describe a VSC9953 port */
struct vsc9953_port_info {
	u8	enabled;
	u8	phyaddr;
	int	index;
	void	*phy_regs;
	phy_interface_t	enet_if;
	struct mii_dev	*bus;
	struct phy_device	*phydev;
};

/* Structure to describe a VSC9953 switch */
struct vsc9953_info {
	struct vsc9953_port_info	port[VSC9953_MAX_PORTS];
};

void vsc9953_init(bd_t *bis);

void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
void vsc9953_port_info_set_phy_address(int port_no, int address);
void vsc9953_port_enable(int port_no);
void vsc9953_port_disable(int port_no);
void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);

#endif /* _VSC9953_H_ */
Commit	Line	Data
6706b115 CC	1	/*
	2	* vsc9953.h
	3	*
	4	* Driver for the Vitesse VSC9953 L2 Switch
	5	*
	6	* This software may be used and distributed according to the
	7	* terms of the GNU Public License, Version 2, incorporated
	8	* herein by reference.
	9	*
	10	* Copyright 2013 Freescale Semiconductor, Inc.
	11	*
	12	*/
	13
	14	#ifndef _VSC9953_H_
	15	#define _VSC9953_H_
	16
	17	#include <config.h>
	18	#include <miiphy.h>
	19	#include <asm/types.h>
6706b115 CC	20
	21	#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
	22
	23	#define VSC9953_SYS_OFFSET 0x010000
	24	#define VSC9953_DEV_GMII_OFFSET 0x100000
	25	#define VSC9953_QSYS_OFFSET 0x200000
	26	#define VSC9953_ANA_OFFSET 0x280000
	27	#define VSC9953_DEVCPU_GCB 0x070000
	28	#define VSC9953_ES0 0x040000
	29	#define VSC9953_IS1 0x050000
	30	#define VSC9953_IS2 0x060000
	31
	32	#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
	33	#define VSC9953_PHY_REGS_OFFST 0x0000AC
	34
3cc8cfff	35	/* Macros for vsc9953_chip_regs.soft_rst register */
c4390486	36	#define VSC9953_SOFT_SWC_RST_ENA 0x00000001
3cc8cfff CC	37
3cc8cfff CC	38	/* Macros for vsc9953_sys_sys.reset_cfg register */
c4390486 CC	39	#define VSC9953_CORE_ENABLE 0x80
	40	#define VSC9953_MEM_ENABLE 0x40
	41	#define VSC9953_MEM_INIT 0x20
6706b115	42
3cc8cfff	43	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
c4390486	44	#define VSC9953_MAC_ENA_CFG 0x00000011
3cc8cfff CC	45
3cc8cfff CC	46	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
c4390486	47	#define VSC9953_MAC_MODE_CFG 0x00000011
3cc8cfff CC	48
3cc8cfff CC	49	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
c4390486	50	#define VSC9953_MAC_IFG_CFG 0x00000515
3cc8cfff CC	51
3cc8cfff CC	52	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
c4390486	53	#define VSC9953_MAC_HDX_CFG 0x00001043
3cc8cfff CC	54
	55	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
	56	#define VSC9953_MAC_MAX_LEN 0x000005ee
	57
	58	/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
c4390486 CC	59	#define VSC9953_CLOCK_CFG 0x00000001
c4390486 CC	60	#define VSC9953_CLOCK_CFG_1000M 0x00000001
3cc8cfff CC	61
	62	/* Macros for vsc9953_sys_sys.front_port_mode register */
	63	#define VSC9953_FRONT_PORT_MODE 0x00000000
	64
	65	/* Macros for vsc9953_ana_pfc.pfc_cfg register */
c4390486 CC	66	#define VSC9953_PFC_FC 0x00000001
c4390486 CC	67	#define VSC9953_PFC_FC_QSGMII 0x00000000
3cc8cfff CC	68
3cc8cfff CC	69	/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
c4390486 CC	70	#define VSC9953_MAC_FC_CFG 0x04700000
c4390486 CC	71	#define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
3cc8cfff CC	72
3cc8cfff CC	73	/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
c4390486	74	#define VSC9953_PAUSE_CFG 0x001ffffe
3cc8cfff CC	75
3cc8cfff CC	76	/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
c4390486	77	#define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
6706b115	78
3cc8cfff	79	/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
c4390486 CC	80	#define VSC9953_VCAP_MV_CFG 0x0000ffff
c4390486 CC	81	#define VSC9953_VCAP_UPDATE_CTRL 0x01000004
3cc8cfff CC	82
	83	/* Macros for vsc9953_qsys_sys.switch_port_mode register */
	84	#define VSC9953_PORT_ENA 0x00003a00
	85
6706b115 CC	86	#define VSC9953_MAX_PORTS 10
	87	#define VSC9953_PORT_CHECK(port) \
	88	(((port) < 0 \|\| (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
	89	#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
	90	( \
	91	(port) < VSC9953_MAX_PORTS - 2 \|\| (port) >= VSC9953_MAX_PORTS \
	92	) ? 0 : 1 \
	93	)
	94
	95	#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
	96
	97	#define MIIMIND_OPR_PEND 0x00000004
	98
	99	struct vsc9953_mdio_info {
	100	struct vsc9953_mii_mng *regs;
	101	char *name;
	102	};
	103
3cc8cfff	104	/* VSC9953 ANA structure */
6706b115	105
3cc8cfff	106	struct vsc9953_ana_port {
6706b115 CC	107	u32 vlan_cfg;
	108	u32 drop_cfg;
	109	u32 qos_cfg;
	110	u32 vcap_cfg;
	111	u32 vcap_s1_key_cfg[3];
	112	u32 vcap_s2_cfg;
	113	u32 qos_pcp_dei_map_cfg[16];
	114	u32 cpu_fwd_cfg;
	115	u32 cpu_fwd_bpdu_cfg;
	116	u32 cpu_fwd_garp_cfg;
	117	u32 cpu_fwd_ccm_cfg;
	118	u32 port_cfg;
	119	u32 pol_cfg;
	120	u32 reserved[34];
	121	};
	122
	123	struct vsc9953_ana_pol {
	124	u32 pol_pir_cfg;
	125	u32 pol_cir_cfg;
	126	u32 pol_mode_cfg;
	127	u32 pol_pir_state;
	128	u32 pol_cir_state;
	129	u32 reserved1[3];
	130	};
	131
	132	struct vsc9953_ana_ana_tables {
	133	u32 entry_lim[11];
	134	u32 an_moved;
	135	u32 mach_data;
	136	u32 macl_data;
	137	u32 mac_access;
	138	u32 mact_indx;
	139	u32 vlan_access;
	140	u32 vlan_tidx;
	141	};
	142
	143	struct vsc9953_ana_ana {
	144	u32 adv_learn;
	145	u32 vlan_mask;
	146	u32 anag_efil;
	147	u32 an_events;
	148	u32 storm_limit_burst;
	149	u32 storm_limit_cfg[4];
	150	u32 isolated_prts;
	151	u32 community_ports;
	152	u32 auto_age;
	153	u32 mac_options;
	154	u32 learn_disc;
	155	u32 agen_ctrl;
	156	u32 mirror_ports;
	157	u32 emirror_ports;
	158	u32 flooding;
	159	u32 flooding_ipmc;
	160	u32 sflow_cfg[11];
	161	u32 port_mode[12];
	162	};
	163
	164	struct vsc9953_ana_pgid {
	165	u32 port_grp_id[91];
	166	};
	167
3cc8cfff	168	struct vsc9953_ana_pfc {
6706b115 CC	169	u32 pfc_cfg;
	170	u32 reserved1[15];
	171	};
	172
	173	struct vsc9953_ana_pol_misc {
	174	u32 pol_flowc[10];
	175	u32 reserved1[17];
	176	u32 pol_hyst;
	177	};
	178
3cc8cfff	179	struct vsc9953_ana_common {
6706b115 CC	180	u32 aggr_cfg;
	181	u32 cpuq_cfg;
	182	u32 cpuq_8021_cfg;
	183	u32 dscp_cfg;
	184	u32 dscp_rewr_cfg;
	185	u32 vcap_rng_type_cfg;
	186	u32 vcap_rng_val_cfg;
	187	u32 discard_cfg;
	188	u32 fid_cfg;
	189	};
	190
	191	struct vsc9953_analyzer {
	192	struct vsc9953_ana_port port[11];
	193	u32 reserved1[9536];
	194	struct vsc9953_ana_pol pol[164];
	195	struct vsc9953_ana_ana_tables ana_tables;
	196	u32 reserved2[14];
	197	struct vsc9953_ana_ana ana;
	198	u32 reserved3[22];
	199	struct vsc9953_ana_pgid port_id_tbl;
	200	u32 reserved4[549];
	201	struct vsc9953_ana_pfc pfc[10];
	202	struct vsc9953_ana_pol_misc pol_misc;
	203	u32 reserved5[196];
	204	struct vsc9953_ana_common common;
	205	};
3cc8cfff	206	/* END VSC9953 ANA structure t*/
6706b115	207
3cc8cfff	208	/* VSC9953 DEV_GMII structure */
6706b115	209
3cc8cfff	210	struct vsc9953_dev_gmii_port_mode {
6706b115 CC	211	u32 clock_cfg;
	212	u32 port_misc;
	213	u32 reserved1;
	214	u32 eee_cfg;
	215	};
	216
3cc8cfff	217	struct vsc9953_dev_gmii_mac_cfg_status {
6706b115 CC	218	u32 mac_ena_cfg;
	219	u32 mac_mode_cfg;
	220	u32 mac_maxlen_cfg;
	221	u32 mac_tags_cfg;
	222	u32 mac_adv_chk_cfg;
	223	u32 mac_ifg_cfg;
	224	u32 mac_hdx_cfg;
	225	u32 mac_fc_mac_low_cfg;
	226	u32 mac_fc_mac_high_cfg;
	227	u32 mac_sticky;
	228	};
	229
	230	struct vsc9953_dev_gmii {
	231	struct vsc9953_dev_gmii_port_mode port_mode;
	232	struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
	233	};
	234
3cc8cfff	235	/* END VSC9953 DEV_GMII structure */
6706b115	236
3cc8cfff	237	/* VSC9953 QSYS structure */
6706b115	238
3cc8cfff	239	struct vsc9953_qsys_hsch {
6706b115 CC	240	u32 cir_cfg;
	241	u32 reserved1;
	242	u32 se_cfg;
	243	u32 se_dwrr_cfg[8];
	244	u32 cir_state;
	245	u32 reserved2[20];
	246	};
	247
3cc8cfff	248	struct vsc9953_qsys_sys {
6706b115 CC	249	u32 port_mode[12];
	250	u32 switch_port_mode[11];
	251	u32 stat_cnt_cfg;
	252	u32 eee_cfg[10];
	253	u32 eee_thrs;
	254	u32 igr_no_sharing;
	255	u32 egr_no_sharing;
	256	u32 sw_status[11];
	257	u32 ext_cpu_cfg;
	258	u32 cpu_group_map;
	259	u32 reserved1[23];
	260	};
	261
3cc8cfff	262	struct vsc9953_qsys_qos_cfg {
6706b115 CC	263	u32 red_profile[16];
	264	u32 res_qos_mode;
	265	};
	266
3cc8cfff	267	struct vsc9953_qsys_drop_cfg {
6706b115 CC	268	u32 egr_drop_mode;
	269	};
	270
3cc8cfff	271	struct vsc9953_qsys_mmgt {
6706b115 CC	272	u32 eq_cntrl;
	273	u32 reserved1;
	274	};
	275
3cc8cfff	276	struct vsc9953_qsys_hsch_misc {
6706b115 CC	277	u32 hsch_misc_cfg;
	278	u32 reserved1[546];
	279	};
	280
3cc8cfff	281	struct vsc9953_qsys_res_ctrl {
6706b115 CC	282	u32 res_cfg;
	283	u32 res_stat;
	284
	285	};
	286
3cc8cfff	287	struct vsc9953_qsys_reg {
6706b115 CC	288	struct vsc9953_qsys_hsch hsch[108];
	289	struct vsc9953_qsys_sys sys;
	290	struct vsc9953_qsys_qos_cfg qos_cfg;
	291	struct vsc9953_qsys_drop_cfg drop_cfg;
	292	struct vsc9953_qsys_mmgt mmgt;
	293	struct vsc9953_qsys_hsch_misc hsch_misc;
	294	struct vsc9953_qsys_res_ctrl res_ctrl[1024];
	295	};
	296
3cc8cfff	297	/* END VSC9953 QSYS structure */
6706b115	298
3cc8cfff	299	/* VSC9953 SYS structure */
6706b115	300
3cc8cfff	301	struct vsc9953_sys_stat {
6706b115 CC	302	u32 rx_cntrs[64];
	303	u32 tx_cntrs[64];
	304	u32 drop_cntrs[64];
	305	u32 reserved1[6];
	306	};
	307
3cc8cfff	308	struct vsc9953_sys_sys {
6706b115 CC	309	u32 reset_cfg;
	310	u32 reserved1;
	311	u32 vlan_etype_cfg;
	312	u32 port_mode[12];
	313	u32 front_port_mode[10];
	314	u32 frame_aging;
	315	u32 stat_cfg;
	316	u32 reserved2[50];
	317	};
	318
3cc8cfff	319	struct vsc9953_sys_pause_cfg {
6706b115 CC	320	u32 pause_cfg[11];
	321	u32 pause_tot_cfg;
	322	u32 tail_drop_level[11];
	323	u32 tot_tail_drop_lvl;
	324	u32 mac_fc_cfg[10];
	325	};
	326
3cc8cfff	327	struct vsc9953_sys_mmgt {
6706b115 CC	328	u16 free_cnt;
	329	};
	330
3cc8cfff	331	struct vsc9953_system_reg {
6706b115 CC	332	struct vsc9953_sys_stat stat;
	333	struct vsc9953_sys_sys sys;
	334	struct vsc9953_sys_pause_cfg pause_cfg;
	335	struct vsc9953_sys_mmgt mmgt;
	336	};
	337
3cc8cfff	338	/* END VSC9953 SYS structure */
6706b115 CC	339
6706b115 CC	340
3cc8cfff	341	/* VSC9953 DEVCPU_GCB structure */
6706b115	342
3cc8cfff	343	struct vsc9953_chip_regs {
6706b115 CC	344	u32 chipd_id;
	345	u32 gpr;
	346	u32 soft_rst;
	347	};
	348
3cc8cfff	349	struct vsc9953_gpio {
6706b115 CC	350	u32 gpio_out_set[10];
	351	u32 gpio_out_clr[10];
	352	u32 gpio_out[10];
	353	u32 gpio_in[10];
	354	};
	355
	356	struct vsc9953_mii_mng {
	357	u32 miimstatus;
	358	u32 reserved1;
	359	u32 miimcmd;
	360	u32 miimdata;
	361	u32 miimcfg;
	362	u32 miimscan_0;
	363	u32 miimscan_1;
	364	u32 miiscan_lst_rslts;
	365	u32 miiscan_lst_rslts_valid;
	366	};
	367
3cc8cfff	368	struct vsc9953_mii_read_scan {
6706b115 CC	369	u32 mii_scan_results_sticky[2];
	370	};
	371
3cc8cfff	372	struct vsc9953_devcpu_gcb {
6706b115 CC	373	struct vsc9953_chip_regs chip_regs;
	374	struct vsc9953_gpio gpio;
	375	struct vsc9953_mii_mng mii_mng[2];
	376	struct vsc9953_mii_read_scan mii_read_scan;
	377	};
	378
3cc8cfff	379	/* END VSC9953 DEVCPU_GCB structure */
6706b115	380
3cc8cfff	381	/* VSC9953 IS* structure */
6706b115	382
3cc8cfff	383	struct vsc9953_vcap_core_cfg {
6706b115 CC	384	u32 vcap_update_ctrl;
	385	u32 vcap_mv_cfg;
	386	};
	387
3cc8cfff CC	388	struct vsc9953_vcap {
3cc8cfff CC	389	struct vsc9953_vcap_core_cfg vcap_core_cfg;
6706b115 CC	390	};
6706b115 CC	391
3cc8cfff	392	/* END VSC9953 IS* structure */
6706b115 CC	393
	394	#define VSC9953_PORT_INFO_INITIALIZER(idx) \
	395	{ \
	396	.enabled = 0, \
	397	.phyaddr = 0, \
	398	.index = idx, \
	399	.phy_regs = NULL, \
	400	.enet_if = PHY_INTERFACE_MODE_NONE, \
	401	.bus = NULL, \
	402	.phydev = NULL, \
	403	}
	404
	405	/* Structure to describe a VSC9953 port */
	406	struct vsc9953_port_info {
	407	u8 enabled;
	408	u8 phyaddr;
	409	int index;
	410	void *phy_regs;
	411	phy_interface_t enet_if;
	412	struct mii_dev *bus;
	413	struct phy_device *phydev;
	414	};
	415
	416	/* Structure to describe a VSC9953 switch */
	417	struct vsc9953_info {
3cc8cfff	418	struct vsc9953_port_info port[VSC9953_MAX_PORTS];
6706b115 CC	419	};
	420
	421	void vsc9953_init(bd_t *bis);
	422
3cc8cfff CC	423	void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
	424	void vsc9953_port_info_set_phy_address(int port_no, int address);
	425	void vsc9953_port_enable(int port_no);
	426	void vsc9953_port_disable(int port_no);
	427	void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
6706b115 CC	428
6706b115 CC	429	#endif /* _VSC9953_H_ */