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1/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8#include <fpga.h>
9
10#ifndef _XILINX_H_
11#define _XILINX_H_
12
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13/* Xilinx types
14 *********************************************************************/
2df9d5c4 15typedef enum { /* typedef xilinx_iface */
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16 min_xilinx_iface_type, /* low range check value */
17 slave_serial, /* serial data and external clock */
18 master_serial, /* serial data w/ internal clock (not used) */
19 slave_parallel, /* parallel data w/ external latch */
20 jtag_mode, /* jtag/tap serial (not used ) */
21 master_selectmap, /* master SelectMap (virtex2) */
22 slave_selectmap, /* slave SelectMap (virtex2) */
d5dae85f 23 devcfg, /* devcfg interface (zynq) */
6b245014 24 csu_dma, /* csu_dma interface (zynqmp) */
53677ef1 25 max_xilinx_iface_type /* insert all new types before this */
2df9d5c4 26} xilinx_iface; /* end, typedef xilinx_iface */
c609719b 27
2df9d5c4 28typedef enum { /* typedef xilinx_family */
53677ef1 29 min_xilinx_type, /* low range check value */
b625b9ae 30 xilinx_spartan2, /* Spartan-II Family */
2df9d5c4 31 xilinx_virtexE, /* Virtex-E Family */
d9071ce0 32 xilinx_virtex2, /* Virtex2 Family */
2a6e3869 33 xilinx_spartan3, /* Spartan-III Family */
d5dae85f 34 xilinx_zynq, /* Zynq Family */
6b245014 35 xilinx_zynqmp, /* ZynqMP Family */
53677ef1 36 max_xilinx_type /* insert all new types before this */
2df9d5c4 37} xilinx_family; /* end, typedef xilinx_family */
c609719b 38
f8c1be98 39typedef struct { /* typedef xilinx_desc */
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40 xilinx_family family; /* part type */
41 xilinx_iface iface; /* interface type */
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42 size_t size; /* bytes of data part can accept */
43 void *iface_fns; /* interface function table */
44 int cookie; /* implementation specific cookie */
14cfc4f3 45 struct xilinx_fpga_op *operations; /* operations */
6631db47 46 char *name; /* device name in bitstream */
f8c1be98 47} xilinx_desc; /* end, typedef xilinx_desc */
c609719b 48
14cfc4f3 49struct xilinx_fpga_op {
7a78bd26 50 int (*load)(xilinx_desc *, const void *, size_t, bitstream_type);
1a897668 51 int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *);
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52 int (*dump)(xilinx_desc *, const void *, size_t);
53 int (*info)(xilinx_desc *);
54};
55
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56/* Generic Xilinx Functions
57 *********************************************************************/
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58int xilinx_load(xilinx_desc *desc, const void *image, size_t size,
59 bitstream_type bstype);
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60int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
61int xilinx_info(xilinx_desc *desc);
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62int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
63 fpga_fs_info *fpga_fsinfo);
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64
65/* Board specific implementation specific function types
66 *********************************************************************/
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67typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie);
68typedef int (*xilinx_init_fn)(int cookie);
69typedef int (*xilinx_err_fn)(int cookie);
70typedef int (*xilinx_done_fn)(int cookie);
71typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie);
72typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie);
73typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie);
74typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie);
75typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie);
76typedef int (*xilinx_busy_fn)(int cookie);
77typedef int (*xilinx_abort_fn)(int cookie);
78typedef int (*xilinx_pre_fn)(int cookie);
79typedef int (*xilinx_post_fn)(int cookie);
80typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie);
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81
82#endif /* _XILINX_H_ */