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fe8c2806 1/*
4707fb50 2 * (C) Copyright 2000-2006
fe8c2806
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26#include <command.h>
27#include <malloc.h>
52cb4d4f 28#include <stdio_dev.h>
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29#ifdef CONFIG_8xx
30#include <mpc8xx.h>
31#endif
0db5bca8
WD
32#ifdef CONFIG_5xx
33#include <mpc5xx.h>
34#endif
cbd8a35c 35#ifdef CONFIG_MPC5xxx
945af8d7
WD
36#include <mpc5xxx.h>
37#endif
7def6b34 38#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
39#include <ide.h>
40#endif
7def6b34 41#if defined(CONFIG_CMD_SCSI)
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42#include <scsi.h>
43#endif
7def6b34 44#if defined(CONFIG_CMD_KGDB)
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45#include <kgdb.h>
46#endif
47#ifdef CONFIG_STATUS_LED
48#include <status_led.h>
49#endif
50#include <net.h>
272cc70b
AF
51#ifdef CONFIG_GENERIC_MMC
52#include <mmc.h>
53#endif
281e00a3 54#include <serial.h>
6d0f6bcf 55#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 56#if !defined(CONFIG_CPM2)
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57#include <commproc.h>
58#endif
7aa78614 59#endif
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60#include <version.h>
61#if defined(CONFIG_BAB7xx)
62#include <w83c553f.h>
63#endif
64#include <dtt.h>
65#if defined(CONFIG_POST)
66#include <post.h>
67#endif
56f94be3
WD
68#if defined(CONFIG_LOGBUFFER)
69#include <logbuff.h>
70#endif
9c67352f 71#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
42d1f039
WD
72#include <asm/cache.h>
73#endif
1c43771b
WD
74#ifdef CONFIG_PS2KBD
75#include <keyboard.h>
76#endif
fe8c2806 77
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78#ifdef CONFIG_ADDR_MAP
79#include <asm/mmu.h>
80#endif
81
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82#ifdef CONFIG_MP
83#include <asm/mp.h>
84#endif
85
310cecb8
LCM
86#ifdef CONFIG_BITBANGMII
87#include <miiphy.h>
88#endif
89
6d0f6bcf 90#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
fa230445
HS
91extern int update_flash_size (int flash_size);
92#endif
93
9045f33c 94#if defined(CONFIG_SC3)
ca43ba18
HS
95extern void sc3_read_eeprom(void);
96#endif
97
7def6b34 98#if defined(CONFIG_CMD_DOC)
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99void doc_init (void);
100#endif
101#if defined(CONFIG_HARD_I2C) || \
102 defined(CONFIG_SOFT_I2C)
103#include <i2c.h>
104#endif
04a9e118 105#include <spi.h>
d6ac2ed8 106#include <nand.h>
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107
108static char *failed = "*** failed ***\n";
109
17d704eb 110#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
fe8c2806 111extern flash_info_t flash_info[];
17d704eb 112#endif
fe8c2806 113
ca43ba18
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114#if defined(CONFIG_START_IDE)
115extern int board_start_ide(void);
116#endif
fe8c2806 117#include <environment.h>
d87080b7 118
bce84c4d 119DECLARE_GLOBAL_DATA_PTR;
fe8c2806 120
0e8d1586 121#if defined(CONFIG_ENV_IS_EMBEDDED)
6d0f6bcf
JCPV
122#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
123#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
124 (CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
9314cee6 125 defined(CONFIG_ENV_IS_IN_NVRAM)
6d0f6bcf 126#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
fe8c2806 127#else
6d0f6bcf 128#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
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129#endif
130
6d0f6bcf
JCPV
131#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
132#define CONFIG_SYS_MEM_TOP_HIDE 0
6fb4b640
SR
133#endif
134
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WD
135extern ulong __init_end;
136extern ulong _end;
3b57fe0a
WD
137ulong monitor_flash_len;
138
7def6b34 139#if defined(CONFIG_CMD_BEDBUG)
8bde7f77
WD
140#include <bedbug/type.h>
141#endif
142
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143/************************************************************************
144 * Utilities *
145 ************************************************************************
146 */
147
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148/*
149 * All attempts to come up with a "common" initialization sequence
150 * that works for all boards and architectures failed: some of the
151 * requirements are just _too_ different. To get rid of the resulting
152 * mess of board dependend #ifdef'ed code we now make the whole
153 * initialization sequence configurable to the user.
154 *
155 * The requirements for any new initalization function is simple: it
156 * receives a pointer to the "global data" structure as it's only
157 * argument, and returns an integer return code, where 0 means
158 * "continue" and != 0 means "fatal error, hang the system".
159 */
160typedef int (init_fnc_t) (void);
161
162/************************************************************************
163 * Init Utilities *
164 ************************************************************************
165 * Some of this code should be moved into the core functions,
166 * but let's get it working (again) first...
167 */
168
169static int init_baudrate (void)
170{
77ddac94 171 char tmp[64]; /* long enough for environment variables */
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172 int i = getenv_r ("baudrate", tmp, sizeof (tmp));
173
174 gd->baudrate = (i > 0)
175 ? (int) simple_strtoul (tmp, NULL, 10)
176 : CONFIG_BAUDRATE;
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177 return (0);
178}
179
180/***********************************************************************/
181
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182void __board_add_ram_info(int use_default)
183{
184 /* please define platform specific board_add_ram_info() */
185}
186void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
187
d96f41e0 188
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189static int init_func_ram (void)
190{
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191#ifdef CONFIG_BOARD_TYPES
192 int board_type = gd->board_type;
193#else
194 int board_type = 0; /* use dummy arg */
195#endif
196 puts ("DRAM: ");
197
198 if ((gd->ram_size = initdram (board_type)) > 0) {
d96f41e0 199 print_size (gd->ram_size, "");
d96f41e0 200 board_add_ram_info(0);
d96f41e0 201 putc('\n');
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202 return (0);
203 }
204 puts (failed);
205 return (1);
206}
207
208/***********************************************************************/
209
210#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
211static int init_func_i2c (void)
212{
213 puts ("I2C: ");
6d0f6bcf 214 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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215 puts ("ready\n");
216 return (0);
217}
218#endif
219
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BW
220#if defined(CONFIG_HARD_SPI)
221static int init_func_spi (void)
222{
223 puts ("SPI: ");
224 spi_init ();
225 puts ("ready\n");
226 return (0);
227}
228#endif
229
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WD
230/***********************************************************************/
231
232#if defined(CONFIG_WATCHDOG)
233static int init_func_watchdog_init (void)
234{
235 puts (" Watchdog enabled\n");
236 WATCHDOG_RESET ();
237 return (0);
238}
239# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
240
241static int init_func_watchdog_reset (void)
242{
243 WATCHDOG_RESET ();
244 return (0);
245}
246# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
247#else
248# define INIT_FUNC_WATCHDOG_INIT /* undef */
249# define INIT_FUNC_WATCHDOG_RESET /* undef */
250#endif /* CONFIG_WATCHDOG */
251
252/************************************************************************
253 * Initialization sequence *
254 ************************************************************************
255 */
256
257init_fnc_t *init_sequence[] = {
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258#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
259 probecpu,
260#endif
91525c67
AV
261#if defined(CONFIG_BOARD_EARLY_INIT_F)
262 board_early_init_f,
263#endif
66ca92a5 264#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
fe8c2806 265 get_clocks, /* get CPU and bus clocks (etc.) */
090eb735
MK
266#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
267 && !defined(CONFIG_TQM885D)
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WD
268 adjust_sdram_tbs_8xx,
269#endif
fe8c2806 270 init_timebase,
c178d3da 271#endif
6d0f6bcf 272#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 273#if !defined(CONFIG_CPM2)
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274 dpram_init,
275#endif
7aa78614 276#endif
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277#if defined(CONFIG_BOARD_POSTCLK_INIT)
278 board_postclk_init,
279#endif
280 env_init,
66ca92a5 281#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
c178d3da
WD
282 get_clocks_866, /* get CPU and bus clocks according to the environment variable */
283 sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
284 init_timebase,
285#endif
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286 init_baudrate,
287 serial_init,
288 console_init_f,
289 display_options,
290#if defined(CONFIG_8260)
291 prt_8260_rsr,
292 prt_8260_clks,
293#endif /* CONFIG_8260 */
0f898604 294#if defined(CONFIG_MPC83xx)
9be39a67
DL
295 prt_83xx_rsr,
296#endif
fe8c2806 297 checkcpu,
cbd8a35c 298#if defined(CONFIG_MPC5xxx)
945af8d7 299 prt_mpc5xxx_clks,
cbd8a35c 300#endif /* CONFIG_MPC5xxx */
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WD
301#if defined(CONFIG_MPC8220)
302 prt_mpc8220_clks,
303#endif
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304 checkboard,
305 INIT_FUNC_WATCHDOG_INIT
c837dcb1 306#if defined(CONFIG_MISC_INIT_F)
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307 misc_init_f,
308#endif
309 INIT_FUNC_WATCHDOG_RESET
310#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
311 init_func_i2c,
312#endif
04a9e118
BW
313#if defined(CONFIG_HARD_SPI)
314 init_func_spi,
315#endif
4532cb69
WD
316#ifdef CONFIG_POST
317 post_init_f,
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318#endif
319 INIT_FUNC_WATCHDOG_RESET
320 init_func_ram,
6d0f6bcf 321#if defined(CONFIG_SYS_DRAM_TEST)
fe8c2806 322 testdram,
6d0f6bcf 323#endif /* CONFIG_SYS_DRAM_TEST */
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WD
324 INIT_FUNC_WATCHDOG_RESET
325
326 NULL, /* Terminate this list */
327};
328
81d93e5c
KG
329ulong get_effective_memsize(void)
330{
331#ifndef CONFIG_VERY_BIG_RAM
332 return gd->ram_size;
333#else
334 /* limit stack to what we can reasonable map */
335 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
336 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
337#endif
338}
339
fe8c2806
WD
340/************************************************************************
341 *
342 * This is the first part of the initialization sequence that is
343 * implemented in C, but still running from ROM.
344 *
345 * The main purpose is to provide a (serial) console interface as
346 * soon as possible (so we can see any error messages), and to
347 * initialize the RAM so that we can relocate the monitor code to
348 * RAM.
349 *
350 * Be aware of the restrictions: global data is read-only, BSS is not
351 * initialized, and stack space is limited to a few kB.
352 *
353 ************************************************************************
354 */
355
95d449ad
MB
356#ifdef CONFIG_LOGBUFFER
357unsigned long logbuffer_base(void)
358{
6d0f6bcf 359 return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
95d449ad
MB
360}
361#endif
362
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WD
363void board_init_f (ulong bootflag)
364{
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WD
365 bd_t *bd;
366 ulong len, addr, addr_sp;
7bc5ee07 367 ulong *s;
fe8c2806
WD
368 gd_t *id;
369 init_fnc_t **init_fnc_ptr;
370#ifdef CONFIG_PRAM
371 int i;
372 ulong reg;
373 uchar tmp[64]; /* long enough for environment variables */
374#endif
375
376 /* Pointer is writable since we allocated a register for it */
6d0f6bcf 377 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
93f6a677
WD
378 /* compiler optimization barrier needed for GCC >= 3.4 */
379 __asm__ __volatile__("": : :"memory");
fe8c2806 380
0f898604 381#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83xx) && \
f060054d 382 !defined(CONFIG_MPC85xx) && !defined(CONFIG_MPC86xx)
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WD
383 /* Clear initial global data */
384 memset ((void *) gd, 0, sizeof (gd_t));
385#endif
386
387 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
388 if ((*init_fnc_ptr) () != 0) {
389 hang ();
390 }
391 }
392
393 /*
394 * Now that we have DRAM mapped and working, we can
395 * relocate the code and continue running from DRAM.
396 *
397 * Reserve memory at end of RAM for (top down in that order):
14f73ca6 398 * - area that won't get touched by U-Boot and Linux (optional)
8bde7f77 399 * - kernel log buffer
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WD
400 * - protected RAM
401 * - LCD framebuffer
402 * - monitor code
403 * - board info struct
404 */
6d0f6bcf 405 len = (ulong)&_end - CONFIG_SYS_MONITOR_BASE;
fe8c2806 406
14f73ca6
SR
407 /*
408 * Subtract specified amount of memory to hide so that it won't
409 * get "touched" at all by U-Boot. By fixing up gd->ram_size
410 * the Linux kernel should now get passed the now "corrected"
411 * memory size and won't touch it either. This should work
412 * for arch/ppc and arch/powerpc. Only Linux board ports in
413 * arch/powerpc with bootwrapper support, that recalculate the
414 * memory size from the SDRAM controller setup will have to
415 * get fixed.
416 */
6d0f6bcf 417 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
14f73ca6 418
6d0f6bcf 419 addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
fe8c2806 420
fc39c2fd
KG
421#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
422 /*
423 * We need to make sure the location we intend to put secondary core
424 * boot code is reserved and not used by any part of u-boot
c0a14aed 425 */
fc39c2fd
KG
426 if (addr > determine_mp_bootpg()) {
427 addr = determine_mp_bootpg();
428 debug ("Reserving MP boot page to %08lx\n", addr);
429 }
430#endif
431
228f29ac 432#ifdef CONFIG_LOGBUFFER
3d610186 433#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
434 /* reserve kernel log buffer */
435 addr -= (LOGBUFF_RESERVE);
9d2b18a0 436 debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
228f29ac 437#endif
3d610186 438#endif
228f29ac 439
fe8c2806
WD
440#ifdef CONFIG_PRAM
441 /*
442 * reserve protected RAM
443 */
77ddac94
WD
444 i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
445 reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
fe8c2806 446 addr -= (reg << 10); /* size is in kB */
9d2b18a0 447 debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
fe8c2806
WD
448#endif /* CONFIG_PRAM */
449
450 /* round down to next 4 kB limit */
451 addr &= ~(4096 - 1);
9d2b18a0 452 debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
fe8c2806
WD
453
454#ifdef CONFIG_LCD
455 /* reserve memory for LCD display (always full pages) */
456 addr = lcd_setmem (addr);
457 gd->fb_base = addr;
458#endif /* CONFIG_LCD */
459
460#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
461 /* reserve memory for video display (always full pages) */
462 addr = video_setmem (addr);
463 gd->fb_base = addr;
464#endif /* CONFIG_VIDEO */
465
466 /*
467 * reserve memory for U-Boot code, data & bss
682011ff 468 * round down to next 4 kB limit
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WD
469 */
470 addr -= len;
682011ff 471 addr &= ~(4096 - 1);
7d314992
WD
472#ifdef CONFIG_E500
473 /* round down to next 64 kB limit so that IVPR stays aligned */
474 addr &= ~(65536 - 1);
475#endif
fe8c2806 476
9d2b18a0 477 debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
fe8c2806 478
c7de829c
WD
479#ifdef CONFIG_AMIGAONEG3SE
480 gd->relocaddr = addr;
481#endif
482
fe8c2806
WD
483 /*
484 * reserve memory for malloc() arena
485 */
486 addr_sp = addr - TOTAL_MALLOC_LEN;
9d2b18a0 487 debug ("Reserving %dk for malloc() at: %08lx\n",
fe8c2806 488 TOTAL_MALLOC_LEN >> 10, addr_sp);
fe8c2806
WD
489
490 /*
491 * (permanently) allocate a Board Info struct
492 * and a permanent copy of the "global" data
493 */
494 addr_sp -= sizeof (bd_t);
495 bd = (bd_t *) addr_sp;
496 gd->bd = bd;
b64f190b 497 debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
fe8c2806 498 sizeof (bd_t), addr_sp);
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WD
499 addr_sp -= sizeof (gd_t);
500 id = (gd_t *) addr_sp;
b64f190b 501 debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
fe8c2806 502 sizeof (gd_t), addr_sp);
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WD
503
504 /*
505 * Finally, we set up a new (bigger) stack.
506 *
507 * Leave some safety gap for SP, force alignment on 16 byte boundary
508 * Clear initial stack frame
509 */
510 addr_sp -= 16;
511 addr_sp &= ~0xF;
7bc5ee07
WD
512 s = (ulong *)addr_sp;
513 *s-- = 0;
514 *s-- = 0;
515 addr_sp = (ulong)s;
9d2b18a0 516 debug ("Stack Pointer at: %08lx\n", addr_sp);
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WD
517
518 /*
519 * Save local variables to board info struct
520 */
521
6d0f6bcf 522 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */
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523 bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
524
525#ifdef CONFIG_IP860
c837dcb1
WD
526 bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */
527 bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */
983fda83 528#elif defined CONFIG_MPC8220
6d0f6bcf
JCPV
529 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM memory */
530 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM memory */
fe8c2806 531#else
c837dcb1
WD
532 bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */
533 bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
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WD
534#endif
535
42d1f039 536#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
debb7354 537 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
6d0f6bcf 538 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
fe8c2806 539#endif
cbd8a35c 540#if defined(CONFIG_MPC5xxx)
6d0f6bcf 541 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
945af8d7 542#endif
0f898604 543#if defined(CONFIG_MPC83xx)
6d0f6bcf 544 bd->bi_immrbar = CONFIG_SYS_IMMR;
f046ccd1 545#endif
983fda83 546#if defined(CONFIG_MPC8220)
6d0f6bcf 547 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
983fda83
WD
548 bd->bi_inpfreq = gd->inp_clk;
549 bd->bi_pcifreq = gd->pci_clk;
550 bd->bi_vcofreq = gd->vco_clk;
551 bd->bi_pevfreq = gd->pev_clk;
552 bd->bi_flbfreq = gd->flb_clk;
553
dd520bf3
WD
554 /* store bootparam to sram (backward compatible), here? */
555 {
6d0f6bcf 556 u32 *sram = (u32 *)CONFIG_SYS_SRAM_BASE;
dd520bf3
WD
557 *sram++ = gd->ram_size;
558 *sram++ = gd->bus_clk;
559 *sram++ = gd->inp_clk;
560 *sram++ = gd->cpu_clk;
561 *sram++ = gd->vco_clk;
562 *sram++ = gd->flb_clk;
563 *sram++ = 0xb8c3ba11; /* boot signature */
564 }
983fda83 565#endif
fe8c2806
WD
566
567 bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
568
569 WATCHDOG_RESET ();
570 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
571 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
9c4c5ae3 572#if defined(CONFIG_CPM2)
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WD
573 bd->bi_cpmfreq = gd->cpm_clk;
574 bd->bi_brgfreq = gd->brg_clk;
575 bd->bi_sccfreq = gd->scc_clk;
576 bd->bi_vco = gd->vco_out;
9c4c5ae3 577#endif /* CONFIG_CPM2 */
281ff9a4 578#if defined(CONFIG_MPC512X)
5d49e0e1 579 bd->bi_ipsfreq = gd->ips_clk;
281ff9a4 580#endif /* CONFIG_MPC512X */
cbd8a35c 581#if defined(CONFIG_MPC5xxx)
945af8d7
WD
582 bd->bi_ipbfreq = gd->ipb_clk;
583 bd->bi_pcifreq = gd->pci_clk;
cbd8a35c 584#endif /* CONFIG_MPC5xxx */
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585 bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
586
6d0f6bcf 587#ifdef CONFIG_SYS_EXTBDINFO
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WD
588 strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
589 strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
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WD
590
591 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
592 bd->bi_plb_busfreq = gd->bus_clk;
343c48bd
SR
593#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
594 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
595 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
fe8c2806 596 bd->bi_pci_busfreq = get_PCI_freq ();
109c0e3a 597 bd->bi_opbfreq = get_OPB_freq ();
9fea65a6 598#elif defined(CONFIG_XILINX_405)
028ab6b5 599 bd->bi_pci_busfreq = get_PCI_freq ();
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600#endif
601#endif
602
9d2b18a0 603 debug ("New Stack Pointer is: %08lx\n", addr_sp);
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WD
604
605 WATCHDOG_RESET ();
606
607#ifdef CONFIG_POST
608 post_bootmode_init();
6dff5529 609 post_run (NULL, POST_ROM | post_bootmode_get(0));
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WD
610#endif
611
612 WATCHDOG_RESET();
613
27b207fd 614 memcpy (id, (void *)gd, sizeof (gd_t));
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WD
615
616 relocate_code (addr_sp, id, addr);
617
618 /* NOTREACHED - relocate_code() does not return */
619}
620
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621/************************************************************************
622 *
623 * This is the next part if the initialization sequence: we are now
624 * running from RAM and have a "normal" C environment, i. e. global
625 * data can be written, BSS has been cleared, the stack size in not
626 * that critical any more, etc.
627 *
628 ************************************************************************
629 */
fe8c2806
WD
630void board_init_r (gd_t *id, ulong dest_addr)
631{
ff7dc067 632 char *s;
fe8c2806 633 bd_t *bd;
a483a167 634 ulong malloc_start;
fe8c2806 635
6d0f6bcf 636#ifndef CONFIG_SYS_NO_FLASH
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WD
637 ulong flash_size;
638#endif
639
640 gd = id; /* initialize RAM version of global data */
641 bd = gd->bd;
642
643 gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
f82b3b63 644
d4e8ada0 645 /* The Malloc area is immediately below the monitor copy in DRAM */
a483a167 646 malloc_start = dest_addr - TOTAL_MALLOC_LEN;
13d46ab2 647
bb105f24
MB
648#ifdef CONFIG_SERIAL_MULTI
649 serial_initialize();
650#endif
fe8c2806 651
9d2b18a0 652 debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
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WD
653
654 WATCHDOG_RESET ();
655
d025aa4b
BB
656 /*
657 * Setup trap handlers
658 */
659 trap_init (dest_addr);
660
c9315e6b 661#ifdef CONFIG_ADDR_MAP
ecf5b98c
KG
662 init_addr_map();
663#endif
664
c837dcb1
WD
665#if defined(CONFIG_BOARD_EARLY_INIT_R)
666 board_early_init_r ();
667#endif
668
3b57fe0a 669 monitor_flash_len = (ulong)&__init_end - dest_addr;
fe8c2806 670
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WD
671 WATCHDOG_RESET ();
672
56f94be3 673#ifdef CONFIG_LOGBUFFER
228f29ac 674 logbuff_init_ptrs ();
56f94be3 675#endif
fe8c2806 676#ifdef CONFIG_POST
228f29ac 677 post_output_backlog ();
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WD
678#endif
679
680 WATCHDOG_RESET();
681
0f898604 682#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx)
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WD
683 icache_enable (); /* it's time to enable the instruction cache */
684#endif
685
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WD
686#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
687 unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
42d1f039
WD
688#endif
689
3bac3513 690#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
fe8c2806 691 /*
3bac3513
WD
692 * Do PCI configuration on BAB7xx and CPC45 _before_ the flash
693 * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus
694 * bridge there.
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WD
695 */
696 pci_init ();
3bac3513
WD
697#endif
698#if defined(CONFIG_BAB7xx)
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WD
699 /*
700 * Initialise the ISA bridge
701 */
702 initialise_w83c553f ();
703#endif
704
705 asm ("sync ; isync");
706
a483a167 707 mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
c790b04d 708
6d0f6bcf 709#if !defined(CONFIG_SYS_NO_FLASH)
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WD
710 puts ("FLASH: ");
711
712 if ((flash_size = flash_init ()) > 0) {
6d0f6bcf 713# ifdef CONFIG_SYS_FLASH_CHECKSUM
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WD
714 print_size (flash_size, "");
715 /*
716 * Compute and print flash CRC if flashchecksum is set to 'y'
717 *
718 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
719 */
720 s = getenv ("flashchecksum");
721 if (s && (*s == 'y')) {
06c53bea 722 printf (" CRC: %08X",
6d0f6bcf 723 crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
7e780369 724 );
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WD
725 }
726 putc ('\n');
6d0f6bcf 727# else /* !CONFIG_SYS_FLASH_CHECKSUM */
fe8c2806 728 print_size (flash_size, "\n");
6d0f6bcf 729# endif /* CONFIG_SYS_FLASH_CHECKSUM */
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WD
730 } else {
731 puts (failed);
732 hang ();
733 }
734
6d0f6bcf 735 bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */
fe8c2806 736 bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
fa230445 737
6d0f6bcf 738#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
fa230445
HS
739 /* Make a update of the Memctrl. */
740 update_flash_size (flash_size);
741#endif
742
743
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WD
744# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
745 /* flash mapped at end of memory map */
746 bd->bi_flashoffset = TEXT_BASE + flash_size;
6d0f6bcf 747# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
3b57fe0a 748 bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
0cb61d7d 749# else
fe8c2806 750 bd->bi_flashoffset = 0;
0cb61d7d 751# endif
6d0f6bcf 752#else /* CONFIG_SYS_NO_FLASH */
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753
754 bd->bi_flashsize = 0;
755 bd->bi_flashstart = 0;
756 bd->bi_flashoffset = 0;
6d0f6bcf 757#endif /* !CONFIG_SYS_NO_FLASH */
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758
759 WATCHDOG_RESET ();
760
761 /* initialize higher level parts of CPU like time base and timers */
762 cpu_init_r ();
763
764 WATCHDOG_RESET ();
765
fe8c2806 766#ifdef CONFIG_SPI
bb1f8b4f 767# if !defined(CONFIG_ENV_IS_IN_EEPROM)
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768 spi_init_f ();
769# endif
770 spi_init_r ();
771#endif
772
7def6b34 773#if defined(CONFIG_CMD_NAND)
887e2ec9
SR
774 WATCHDOG_RESET ();
775 puts ("NAND: ");
776 nand_init(); /* go init the NAND */
777#endif
778
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WD
779 /* relocate environment function pointers etc. */
780 env_relocate ();
781
782 /*
783 * Fill in missing fields of bd_info.
8bde7f77
WD
784 * We do this here, where we have "normal" access to the
785 * environment; we used to do this still running from ROM,
786 * where had to use getenv_r(), which can be pretty slow when
787 * the environment is in EEPROM.
fe8c2806 788 */
7abf0c58 789
6d0f6bcf 790#if defined(CONFIG_SYS_EXTBDINFO)
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WD
791#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
792#if defined(CONFIG_I2CFAST)
793 /*
794 * set bi_iic_fast for linux taking environment variable
795 * "i2cfast" into account
796 */
797 {
798 char *s = getenv ("i2cfast");
799 if (s && ((*s == 'y') || (*s == 'Y'))) {
800 bd->bi_iic_fast[0] = 1;
801 bd->bi_iic_fast[1] = 1;
802 } else {
803 bd->bi_iic_fast[0] = 0;
804 bd->bi_iic_fast[1] = 0;
805 }
806 }
807#else
808 bd->bi_iic_fast[0] = 0;
809 bd->bi_iic_fast[1] = 0;
810#endif /* CONFIG_I2CFAST */
811#endif /* CONFIG_405GP, CONFIG_405EP */
6d0f6bcf 812#endif /* CONFIG_SYS_EXTBDINFO */
7abf0c58 813
9045f33c 814#if defined(CONFIG_SC3)
ca43ba18
HS
815 sc3_read_eeprom();
816#endif
d59feffb 817
6d0f6bcf 818#if defined (CONFIG_ID_EEPROM) || defined (CONFIG_SYS_I2C_MAC_OFFSET)
d59feffb
HW
819 mac_read_from_eeprom();
820#endif
821
fe8c2806
WD
822#ifdef CONFIG_HERMES
823 if ((gd->board_type >> 16) == 2)
824 bd->bi_ethspeed = gd->board_type & 0xFFFF;
825 else
826 bd->bi_ethspeed = 0xFFFF;
827#endif
828
02a301cd 829#ifdef CONFIG_CMD_NET
eb85aa59
MF
830 /* kept around for legacy kernels only ... ignore the next section */
831 eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
e2ffd59b 832#ifdef CONFIG_HAS_ETH1
eb85aa59 833 eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
fe8c2806 834#endif
e2ffd59b 835#ifdef CONFIG_HAS_ETH2
eb85aa59 836 eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
fe8c2806 837#endif
e2ffd59b 838#ifdef CONFIG_HAS_ETH3
eb85aa59 839 eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
ba56f625 840#endif
c68a05fe 841#ifdef CONFIG_HAS_ETH4
eb85aa59 842 eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
c68a05fe 843#endif
c68a05fe 844#ifdef CONFIG_HAS_ETH5
eb85aa59 845 eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
c68a05fe 846#endif
02a301cd 847#endif /* CONFIG_CMD_NET */
c68a05fe 848
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WD
849 /* IP Address */
850 bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
851
852 WATCHDOG_RESET ();
853
979bdbc7 854#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45)
fe8c2806
WD
855 /*
856 * Do pci configuration
857 */
858 pci_init ();
859#endif
860
861/** leave this here (after malloc(), environment and PCI are working) **/
52cb4d4f
JCPV
862 /* Initialize stdio devices */
863 stdio_init ();
fe8c2806 864
27b207fd
WD
865 /* Initialize the jump table for applications */
866 jumptable_init ();
fe8c2806 867
500856eb
RJ
868#if defined(CONFIG_API)
869 /* Initialize API */
870 api_init ();
871#endif
872
fe8c2806
WD
873 /* Initialize the console (after the relocation and devices init) */
874 console_init_r ();
fe8c2806 875
3a8f28d0 876#if defined(CONFIG_MISC_INIT_R)
fe8c2806
WD
877 /* miscellaneous platform dependent initialisations */
878 misc_init_r ();
879#endif
880
881#ifdef CONFIG_HERMES
882 if (bd->bi_ethspeed != 0xFFFF)
883 hermes_start_lxt980 ((int) bd->bi_ethspeed);
884#endif
885
7def6b34 886#if defined(CONFIG_CMD_KGDB)
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WD
887 WATCHDOG_RESET ();
888 puts ("KGDB: ");
889 kgdb_init ();
890#endif
891
9d2b18a0 892 debug ("U-Boot relocated to %08lx\n", dest_addr);
fe8c2806
WD
893
894 /*
895 * Enable Interrupts
896 */
897 interrupt_init ();
898
899 /* Must happen after interrupts are initialized since
900 * an irq handler gets installed
901 */
42dfe7a1 902#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD
903 serial_buffered_init();
904#endif
905
566a494f 906#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
fe8c2806
WD
907 status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
908#endif
909
910 udelay (20);
911
912 set_timer (0);
913
fe8c2806
WD
914 /* Initialize from environment */
915 if ((s = getenv ("loadaddr")) != NULL) {
916 load_addr = simple_strtoul (s, NULL, 16);
917 }
7def6b34 918#if defined(CONFIG_CMD_NET)
fe8c2806
WD
919 if ((s = getenv ("bootfile")) != NULL) {
920 copy_filename (BootFile, s, sizeof (BootFile));
921 }
b3aff0cb 922#endif
fe8c2806
WD
923
924 WATCHDOG_RESET ();
925
9c2d63ec
HS
926#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */
927 dtt_init ();
928#endif
7def6b34 929#if defined(CONFIG_CMD_SCSI)
fe8c2806
WD
930 WATCHDOG_RESET ();
931 puts ("SCSI: ");
932 scsi_init ();
933#endif
934
272cc70b
AF
935#ifdef CONFIG_GENERIC_MMC
936 WATCHDOG_RESET ();
937 puts ("MMC: ");
938 mmc_initialize (bd);
939#endif
940
7def6b34 941#if defined(CONFIG_CMD_DOC)
fe8c2806
WD
942 WATCHDOG_RESET ();
943 puts ("DOC: ");
944 doc_init ();
945#endif
946
310cecb8
LCM
947#ifdef CONFIG_BITBANGMII
948 bb_miiphy_init();
949#endif
7def6b34 950#if defined(CONFIG_CMD_NET)
63ff004c 951#if defined(CONFIG_NET_MULTI)
fe8c2806
WD
952 WATCHDOG_RESET ();
953 puts ("Net: ");
63ff004c 954#endif
fe8c2806
WD
955 eth_initialize (bd);
956#endif
957
004eca0c 958#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
63ff004c
MB
959 WATCHDOG_RESET ();
960 debug ("Reset Ethernet PHY\n");
961 reset_phy ();
962#endif
963
fe8c2806 964#ifdef CONFIG_POST
6dff5529 965 post_run (NULL, POST_RAM | post_bootmode_get(0));
fe8c2806
WD
966#endif
967
7def6b34
JL
968#if defined(CONFIG_CMD_PCMCIA) \
969 && !defined(CONFIG_CMD_IDE)
fe8c2806
WD
970 WATCHDOG_RESET ();
971 puts ("PCMCIA:");
972 pcmcia_init ();
973#endif
974
7def6b34 975#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
976 WATCHDOG_RESET ();
977# ifdef CONFIG_IDE_8xx_PCCARD
978 puts ("PCMCIA:");
979# else
980 puts ("IDE: ");
981#endif
ca43ba18
HS
982#if defined(CONFIG_START_IDE)
983 if (board_start_ide())
984 ide_init ();
985#else
fe8c2806 986 ide_init ();
ca43ba18 987#endif
b3aff0cb 988#endif
fe8c2806
WD
989
990#ifdef CONFIG_LAST_STAGE_INIT
991 WATCHDOG_RESET ();
992 /*
993 * Some parts can be only initialized if all others (like
994 * Interrupts) are up and running (i.e. the PC-style ISA
995 * keyboard).
996 */
997 last_stage_init ();
998#endif
999
7def6b34 1000#if defined(CONFIG_CMD_BEDBUG)
fe8c2806
WD
1001 WATCHDOG_RESET ();
1002 bedbug_init ();
1003#endif
1004
228f29ac 1005#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
fe8c2806
WD
1006 /*
1007 * Export available size of memory for Linux,
1008 * taking into account the protected RAM at top of memory
1009 */
1010 {
1011 ulong pram;
fe8c2806 1012 uchar memsz[32];
228f29ac
WD
1013#ifdef CONFIG_PRAM
1014 char *s;
fe8c2806
WD
1015
1016 if ((s = getenv ("pram")) != NULL) {
1017 pram = simple_strtoul (s, NULL, 10);
1018 } else {
1019 pram = CONFIG_PRAM;
1020 }
228f29ac
WD
1021#else
1022 pram=0;
1023#endif
1024#ifdef CONFIG_LOGBUFFER
3d610186 1025#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
1026 /* Also take the logbuffer into account (pram is in kB) */
1027 pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
3d610186 1028#endif
228f29ac 1029#endif
77ddac94
WD
1030 sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
1031 setenv ("mem", (char *)memsz);
fe8c2806
WD
1032 }
1033#endif
1034
1c43771b
WD
1035#ifdef CONFIG_PS2KBD
1036 puts ("PS/2: ");
1037 kbd_init();
1038#endif
1039
4532cb69
WD
1040#ifdef CONFIG_MODEM_SUPPORT
1041 {
1042 extern int do_mdm_init;
1043 do_mdm_init = gd->do_mdm_init;
1044 }
1045#endif
1046
fe8c2806
WD
1047 /* Initialization complete - start the monitor */
1048
1049 /* main_loop() can return to retry autoboot, if so just run it again. */
1050 for (;;) {
1051 WATCHDOG_RESET ();
1052 main_loop ();
1053 }
1054
1055 /* NOTREACHED - no way out of command loop except booting */
1056}
1057
1058void hang (void)
1059{
1060 puts ("### ERROR ### Please RESET the board ###\n");
63e73c9a 1061 show_boot_progress(-30);
fe8c2806
WD
1062 for (;;);
1063}
1064
4532cb69 1065
fe8c2806
WD
1066#if 0 /* We could use plain global data, but the resulting code is bigger */
1067/*
1068 * Pointer to initial global data area
1069 *
1070 * Here we initialize it.
1071 */
1072#undef XTRN_DECLARE_GLOBAL_DATA_PTR
1073#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
6d0f6bcf 1074DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
fe8c2806
WD
1075#endif /* 0 */
1076
1077/************************************************************************/