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fe8c2806 1/*
4707fb50 2 * (C) Copyright 2000-2006
fe8c2806
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26#include <command.h>
27#include <malloc.h>
28#include <devices.h>
fe8c2806
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29#ifdef CONFIG_8xx
30#include <mpc8xx.h>
31#endif
0db5bca8
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32#ifdef CONFIG_5xx
33#include <mpc5xx.h>
34#endif
cbd8a35c 35#ifdef CONFIG_MPC5xxx
945af8d7
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36#include <mpc5xxx.h>
37#endif
7def6b34 38#if defined(CONFIG_CMD_IDE)
fe8c2806
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39#include <ide.h>
40#endif
7def6b34 41#if defined(CONFIG_CMD_SCSI)
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42#include <scsi.h>
43#endif
7def6b34 44#if defined(CONFIG_CMD_KGDB)
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45#include <kgdb.h>
46#endif
47#ifdef CONFIG_STATUS_LED
48#include <status_led.h>
49#endif
50#include <net.h>
272cc70b
AF
51#ifdef CONFIG_GENERIC_MMC
52#include <mmc.h>
53#endif
281e00a3 54#include <serial.h>
6d0f6bcf 55#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 56#if !defined(CONFIG_CPM2)
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57#include <commproc.h>
58#endif
7aa78614 59#endif
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60#include <version.h>
61#if defined(CONFIG_BAB7xx)
62#include <w83c553f.h>
63#endif
64#include <dtt.h>
65#if defined(CONFIG_POST)
66#include <post.h>
67#endif
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WD
68#if defined(CONFIG_LOGBUFFER)
69#include <logbuff.h>
70#endif
6d0f6bcf 71#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
42d1f039
WD
72#include <asm/cache.h>
73#endif
1c43771b
WD
74#ifdef CONFIG_PS2KBD
75#include <keyboard.h>
76#endif
fe8c2806 77
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78#ifdef CONFIG_ADDR_MAP
79#include <asm/mmu.h>
80#endif
81
6d0f6bcf 82#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
fa230445
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83extern int update_flash_size (int flash_size);
84#endif
85
9045f33c 86#if defined(CONFIG_SC3)
ca43ba18
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87extern void sc3_read_eeprom(void);
88#endif
89
7def6b34 90#if defined(CONFIG_CMD_DOC)
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91void doc_init (void);
92#endif
93#if defined(CONFIG_HARD_I2C) || \
94 defined(CONFIG_SOFT_I2C)
95#include <i2c.h>
96#endif
04a9e118 97#include <spi.h>
d6ac2ed8 98#include <nand.h>
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99
100static char *failed = "*** failed ***\n";
101
17d704eb 102#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
fe8c2806 103extern flash_info_t flash_info[];
17d704eb 104#endif
fe8c2806 105
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106#if defined(CONFIG_START_IDE)
107extern int board_start_ide(void);
108#endif
fe8c2806 109#include <environment.h>
d87080b7 110
bce84c4d 111DECLARE_GLOBAL_DATA_PTR;
fe8c2806 112
0e8d1586 113#if defined(CONFIG_ENV_IS_EMBEDDED)
6d0f6bcf
JCPV
114#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
115#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
116 (CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
9314cee6 117 defined(CONFIG_ENV_IS_IN_NVRAM)
6d0f6bcf 118#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
fe8c2806 119#else
6d0f6bcf 120#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
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121#endif
122
6d0f6bcf
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123#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
124#define CONFIG_SYS_MEM_TOP_HIDE 0
6fb4b640
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125#endif
126
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127extern ulong __init_end;
128extern ulong _end;
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129ulong monitor_flash_len;
130
7def6b34 131#if defined(CONFIG_CMD_BEDBUG)
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132#include <bedbug/type.h>
133#endif
134
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135/*
136 * Begin and End of memory area for malloc(), and current "brk"
137 */
138static ulong mem_malloc_start = 0;
139static ulong mem_malloc_end = 0;
140static ulong mem_malloc_brk = 0;
141
142/************************************************************************
143 * Utilities *
144 ************************************************************************
145 */
146
147/*
148 * The Malloc area is immediately below the monitor copy in DRAM
149 */
150static void mem_malloc_init (void)
151{
e9514751 152#if !defined(CONFIG_RELOC_FIXUP_WORKS)
6d0f6bcf 153 mem_malloc_end = CONFIG_SYS_MONITOR_BASE + gd->reloc_off;
e9514751
SR
154#endif
155 mem_malloc_start = mem_malloc_end - TOTAL_MALLOC_LEN;
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156 mem_malloc_brk = mem_malloc_start;
157
158 memset ((void *) mem_malloc_start,
159 0,
160 mem_malloc_end - mem_malloc_start);
161}
162
163void *sbrk (ptrdiff_t increment)
164{
165 ulong old = mem_malloc_brk;
166 ulong new = old + increment;
167
168 if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
169 return (NULL);
170 }
171 mem_malloc_brk = new;
172 return ((void *) old);
173}
174
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175/*
176 * All attempts to come up with a "common" initialization sequence
177 * that works for all boards and architectures failed: some of the
178 * requirements are just _too_ different. To get rid of the resulting
179 * mess of board dependend #ifdef'ed code we now make the whole
180 * initialization sequence configurable to the user.
181 *
182 * The requirements for any new initalization function is simple: it
183 * receives a pointer to the "global data" structure as it's only
184 * argument, and returns an integer return code, where 0 means
185 * "continue" and != 0 means "fatal error, hang the system".
186 */
187typedef int (init_fnc_t) (void);
188
189/************************************************************************
190 * Init Utilities *
191 ************************************************************************
192 * Some of this code should be moved into the core functions,
193 * but let's get it working (again) first...
194 */
195
196static int init_baudrate (void)
197{
77ddac94 198 char tmp[64]; /* long enough for environment variables */
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199 int i = getenv_r ("baudrate", tmp, sizeof (tmp));
200
201 gd->baudrate = (i > 0)
202 ? (int) simple_strtoul (tmp, NULL, 10)
203 : CONFIG_BAUDRATE;
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204 return (0);
205}
206
207/***********************************************************************/
208
79f240f7
KP
209void __board_add_ram_info(int use_default)
210{
211 /* please define platform specific board_add_ram_info() */
212}
213void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
214
d96f41e0 215
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216static int init_func_ram (void)
217{
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218#ifdef CONFIG_BOARD_TYPES
219 int board_type = gd->board_type;
220#else
221 int board_type = 0; /* use dummy arg */
222#endif
223 puts ("DRAM: ");
224
225 if ((gd->ram_size = initdram (board_type)) > 0) {
d96f41e0 226 print_size (gd->ram_size, "");
d96f41e0 227 board_add_ram_info(0);
d96f41e0 228 putc('\n');
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229 return (0);
230 }
231 puts (failed);
232 return (1);
233}
234
235/***********************************************************************/
236
237#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
238static int init_func_i2c (void)
239{
240 puts ("I2C: ");
6d0f6bcf 241 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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242 puts ("ready\n");
243 return (0);
244}
245#endif
246
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247#if defined(CONFIG_HARD_SPI)
248static int init_func_spi (void)
249{
250 puts ("SPI: ");
251 spi_init ();
252 puts ("ready\n");
253 return (0);
254}
255#endif
256
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257/***********************************************************************/
258
259#if defined(CONFIG_WATCHDOG)
260static int init_func_watchdog_init (void)
261{
262 puts (" Watchdog enabled\n");
263 WATCHDOG_RESET ();
264 return (0);
265}
266# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
267
268static int init_func_watchdog_reset (void)
269{
270 WATCHDOG_RESET ();
271 return (0);
272}
273# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
274#else
275# define INIT_FUNC_WATCHDOG_INIT /* undef */
276# define INIT_FUNC_WATCHDOG_RESET /* undef */
277#endif /* CONFIG_WATCHDOG */
278
279/************************************************************************
280 * Initialization sequence *
281 ************************************************************************
282 */
283
284init_fnc_t *init_sequence[] = {
285
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286#if defined(CONFIG_BOARD_EARLY_INIT_F)
287 board_early_init_f,
fe8c2806 288#endif
c178d3da 289
66ca92a5 290#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
fe8c2806 291 get_clocks, /* get CPU and bus clocks (etc.) */
090eb735
MK
292#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
293 && !defined(CONFIG_TQM885D)
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WD
294 adjust_sdram_tbs_8xx,
295#endif
fe8c2806 296 init_timebase,
c178d3da 297#endif
6d0f6bcf 298#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 299#if !defined(CONFIG_CPM2)
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300 dpram_init,
301#endif
7aa78614 302#endif
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303#if defined(CONFIG_BOARD_POSTCLK_INIT)
304 board_postclk_init,
305#endif
306 env_init,
66ca92a5 307#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
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WD
308 get_clocks_866, /* get CPU and bus clocks according to the environment variable */
309 sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
310 init_timebase,
311#endif
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WD
312 init_baudrate,
313 serial_init,
314 console_init_f,
315 display_options,
316#if defined(CONFIG_8260)
317 prt_8260_rsr,
318 prt_8260_clks,
319#endif /* CONFIG_8260 */
9be39a67
DL
320#if defined(CONFIG_MPC83XX)
321 prt_83xx_rsr,
322#endif
fe8c2806 323 checkcpu,
cbd8a35c 324#if defined(CONFIG_MPC5xxx)
945af8d7 325 prt_mpc5xxx_clks,
cbd8a35c 326#endif /* CONFIG_MPC5xxx */
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WD
327#if defined(CONFIG_MPC8220)
328 prt_mpc8220_clks,
329#endif
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330 checkboard,
331 INIT_FUNC_WATCHDOG_INIT
c837dcb1 332#if defined(CONFIG_MISC_INIT_F)
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333 misc_init_f,
334#endif
335 INIT_FUNC_WATCHDOG_RESET
336#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
337 init_func_i2c,
338#endif
04a9e118
BW
339#if defined(CONFIG_HARD_SPI)
340 init_func_spi,
341#endif
4532cb69
WD
342#ifdef CONFIG_POST
343 post_init_f,
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WD
344#endif
345 INIT_FUNC_WATCHDOG_RESET
346 init_func_ram,
6d0f6bcf 347#if defined(CONFIG_SYS_DRAM_TEST)
fe8c2806 348 testdram,
6d0f6bcf 349#endif /* CONFIG_SYS_DRAM_TEST */
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WD
350 INIT_FUNC_WATCHDOG_RESET
351
352 NULL, /* Terminate this list */
353};
354
81d93e5c
KG
355ulong get_effective_memsize(void)
356{
357#ifndef CONFIG_VERY_BIG_RAM
358 return gd->ram_size;
359#else
360 /* limit stack to what we can reasonable map */
361 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
362 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
363#endif
364}
365
fe8c2806
WD
366/************************************************************************
367 *
368 * This is the first part of the initialization sequence that is
369 * implemented in C, but still running from ROM.
370 *
371 * The main purpose is to provide a (serial) console interface as
372 * soon as possible (so we can see any error messages), and to
373 * initialize the RAM so that we can relocate the monitor code to
374 * RAM.
375 *
376 * Be aware of the restrictions: global data is read-only, BSS is not
377 * initialized, and stack space is limited to a few kB.
378 *
379 ************************************************************************
380 */
381
95d449ad
MB
382#ifdef CONFIG_LOGBUFFER
383unsigned long logbuffer_base(void)
384{
6d0f6bcf 385 return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
95d449ad
MB
386}
387#endif
388
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389void board_init_f (ulong bootflag)
390{
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391 bd_t *bd;
392 ulong len, addr, addr_sp;
7bc5ee07 393 ulong *s;
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WD
394 gd_t *id;
395 init_fnc_t **init_fnc_ptr;
396#ifdef CONFIG_PRAM
397 int i;
398 ulong reg;
399 uchar tmp[64]; /* long enough for environment variables */
400#endif
401
402 /* Pointer is writable since we allocated a register for it */
6d0f6bcf 403 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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WD
404 /* compiler optimization barrier needed for GCC >= 3.4 */
405 __asm__ __volatile__("": : :"memory");
fe8c2806 406
f060054d
KG
407#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX) && \
408 !defined(CONFIG_MPC85xx) && !defined(CONFIG_MPC86xx)
fe8c2806
WD
409 /* Clear initial global data */
410 memset ((void *) gd, 0, sizeof (gd_t));
411#endif
412
413 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
414 if ((*init_fnc_ptr) () != 0) {
415 hang ();
416 }
417 }
418
419 /*
420 * Now that we have DRAM mapped and working, we can
421 * relocate the code and continue running from DRAM.
422 *
423 * Reserve memory at end of RAM for (top down in that order):
14f73ca6 424 * - area that won't get touched by U-Boot and Linux (optional)
8bde7f77 425 * - kernel log buffer
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WD
426 * - protected RAM
427 * - LCD framebuffer
428 * - monitor code
429 * - board info struct
430 */
6d0f6bcf 431 len = (ulong)&_end - CONFIG_SYS_MONITOR_BASE;
fe8c2806 432
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SR
433 /*
434 * Subtract specified amount of memory to hide so that it won't
435 * get "touched" at all by U-Boot. By fixing up gd->ram_size
436 * the Linux kernel should now get passed the now "corrected"
437 * memory size and won't touch it either. This should work
438 * for arch/ppc and arch/powerpc. Only Linux board ports in
439 * arch/powerpc with bootwrapper support, that recalculate the
440 * memory size from the SDRAM controller setup will have to
441 * get fixed.
442 */
6d0f6bcf 443 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
14f73ca6 444
6d0f6bcf 445 addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
fe8c2806 446
228f29ac 447#ifdef CONFIG_LOGBUFFER
3d610186 448#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
449 /* reserve kernel log buffer */
450 addr -= (LOGBUFF_RESERVE);
9d2b18a0 451 debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
228f29ac 452#endif
3d610186 453#endif
228f29ac 454
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WD
455#ifdef CONFIG_PRAM
456 /*
457 * reserve protected RAM
458 */
77ddac94
WD
459 i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
460 reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
fe8c2806 461 addr -= (reg << 10); /* size is in kB */
9d2b18a0 462 debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
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WD
463#endif /* CONFIG_PRAM */
464
465 /* round down to next 4 kB limit */
466 addr &= ~(4096 - 1);
9d2b18a0 467 debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
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WD
468
469#ifdef CONFIG_LCD
470 /* reserve memory for LCD display (always full pages) */
471 addr = lcd_setmem (addr);
472 gd->fb_base = addr;
473#endif /* CONFIG_LCD */
474
475#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
476 /* reserve memory for video display (always full pages) */
477 addr = video_setmem (addr);
478 gd->fb_base = addr;
479#endif /* CONFIG_VIDEO */
480
481 /*
482 * reserve memory for U-Boot code, data & bss
682011ff 483 * round down to next 4 kB limit
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484 */
485 addr -= len;
682011ff 486 addr &= ~(4096 - 1);
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487#ifdef CONFIG_E500
488 /* round down to next 64 kB limit so that IVPR stays aligned */
489 addr &= ~(65536 - 1);
490#endif
fe8c2806 491
9d2b18a0 492 debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
fe8c2806 493
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WD
494#ifdef CONFIG_AMIGAONEG3SE
495 gd->relocaddr = addr;
496#endif
497
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498 /*
499 * reserve memory for malloc() arena
500 */
501 addr_sp = addr - TOTAL_MALLOC_LEN;
9d2b18a0 502 debug ("Reserving %dk for malloc() at: %08lx\n",
fe8c2806 503 TOTAL_MALLOC_LEN >> 10, addr_sp);
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WD
504
505 /*
506 * (permanently) allocate a Board Info struct
507 * and a permanent copy of the "global" data
508 */
509 addr_sp -= sizeof (bd_t);
510 bd = (bd_t *) addr_sp;
511 gd->bd = bd;
b64f190b 512 debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
fe8c2806 513 sizeof (bd_t), addr_sp);
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WD
514 addr_sp -= sizeof (gd_t);
515 id = (gd_t *) addr_sp;
b64f190b 516 debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
fe8c2806 517 sizeof (gd_t), addr_sp);
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WD
518
519 /*
520 * Finally, we set up a new (bigger) stack.
521 *
522 * Leave some safety gap for SP, force alignment on 16 byte boundary
523 * Clear initial stack frame
524 */
525 addr_sp -= 16;
526 addr_sp &= ~0xF;
7bc5ee07
WD
527 s = (ulong *)addr_sp;
528 *s-- = 0;
529 *s-- = 0;
530 addr_sp = (ulong)s;
9d2b18a0 531 debug ("Stack Pointer at: %08lx\n", addr_sp);
fe8c2806
WD
532
533 /*
534 * Save local variables to board info struct
535 */
536
6d0f6bcf 537 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */
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538 bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
539
540#ifdef CONFIG_IP860
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541 bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */
542 bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */
983fda83 543#elif defined CONFIG_MPC8220
6d0f6bcf
JCPV
544 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM memory */
545 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM memory */
fe8c2806 546#else
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WD
547 bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */
548 bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
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WD
549#endif
550
42d1f039 551#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
debb7354 552 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
6d0f6bcf 553 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
fe8c2806 554#endif
cbd8a35c 555#if defined(CONFIG_MPC5xxx)
6d0f6bcf 556 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
945af8d7 557#endif
f046ccd1 558#if defined(CONFIG_MPC83XX)
6d0f6bcf 559 bd->bi_immrbar = CONFIG_SYS_IMMR;
f046ccd1 560#endif
983fda83 561#if defined(CONFIG_MPC8220)
6d0f6bcf 562 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
983fda83
WD
563 bd->bi_inpfreq = gd->inp_clk;
564 bd->bi_pcifreq = gd->pci_clk;
565 bd->bi_vcofreq = gd->vco_clk;
566 bd->bi_pevfreq = gd->pev_clk;
567 bd->bi_flbfreq = gd->flb_clk;
568
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WD
569 /* store bootparam to sram (backward compatible), here? */
570 {
6d0f6bcf 571 u32 *sram = (u32 *)CONFIG_SYS_SRAM_BASE;
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WD
572 *sram++ = gd->ram_size;
573 *sram++ = gd->bus_clk;
574 *sram++ = gd->inp_clk;
575 *sram++ = gd->cpu_clk;
576 *sram++ = gd->vco_clk;
577 *sram++ = gd->flb_clk;
578 *sram++ = 0xb8c3ba11; /* boot signature */
579 }
983fda83 580#endif
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WD
581
582 bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
583
584 WATCHDOG_RESET ();
585 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
586 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
9c4c5ae3 587#if defined(CONFIG_CPM2)
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588 bd->bi_cpmfreq = gd->cpm_clk;
589 bd->bi_brgfreq = gd->brg_clk;
590 bd->bi_sccfreq = gd->scc_clk;
591 bd->bi_vco = gd->vco_out;
9c4c5ae3 592#endif /* CONFIG_CPM2 */
281ff9a4 593#if defined(CONFIG_MPC512X)
5d49e0e1 594 bd->bi_ipsfreq = gd->ips_clk;
281ff9a4 595#endif /* CONFIG_MPC512X */
cbd8a35c 596#if defined(CONFIG_MPC5xxx)
945af8d7
WD
597 bd->bi_ipbfreq = gd->ipb_clk;
598 bd->bi_pcifreq = gd->pci_clk;
cbd8a35c 599#endif /* CONFIG_MPC5xxx */
fe8c2806
WD
600 bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
601
6d0f6bcf 602#ifdef CONFIG_SYS_EXTBDINFO
77ddac94
WD
603 strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
604 strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
fe8c2806
WD
605
606 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
607 bd->bi_plb_busfreq = gd->bus_clk;
343c48bd
SR
608#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
609 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
610 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
fe8c2806 611 bd->bi_pci_busfreq = get_PCI_freq ();
109c0e3a 612 bd->bi_opbfreq = get_OPB_freq ();
9fea65a6 613#elif defined(CONFIG_XILINX_405)
028ab6b5 614 bd->bi_pci_busfreq = get_PCI_freq ();
fe8c2806
WD
615#endif
616#endif
617
9d2b18a0 618 debug ("New Stack Pointer is: %08lx\n", addr_sp);
fe8c2806
WD
619
620 WATCHDOG_RESET ();
621
622#ifdef CONFIG_POST
623 post_bootmode_init();
6dff5529 624 post_run (NULL, POST_ROM | post_bootmode_get(0));
fe8c2806
WD
625#endif
626
627 WATCHDOG_RESET();
628
27b207fd 629 memcpy (id, (void *)gd, sizeof (gd_t));
fe8c2806
WD
630
631 relocate_code (addr_sp, id, addr);
632
633 /* NOTREACHED - relocate_code() does not return */
634}
635
fe8c2806
WD
636/************************************************************************
637 *
638 * This is the next part if the initialization sequence: we are now
639 * running from RAM and have a "normal" C environment, i. e. global
640 * data can be written, BSS has been cleared, the stack size in not
641 * that critical any more, etc.
642 *
643 ************************************************************************
644 */
fe8c2806
WD
645void board_init_r (gd_t *id, ulong dest_addr)
646{
fe8c2806
WD
647 cmd_tbl_t *cmdtp;
648 char *s, *e;
649 bd_t *bd;
650 int i;
651 extern void malloc_bin_reloc (void);
93f6d725 652#ifndef CONFIG_ENV_IS_NOWHERE
fe8c2806
WD
653 extern char * env_name_spec;
654#endif
655
6d0f6bcf 656#ifndef CONFIG_SYS_NO_FLASH
fe8c2806
WD
657 ulong flash_size;
658#endif
659
660 gd = id; /* initialize RAM version of global data */
661 bd = gd->bd;
662
663 gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
f82b3b63
GL
664
665#if defined(CONFIG_RELOC_FIXUP_WORKS)
666 gd->reloc_off = 0;
e9514751 667 mem_malloc_end = dest_addr;
f82b3b63 668#else
6d0f6bcf 669 gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
f82b3b63 670#endif
bb105f24
MB
671
672#ifdef CONFIG_SERIAL_MULTI
673 serial_initialize();
674#endif
fe8c2806 675
9d2b18a0 676 debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
fe8c2806
WD
677
678 WATCHDOG_RESET ();
679
d025aa4b
BB
680 /*
681 * Setup trap handlers
682 */
683 trap_init (dest_addr);
684
c9315e6b 685#ifdef CONFIG_ADDR_MAP
ecf5b98c
KG
686 init_addr_map();
687#endif
688
c837dcb1
WD
689#if defined(CONFIG_BOARD_EARLY_INIT_R)
690 board_early_init_r ();
691#endif
692
3b57fe0a 693 monitor_flash_len = (ulong)&__init_end - dest_addr;
fe8c2806
WD
694
695 /*
696 * We have to relocate the command table manually
697 */
8bde7f77 698 for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
fe8c2806 699 ulong addr;
fe8c2806
WD
700 addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
701#if 0
702 printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
703 cmdtp->name, (ulong) (cmdtp->cmd), addr);
704#endif
705 cmdtp->cmd =
706 (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
707
708 addr = (ulong)(cmdtp->name) + gd->reloc_off;
709 cmdtp->name = (char *)addr;
710
711 if (cmdtp->usage) {
712 addr = (ulong)(cmdtp->usage) + gd->reloc_off;
713 cmdtp->usage = (char *)addr;
714 }
6d0f6bcf 715#ifdef CONFIG_SYS_LONGHELP
fe8c2806
WD
716 if (cmdtp->help) {
717 addr = (ulong)(cmdtp->help) + gd->reloc_off;
718 cmdtp->help = (char *)addr;
719 }
720#endif
721 }
722 /* there are some other pointer constants we must deal with */
93f6d725 723#ifndef CONFIG_ENV_IS_NOWHERE
fe8c2806
WD
724 env_name_spec += gd->reloc_off;
725#endif
726
727 WATCHDOG_RESET ();
728
56f94be3 729#ifdef CONFIG_LOGBUFFER
228f29ac 730 logbuff_init_ptrs ();
56f94be3 731#endif
fe8c2806 732#ifdef CONFIG_POST
228f29ac 733 post_output_backlog ();
fe8c2806
WD
734 post_reloc ();
735#endif
736
737 WATCHDOG_RESET();
738
506f3918 739#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83XX)
fe8c2806
WD
740 icache_enable (); /* it's time to enable the instruction cache */
741#endif
742
6d0f6bcf 743#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
c837dcb1 744 unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
42d1f039
WD
745#endif
746
3bac3513 747#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
fe8c2806 748 /*
3bac3513
WD
749 * Do PCI configuration on BAB7xx and CPC45 _before_ the flash
750 * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus
751 * bridge there.
fe8c2806
WD
752 */
753 pci_init ();
3bac3513
WD
754#endif
755#if defined(CONFIG_BAB7xx)
fe8c2806
WD
756 /*
757 * Initialise the ISA bridge
758 */
759 initialise_w83c553f ();
760#endif
761
762 asm ("sync ; isync");
763
6d0f6bcf 764#if !defined(CONFIG_SYS_NO_FLASH)
fe8c2806
WD
765 puts ("FLASH: ");
766
767 if ((flash_size = flash_init ()) > 0) {
6d0f6bcf 768# ifdef CONFIG_SYS_FLASH_CHECKSUM
fe8c2806
WD
769 print_size (flash_size, "");
770 /*
771 * Compute and print flash CRC if flashchecksum is set to 'y'
772 *
773 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
774 */
775 s = getenv ("flashchecksum");
776 if (s && (*s == 'y')) {
06c53bea 777 printf (" CRC: %08X",
6d0f6bcf 778 crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
7e780369 779 );
fe8c2806
WD
780 }
781 putc ('\n');
6d0f6bcf 782# else /* !CONFIG_SYS_FLASH_CHECKSUM */
fe8c2806 783 print_size (flash_size, "\n");
6d0f6bcf 784# endif /* CONFIG_SYS_FLASH_CHECKSUM */
fe8c2806
WD
785 } else {
786 puts (failed);
787 hang ();
788 }
789
6d0f6bcf 790 bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */
fe8c2806 791 bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
fa230445 792
6d0f6bcf 793#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
fa230445
HS
794 /* Make a update of the Memctrl. */
795 update_flash_size (flash_size);
796#endif
797
798
7e780369
WD
799# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
800 /* flash mapped at end of memory map */
801 bd->bi_flashoffset = TEXT_BASE + flash_size;
6d0f6bcf 802# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
3b57fe0a 803 bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
0cb61d7d 804# else
fe8c2806 805 bd->bi_flashoffset = 0;
0cb61d7d 806# endif
6d0f6bcf 807#else /* CONFIG_SYS_NO_FLASH */
fe8c2806
WD
808
809 bd->bi_flashsize = 0;
810 bd->bi_flashstart = 0;
811 bd->bi_flashoffset = 0;
6d0f6bcf 812#endif /* !CONFIG_SYS_NO_FLASH */
fe8c2806
WD
813
814 WATCHDOG_RESET ();
815
816 /* initialize higher level parts of CPU like time base and timers */
817 cpu_init_r ();
818
819 WATCHDOG_RESET ();
820
821 /* initialize malloc() area */
822 mem_malloc_init ();
823 malloc_bin_reloc ();
824
825#ifdef CONFIG_SPI
bb1f8b4f 826# if !defined(CONFIG_ENV_IS_IN_EEPROM)
fe8c2806
WD
827 spi_init_f ();
828# endif
829 spi_init_r ();
830#endif
831
7def6b34 832#if defined(CONFIG_CMD_NAND)
887e2ec9
SR
833 WATCHDOG_RESET ();
834 puts ("NAND: ");
835 nand_init(); /* go init the NAND */
836#endif
837
fe8c2806
WD
838 /* relocate environment function pointers etc. */
839 env_relocate ();
840
841 /*
842 * Fill in missing fields of bd_info.
8bde7f77
WD
843 * We do this here, where we have "normal" access to the
844 * environment; we used to do this still running from ROM,
845 * where had to use getenv_r(), which can be pretty slow when
846 * the environment is in EEPROM.
fe8c2806 847 */
7abf0c58 848
6d0f6bcf 849#if defined(CONFIG_SYS_EXTBDINFO)
7abf0c58
WD
850#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
851#if defined(CONFIG_I2CFAST)
852 /*
853 * set bi_iic_fast for linux taking environment variable
854 * "i2cfast" into account
855 */
856 {
857 char *s = getenv ("i2cfast");
858 if (s && ((*s == 'y') || (*s == 'Y'))) {
859 bd->bi_iic_fast[0] = 1;
860 bd->bi_iic_fast[1] = 1;
861 } else {
862 bd->bi_iic_fast[0] = 0;
863 bd->bi_iic_fast[1] = 0;
864 }
865 }
866#else
867 bd->bi_iic_fast[0] = 0;
868 bd->bi_iic_fast[1] = 0;
869#endif /* CONFIG_I2CFAST */
870#endif /* CONFIG_405GP, CONFIG_405EP */
6d0f6bcf 871#endif /* CONFIG_SYS_EXTBDINFO */
7abf0c58 872
9045f33c 873#if defined(CONFIG_SC3)
ca43ba18
HS
874 sc3_read_eeprom();
875#endif
d59feffb 876
6d0f6bcf 877#if defined (CONFIG_ID_EEPROM) || defined (CONFIG_SYS_I2C_MAC_OFFSET)
d59feffb
HW
878 mac_read_from_eeprom();
879#endif
880
fe8c2806 881 s = getenv ("ethaddr");
fe8c2806
WD
882 for (i = 0; i < 6; ++i) {
883 bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
884 if (s)
885 s = (*e) ? e + 1 : e;
886 }
887#ifdef CONFIG_HERMES
888 if ((gd->board_type >> 16) == 2)
889 bd->bi_ethspeed = gd->board_type & 0xFFFF;
890 else
891 bd->bi_ethspeed = 0xFFFF;
892#endif
893
e2ffd59b 894#ifdef CONFIG_HAS_ETH1
fe8c2806
WD
895 /* handle the 2nd ethernet address */
896
897 s = getenv ("eth1addr");
898
899 for (i = 0; i < 6; ++i) {
900 bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
901 if (s)
902 s = (*e) ? e + 1 : e;
903 }
904#endif
e2ffd59b 905#ifdef CONFIG_HAS_ETH2
fe8c2806
WD
906 /* handle the 3rd ethernet address */
907
908 s = getenv ("eth2addr");
fe8c2806
WD
909 for (i = 0; i < 6; ++i) {
910 bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
911 if (s)
912 s = (*e) ? e + 1 : e;
913 }
914#endif
915
e2ffd59b 916#ifdef CONFIG_HAS_ETH3
ba56f625
WD
917 /* handle 4th ethernet address */
918 s = getenv("eth3addr");
ba56f625
WD
919 for (i = 0; i < 6; ++i) {
920 bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
921 if (s)
922 s = (*e) ? e + 1 : e;
923 }
924#endif
fe8c2806 925
c68a05fe 926#ifdef CONFIG_HAS_ETH4
927 /* handle 5th ethernet address */
928 s = getenv("eth4addr");
c68a05fe 929 for (i = 0; i < 6; ++i) {
930 bd->bi_enet4addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
931 if (s)
932 s = (*e) ? e + 1 : e;
933 }
934#endif
935
936#ifdef CONFIG_HAS_ETH5
937 /* handle 6th ethernet address */
938 s = getenv("eth5addr");
c68a05fe 939 for (i = 0; i < 6; ++i) {
940 bd->bi_enet5addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
941 if (s)
942 s = (*e) ? e + 1 : e;
943 }
944#endif
945
fe8c2806 946#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
fa230445 947 defined(CONFIG_TQM8272) || \
566a494f
HS
948 defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || \
949 defined(CONFIG_KUP4X) || defined(CONFIG_PCS440EP)
fe8c2806
WD
950 load_sernum_ethaddr ();
951#endif
952 /* IP Address */
953 bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
954
955 WATCHDOG_RESET ();
956
979bdbc7 957#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45)
fe8c2806
WD
958 /*
959 * Do pci configuration
960 */
961 pci_init ();
962#endif
963
964/** leave this here (after malloc(), environment and PCI are working) **/
965 /* Initialize devices */
966 devices_init ();
967
27b207fd
WD
968 /* Initialize the jump table for applications */
969 jumptable_init ();
fe8c2806 970
500856eb
RJ
971#if defined(CONFIG_API)
972 /* Initialize API */
973 api_init ();
974#endif
975
fe8c2806
WD
976 /* Initialize the console (after the relocation and devices init) */
977 console_init_r ();
fe8c2806
WD
978
979#if defined(CONFIG_CCM) || \
980 defined(CONFIG_COGENT) || \
981 defined(CONFIG_CPCI405) || \
982 defined(CONFIG_EVB64260) || \
56f94be3 983 defined(CONFIG_KUP4K) || \
0608e04d 984 defined(CONFIG_KUP4X) || \
fe8c2806
WD
985 defined(CONFIG_LWMON) || \
986 defined(CONFIG_PCU_E) || \
9045f33c 987 defined(CONFIG_SC3) || \
fe8c2806
WD
988 defined(CONFIG_W7O) || \
989 defined(CONFIG_MISC_INIT_R)
990 /* miscellaneous platform dependent initialisations */
991 misc_init_r ();
992#endif
993
994#ifdef CONFIG_HERMES
995 if (bd->bi_ethspeed != 0xFFFF)
996 hermes_start_lxt980 ((int) bd->bi_ethspeed);
997#endif
998
7def6b34 999#if defined(CONFIG_CMD_KGDB)
fe8c2806
WD
1000 WATCHDOG_RESET ();
1001 puts ("KGDB: ");
1002 kgdb_init ();
1003#endif
1004
9d2b18a0 1005 debug ("U-Boot relocated to %08lx\n", dest_addr);
fe8c2806
WD
1006
1007 /*
1008 * Enable Interrupts
1009 */
1010 interrupt_init ();
1011
1012 /* Must happen after interrupts are initialized since
1013 * an irq handler gets installed
1014 */
42dfe7a1 1015#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD
1016 serial_buffered_init();
1017#endif
1018
566a494f 1019#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
fe8c2806
WD
1020 status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
1021#endif
1022
1023 udelay (20);
1024
1025 set_timer (0);
1026
fe8c2806
WD
1027 /* Initialize from environment */
1028 if ((s = getenv ("loadaddr")) != NULL) {
1029 load_addr = simple_strtoul (s, NULL, 16);
1030 }
7def6b34 1031#if defined(CONFIG_CMD_NET)
fe8c2806
WD
1032 if ((s = getenv ("bootfile")) != NULL) {
1033 copy_filename (BootFile, s, sizeof (BootFile));
1034 }
b3aff0cb 1035#endif
fe8c2806
WD
1036
1037 WATCHDOG_RESET ();
1038
9c2d63ec
HS
1039#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */
1040 dtt_init ();
1041#endif
7def6b34 1042#if defined(CONFIG_CMD_SCSI)
fe8c2806
WD
1043 WATCHDOG_RESET ();
1044 puts ("SCSI: ");
1045 scsi_init ();
1046#endif
1047
272cc70b
AF
1048#ifdef CONFIG_GENERIC_MMC
1049 WATCHDOG_RESET ();
1050 puts ("MMC: ");
1051 mmc_initialize (bd);
1052#endif
1053
7def6b34 1054#if defined(CONFIG_CMD_DOC)
fe8c2806
WD
1055 WATCHDOG_RESET ();
1056 puts ("DOC: ");
1057 doc_init ();
1058#endif
1059
7def6b34 1060#if defined(CONFIG_CMD_NET)
63ff004c 1061#if defined(CONFIG_NET_MULTI)
fe8c2806
WD
1062 WATCHDOG_RESET ();
1063 puts ("Net: ");
63ff004c 1064#endif
fe8c2806
WD
1065 eth_initialize (bd);
1066#endif
1067
7def6b34 1068#if defined(CONFIG_CMD_NET) && ( \
63ff004c
MB
1069 defined(CONFIG_CCM) || \
1070 defined(CONFIG_ELPT860) || \
1071 defined(CONFIG_EP8260) || \
1072 defined(CONFIG_IP860) || \
1073 defined(CONFIG_IVML24) || \
1074 defined(CONFIG_IVMS8) || \
1075 defined(CONFIG_MPC8260ADS) || \
1076 defined(CONFIG_MPC8266ADS) || \
1077 defined(CONFIG_MPC8560ADS) || \
1078 defined(CONFIG_PCU_E) || \
1079 defined(CONFIG_RPXSUPER) || \
1080 defined(CONFIG_STXGP3) || \
1081 defined(CONFIG_SPD823TS) || \
1082 defined(CONFIG_RESET_PHY_R) )
1083
1084 WATCHDOG_RESET ();
1085 debug ("Reset Ethernet PHY\n");
1086 reset_phy ();
1087#endif
1088
fe8c2806 1089#ifdef CONFIG_POST
6dff5529 1090 post_run (NULL, POST_RAM | post_bootmode_get(0));
fe8c2806
WD
1091#endif
1092
7def6b34
JL
1093#if defined(CONFIG_CMD_PCMCIA) \
1094 && !defined(CONFIG_CMD_IDE)
fe8c2806
WD
1095 WATCHDOG_RESET ();
1096 puts ("PCMCIA:");
1097 pcmcia_init ();
1098#endif
1099
7def6b34 1100#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
1101 WATCHDOG_RESET ();
1102# ifdef CONFIG_IDE_8xx_PCCARD
1103 puts ("PCMCIA:");
1104# else
1105 puts ("IDE: ");
1106#endif
ca43ba18
HS
1107#if defined(CONFIG_START_IDE)
1108 if (board_start_ide())
1109 ide_init ();
1110#else
fe8c2806 1111 ide_init ();
ca43ba18 1112#endif
b3aff0cb 1113#endif
fe8c2806
WD
1114
1115#ifdef CONFIG_LAST_STAGE_INIT
1116 WATCHDOG_RESET ();
1117 /*
1118 * Some parts can be only initialized if all others (like
1119 * Interrupts) are up and running (i.e. the PC-style ISA
1120 * keyboard).
1121 */
1122 last_stage_init ();
1123#endif
1124
7def6b34 1125#if defined(CONFIG_CMD_BEDBUG)
fe8c2806
WD
1126 WATCHDOG_RESET ();
1127 bedbug_init ();
1128#endif
1129
228f29ac 1130#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
fe8c2806
WD
1131 /*
1132 * Export available size of memory for Linux,
1133 * taking into account the protected RAM at top of memory
1134 */
1135 {
1136 ulong pram;
fe8c2806 1137 uchar memsz[32];
228f29ac
WD
1138#ifdef CONFIG_PRAM
1139 char *s;
fe8c2806
WD
1140
1141 if ((s = getenv ("pram")) != NULL) {
1142 pram = simple_strtoul (s, NULL, 10);
1143 } else {
1144 pram = CONFIG_PRAM;
1145 }
228f29ac
WD
1146#else
1147 pram=0;
1148#endif
1149#ifdef CONFIG_LOGBUFFER
3d610186 1150#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
1151 /* Also take the logbuffer into account (pram is in kB) */
1152 pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
3d610186 1153#endif
228f29ac 1154#endif
77ddac94
WD
1155 sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
1156 setenv ("mem", (char *)memsz);
fe8c2806
WD
1157 }
1158#endif
1159
1c43771b
WD
1160#ifdef CONFIG_PS2KBD
1161 puts ("PS/2: ");
1162 kbd_init();
1163#endif
1164
4532cb69
WD
1165#ifdef CONFIG_MODEM_SUPPORT
1166 {
1167 extern int do_mdm_init;
1168 do_mdm_init = gd->do_mdm_init;
1169 }
1170#endif
1171
fe8c2806
WD
1172 /* Initialization complete - start the monitor */
1173
1174 /* main_loop() can return to retry autoboot, if so just run it again. */
1175 for (;;) {
1176 WATCHDOG_RESET ();
1177 main_loop ();
1178 }
1179
1180 /* NOTREACHED - no way out of command loop except booting */
1181}
1182
1183void hang (void)
1184{
1185 puts ("### ERROR ### Please RESET the board ###\n");
63e73c9a 1186 show_boot_progress(-30);
fe8c2806
WD
1187 for (;;);
1188}
1189
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1190#ifdef CONFIG_MODEM_SUPPORT
1191/* called from main loop (common/main.c) */
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1192/* 'inline' - We have to do it fast */
1193static inline void mdm_readline(char *buf, int bufsiz)
1194{
1195 char c;
1196 char *p;
1197 int n;
1198
1199 n = 0;
1200 p = buf;
1201 for(;;) {
1202 c = serial_getc();
1203
1204 /* dbg("(%c)", c); */
1205
1206 switch(c) {
1207 case '\r':
1208 break;
1209 case '\n':
1210 *p = '\0';
1211 return;
1212
1213 default:
1214 if(n++ > bufsiz) {
1215 *p = '\0';
1216 return; /* sanity check */
1217 }
1218 *p = c;
1219 p++;
1220 break;
1221 }
1222 }
1223}
1224
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1225extern void dbg(const char *fmt, ...);
1226int mdm_init (void)
1227{
1228 char env_str[16];
1229 char *init_str;
1230 int i;
1231 extern char console_buffer[];
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1232 extern void enable_putc(void);
1233 extern int hwflow_onoff(int);
1234
1235 enable_putc(); /* enable serial_putc() */
1236
1237#ifdef CONFIG_HWFLOW
1238 init_str = getenv("mdm_flow_control");
1239 if (init_str && (strcmp(init_str, "rts/cts") == 0))
1240 hwflow_onoff (1);
1241 else
1242 hwflow_onoff(-1);
1243#endif
1244
1245 for (i = 1;;i++) {
1246 sprintf(env_str, "mdm_init%d", i);
1247 if ((init_str = getenv(env_str)) != NULL) {
1248 serial_puts(init_str);
1249 serial_puts("\n");
1250 for(;;) {
6d0f6bcf 1251 mdm_readline(console_buffer, CONFIG_SYS_CBSIZE);
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1252 dbg("ini%d: [%s]", i, console_buffer);
1253
1254 if ((strcmp(console_buffer, "OK") == 0) ||
1255 (strcmp(console_buffer, "ERROR") == 0)) {
1256 dbg("ini%d: cmd done", i);
1257 break;
1258 } else /* in case we are originating call ... */
1259 if (strncmp(console_buffer, "CONNECT", 7) == 0) {
1260 dbg("ini%d: connect", i);
1261 return 0;
1262 }
1263 }
1264 } else
1265 break; /* no init string - stop modem init */
1266
1267 udelay(100000);
1268 }
1269
1270 udelay(100000);
1271
1272 /* final stage - wait for connect */
1273 for(;i > 1;) { /* if 'i' > 1 - wait for connection
1274 message from modem */
6d0f6bcf 1275 mdm_readline(console_buffer, CONFIG_SYS_CBSIZE);
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1276 dbg("ini_f: [%s]", console_buffer);
1277 if (strncmp(console_buffer, "CONNECT", 7) == 0) {
1278 dbg("ini_f: connected");
1279 return 0;
1280 }
1281 }
1282
1283 return 0;
1284}
1285
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1286#endif
1287
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1288#if 0 /* We could use plain global data, but the resulting code is bigger */
1289/*
1290 * Pointer to initial global data area
1291 *
1292 * Here we initialize it.
1293 */
1294#undef XTRN_DECLARE_GLOBAL_DATA_PTR
1295#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
6d0f6bcf 1296DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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1297#endif /* 0 */
1298
1299/************************************************************************/