]>
Commit | Line | Data |
---|---|---|
3f7f6b85 RZ |
1 | /* |
2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
3 | * Author: Roy Zang <tie-fei.zang@freescale.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
3f7f6b85 RZ |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <ns16550.h> | |
10 | #include <asm/io.h> | |
11 | #include <nand.h> | |
12 | #include <asm/fsl_law.h> | |
5614e71b | 13 | #include <fsl_ddr_sdram.h> |
02ea538c MM |
14 | #include <asm/global_data.h> |
15 | ||
16 | DECLARE_GLOBAL_DATA_PTR; | |
3f7f6b85 RZ |
17 | |
18 | /* Fixed sdram init -- doesn't use serial presence detect. */ | |
19 | void sdram_init(void) | |
20 | { | |
9a17eb5b YS |
21 | struct ccsr_ddr __iomem *ddr = |
22 | (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; | |
3f7f6b85 RZ |
23 | |
24 | set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); | |
25 | ||
ae6beb24 MM |
26 | __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); |
27 | __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); | |
28 | __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); | |
29 | __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); | |
30 | __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); | |
31 | __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); | |
32 | __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); | |
33 | __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); | |
34 | __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2); | |
35 | __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); | |
36 | __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); | |
37 | __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); | |
38 | __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); | |
39 | __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); | |
40 | __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); | |
41 | __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); | |
42 | __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl); | |
43 | __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl); | |
44 | __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1); | |
45 | __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2); | |
02ea538c | 46 | /* Set, but do not enable the memory */ |
ae6beb24 | 47 | __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); |
02ea538c MM |
48 | |
49 | asm volatile("sync;isync"); | |
50 | udelay(500); | |
51 | ||
52 | /* Let the controller go */ | |
53 | out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); | |
3f7f6b85 RZ |
54 | } |
55 | ||
56 | void board_init_f(ulong bootflag) | |
57 | { | |
02ea538c | 58 | u32 plat_ratio; |
3f7f6b85 RZ |
59 | ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
60 | ||
61 | /* initialize selected port with appropriate baud rate */ | |
62 | plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; | |
63 | plat_ratio >>= 1; | |
02ea538c | 64 | gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; |
3f7f6b85 | 65 | NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
02ea538c | 66 | gd->bus_clk / 16 / CONFIG_BAUDRATE); |
3f7f6b85 RZ |
67 | |
68 | puts("\nNAND boot... "); | |
69 | /* Initialize the DDR3 */ | |
70 | sdram_init(); | |
71 | /* copy code to RAM and jump to it - this should not return */ | |
72 | /* NOTE - code has to be copied out of NAND buffer before | |
73 | * other blocks can be read. | |
74 | */ | |
75 | relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, | |
76 | CONFIG_SYS_NAND_U_BOOT_RELOC); | |
77 | } | |
78 | ||
79 | void board_init_r(gd_t *gd, ulong dest_addr) | |
80 | { | |
81 | nand_boot(); | |
82 | } | |
83 | ||
84 | void putc(char c) | |
85 | { | |
86 | if (c == '\n') | |
87 | NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); | |
88 | ||
89 | NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); | |
90 | } | |
91 | ||
92 | void puts(const char *str) | |
93 | { | |
94 | while (*str) | |
95 | putc(*str++); | |
96 | } |