[people/ms/u-boot.git] / nand_spl / nand_boot.c

/*
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <nand.h>
#include <asm/io.h>

#define CFG_NAND_READ_DELAY \
	{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }

static int nand_ecc_pos[] = CFG_NAND_ECCPOS;

extern void board_nand_init(struct nand_chip *nand);

#if (CFG_NAND_PAGE_SIZE <= 512)
/*
 * NAND command for small page NAND devices (512)
 */
static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
{
	struct nand_chip *this = mtd->priv;
	int page_addr = page + block * CFG_NAND_PAGE_COUNT;
	int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;

	if (this->dev_ready)
		while (!this->dev_ready(mtd))
			;
	else
		CFG_NAND_READ_DELAY;

	/* Begin command latch cycle */
	this->cmd_ctrl(mtd, cmd, ctrl);
	/* Set ALE and clear CLE to start address cycle */
	ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
	/* Column address */
	this->cmd_ctrl(mtd, offs, ctrl);
	ctrl &= ~NAND_CTRL_CHANGE;
	this->cmd_ctrl(mtd, (u8)(page_addr & 0xff), ctrl);	/* A[16:9] */
	ctrl &= ~NAND_CTRL_CHANGE;
	this->cmd_ctrl(mtd, (u8)((page_addr >> 8) & 0xff), ctrl); /* A[24:17] */
#ifdef CFG_NAND_4_ADDR_CYCLE
	/* One more address cycle for devices > 32MiB */
	this->cmd_ctrl(mtd, (u8)((page_addr >> 16) & 0x0f), ctrl); /* A[xx:25] */
#endif
	/* Latch in address */
	this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

	/*
	 * Wait a while for the data to be ready
	 */
	if (this->dev_ready)
		while (!this->dev_ready(mtd))
			;
	else
		CFG_NAND_READ_DELAY;

	return 0;
}
#else
/*
 * NAND command for large page NAND devices (2k)
 */
static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
{
	struct nand_chip *this = mtd->priv;
	int page_offs = offs;
	int page_addr = page + block * CFG_NAND_PAGE_COUNT;

	if (this->dev_ready)
		this->dev_ready(mtd);
	else
		CFG_NAND_READ_DELAY;

	/* Emulate NAND_CMD_READOOB */
	if (cmd == NAND_CMD_READOOB) {
		page_offs += CFG_NAND_PAGE_SIZE;
		cmd = NAND_CMD_READ0;
	}

	/* Begin command latch cycle */
	this->hwcontrol(mtd, NAND_CTL_SETCLE);
	this->write_byte(mtd, cmd);
	/* Set ALE and clear CLE to start address cycle */
	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
	this->hwcontrol(mtd, NAND_CTL_SETALE);
	/* Column address */
	this->write_byte(mtd, page_offs & 0xff);			/* A[7:0] */
	this->write_byte(mtd, (uchar)((page_offs >> 8) & 0xff));	/* A[11:9] */
	/* Row address */
	this->write_byte(mtd, (uchar)(page_addr & 0xff));		/* A[19:12] */
	this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff));	/* A[27:20] */
#ifdef CFG_NAND_5_ADDR_CYCLE
	/* One more address cycle for devices > 128MiB */
	this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f));	/* A[xx:28] */
#endif
	/* Latch in address */
	this->hwcontrol(mtd, NAND_CTL_CLRALE);

	/* Begin command latch cycle */
	this->hwcontrol(mtd, NAND_CTL_SETCLE);
	/* Write out the start read command */
	this->write_byte(mtd, NAND_CMD_READSTART);
	/* End command latch cycle */
	this->hwcontrol(mtd, NAND_CTL_CLRCLE);

	/*
	 * Wait a while for the data to be ready
	 */
	if (this->dev_ready)
		this->dev_ready(mtd);
	else
		CFG_NAND_READ_DELAY;

	return 0;
}
#endif

static int nand_is_bad_block(struct mtd_info *mtd, int block)
{
	struct nand_chip *this = mtd->priv;

	nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);

	/*
	 * Read one byte
	 */
	if (in_8(this->IO_ADDR_R) != 0xff)
		return 1;

	return 0;
}

static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
{
	struct nand_chip *this = mtd->priv;
	u_char *ecc_calc;
	u_char *ecc_code;
	u_char *oob_data;
	int i;
	int eccsize = CFG_NAND_ECCSIZE;
	int eccbytes = CFG_NAND_ECCBYTES;
	int eccsteps = CFG_NAND_ECCSTEPS;
	uint8_t *p = dst;
	int stat;

	nand_command(mtd, block, page, 0, NAND_CMD_READ0);

	/* No malloc available for now, just use some temporary locations
	 * in SDRAM
	 */
	ecc_calc = (u_char *)(CFG_SDRAM_BASE + 0x10000);
	ecc_code = ecc_calc + 0x100;
	oob_data = ecc_calc + 0x200;

	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		this->ecc.hwctl(mtd, NAND_ECC_READ);
		this->read_buf(mtd, p, eccsize);
		this->ecc.calculate(mtd, p, &ecc_calc[i]);
	}
	this->read_buf(mtd, oob_data, CFG_NAND_OOBSIZE);

	/* Pick the ECC bytes out of the oob data */
	for (i = 0; i < CFG_NAND_ECCTOTAL; i++)
		ecc_code[i] = oob_data[nand_ecc_pos[i]];

	eccsteps = CFG_NAND_ECCSTEPS;
	p = dst;

	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		/* No chance to do something with the possible error message
		 * from correct_data(). We just hope that all possible errors
		 * are corrected by this routine.
		 */
		stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
	}

	return 0;
}

static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst)
{
	int block;
	int blockcopy_count;
	int page;

	/*
	 * offs has to be aligned to a block address!
	 */
	block = offs / CFG_NAND_BLOCK_SIZE;
	blockcopy_count = 0;

	while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) {
		if (!nand_is_bad_block(mtd, block)) {
			/*
			 * Skip bad blocks
			 */
			for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) {
				nand_read_page(mtd, block, page, dst);
				dst += CFG_NAND_PAGE_SIZE;
			}

			blockcopy_count++;
		}

		block++;
	}

	return 0;
}

/*
 * The main entry for NAND booting. It's necessary that SDRAM is already
 * configured and available since this code loads the main U-Boot image
 * from NAND into SDRAM and starts it from there.
 */
void nand_boot(void)
{
	struct nand_chip nand_chip;
	nand_info_t nand_info;
	int ret;
	void (*uboot)(void);

	/*
	 * Init board specific nand support
	 */
	nand_info.priv = &nand_chip;
	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CFG_NAND_BASE;
	nand_chip.dev_ready = NULL;	/* preset to NULL */
	board_nand_init(&nand_chip);

	/*
	 * Load U-Boot image from NAND into RAM
	 */
	ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
			(uchar *)CFG_NAND_U_BOOT_DST);

	/*
	 * Jump to U-Boot image
	 */
	uboot = (void (*)(void))CFG_NAND_U_BOOT_START;
	(*uboot)();
}
Commit	Line	Data
887e2ec9	1	/*
46f37383	2	* (C) Copyright 2006-2008
887e2ec9 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
	20
	21	#include <common.h>
	22	#include <nand.h>
c568f77a	23	#include <asm/io.h>
887e2ec9 SR	24
	25	#define CFG_NAND_READ_DELAY \
	26	{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
	27
42be56f5 SR	28	static int nand_ecc_pos[] = CFG_NAND_ECCPOS;
42be56f5 SR	29
887e2ec9	30	extern void board_nand_init(struct nand_chip *nand);
887e2ec9	31
46f37383 SR	32	#if (CFG_NAND_PAGE_SIZE <= 512)
	33	/*
	34	* NAND command for small page NAND devices (512)
	35	*/
42be56f5	36	static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
887e2ec9	37	{
511d0c72	38	struct nand_chip *this = mtd->priv;
42be56f5	39	int page_addr = page + block * CFG_NAND_PAGE_COUNT;
c568f77a	40	int ctrl = NAND_CTRL_CLE \| NAND_CTRL_CHANGE;
42be56f5 SR	41
42be56f5 SR	42	if (this->dev_ready)
c568f77a SR	43	while (!this->dev_ready(mtd))
c568f77a SR	44	;
42be56f5 SR	45	else
42be56f5 SR	46	CFG_NAND_READ_DELAY;
887e2ec9 SR	47
887e2ec9 SR	48	/* Begin command latch cycle */
c568f77a	49	this->cmd_ctrl(mtd, cmd, ctrl);
887e2ec9	50	/* Set ALE and clear CLE to start address cycle */
c568f77a	51	ctrl = NAND_CTRL_ALE \| NAND_CTRL_CHANGE;
887e2ec9	52	/* Column address */
c568f77a SR	53	this->cmd_ctrl(mtd, offs, ctrl);
	54	ctrl &= ~NAND_CTRL_CHANGE;
	55	this->cmd_ctrl(mtd, (u8)(page_addr & 0xff), ctrl); /* A[16:9] */
	56	ctrl &= ~NAND_CTRL_CHANGE;
	57	this->cmd_ctrl(mtd, (u8)((page_addr >> 8) & 0xff), ctrl); /* A[24:17] */
887e2ec9 SR	58	#ifdef CFG_NAND_4_ADDR_CYCLE
887e2ec9 SR	59	/* One more address cycle for devices > 32MiB */
c568f77a	60	this->cmd_ctrl(mtd, (u8)((page_addr >> 16) & 0x0f), ctrl); /* A[xx:25] */
887e2ec9 SR	61	#endif
887e2ec9 SR	62	/* Latch in address */
c568f77a	63	this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
887e2ec9 SR	64
	65	/*
	66	* Wait a while for the data to be ready
	67	*/
	68	if (this->dev_ready)
c568f77a SR	69	while (!this->dev_ready(mtd))
c568f77a SR	70	;
887e2ec9 SR	71	else
	72	CFG_NAND_READ_DELAY;
	73
42be56f5 SR	74	return 0;
42be56f5 SR	75	}
46f37383 SR	76	#else
	77	/*
	78	* NAND command for large page NAND devices (2k)
	79	*/
	80	static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
	81	{
	82	struct nand_chip *this = mtd->priv;
	83	int page_offs = offs;
	84	int page_addr = page + block * CFG_NAND_PAGE_COUNT;
	85
	86	if (this->dev_ready)
	87	this->dev_ready(mtd);
	88	else
	89	CFG_NAND_READ_DELAY;
	90
	91	/* Emulate NAND_CMD_READOOB */
	92	if (cmd == NAND_CMD_READOOB) {
	93	page_offs += CFG_NAND_PAGE_SIZE;
	94	cmd = NAND_CMD_READ0;
	95	}
	96
	97	/* Begin command latch cycle */
	98	this->hwcontrol(mtd, NAND_CTL_SETCLE);
	99	this->write_byte(mtd, cmd);
	100	/* Set ALE and clear CLE to start address cycle */
	101	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
	102	this->hwcontrol(mtd, NAND_CTL_SETALE);
	103	/* Column address */
	104	this->write_byte(mtd, page_offs & 0xff); /* A[7:0] */
	105	this->write_byte(mtd, (uchar)((page_offs >> 8) & 0xff)); /* A[11:9] */
	106	/* Row address */
	107	this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[19:12] */
	108	this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[27:20] */
	109	#ifdef CFG_NAND_5_ADDR_CYCLE
	110	/* One more address cycle for devices > 128MiB */
	111	this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:28] */
	112	#endif
	113	/* Latch in address */
	114	this->hwcontrol(mtd, NAND_CTL_CLRALE);
	115
	116	/* Begin command latch cycle */
	117	this->hwcontrol(mtd, NAND_CTL_SETCLE);
	118	/* Write out the start read command */
	119	this->write_byte(mtd, NAND_CMD_READSTART);
	120	/* End command latch cycle */
	121	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
	122
	123	/*
	124	* Wait a while for the data to be ready
	125	*/
	126	if (this->dev_ready)
	127	this->dev_ready(mtd);
	128	else
	129	CFG_NAND_READ_DELAY;
	130
	131	return 0;
	132	}
	133	#endif
42be56f5 SR	134
	135	static int nand_is_bad_block(struct mtd_info *mtd, int block)
	136	{
	137	struct nand_chip *this = mtd->priv;
	138
	139	nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
	140
887e2ec9	141	/*
10c7382b	142	* Read one byte
887e2ec9	143	*/
c568f77a	144	if (in_8(this->IO_ADDR_R) != 0xff)
887e2ec9 SR	145	return 1;
	146
	147	return 0;
	148	}
	149
	150	static int nand_read_page(struct mtd_info mtd, int block, int page, uchar dst)
	151	{
511d0c72	152	struct nand_chip *this = mtd->priv;
42be56f5 SR	153	u_char *ecc_calc;
	154	u_char *ecc_code;
	155	u_char *oob_data;
887e2ec9	156	int i;
42be56f5 SR	157	int eccsize = CFG_NAND_ECCSIZE;
	158	int eccbytes = CFG_NAND_ECCBYTES;
	159	int eccsteps = CFG_NAND_ECCSTEPS;
	160	uint8_t *p = dst;
	161	int stat;
887e2ec9	162
42be56f5	163	nand_command(mtd, block, page, 0, NAND_CMD_READ0);
887e2ec9	164
42be56f5 SR	165	/* No malloc available for now, just use some temporary locations
42be56f5 SR	166	* in SDRAM
887e2ec9	167	*/
42be56f5 SR	168	ecc_calc = (u_char *)(CFG_SDRAM_BASE + 0x10000);
	169	ecc_code = ecc_calc + 0x100;
	170	oob_data = ecc_calc + 0x200;
	171
	172	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
c568f77a	173	this->ecc.hwctl(mtd, NAND_ECC_READ);
42be56f5	174	this->read_buf(mtd, p, eccsize);
c568f77a	175	this->ecc.calculate(mtd, p, &ecc_calc[i]);
42be56f5 SR	176	}
	177	this->read_buf(mtd, oob_data, CFG_NAND_OOBSIZE);
	178
	179	/* Pick the ECC bytes out of the oob data */
	180	for (i = 0; i < CFG_NAND_ECCTOTAL; i++)
	181	ecc_code[i] = oob_data[nand_ecc_pos[i]];
	182
	183	eccsteps = CFG_NAND_ECCSTEPS;
	184	p = dst;
	185
	186	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
	187	/* No chance to do something with the possible error message
	188	* from correct_data(). We just hope that all possible errors
	189	* are corrected by this routine.
	190	*/
c568f77a	191	stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
42be56f5	192	}
887e2ec9 SR	193
	194	return 0;
	195	}
	196
	197	static int nand_load(struct mtd_info mtd, int offs, int uboot_size, uchar dst)
	198	{
	199	int block;
	200	int blockcopy_count;
	201	int page;
	202
	203	/*
	204	* offs has to be aligned to a block address!
	205	*/
	206	block = offs / CFG_NAND_BLOCK_SIZE;
	207	blockcopy_count = 0;
	208
	209	while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) {
	210	if (!nand_is_bad_block(mtd, block)) {
	211	/*
	212	* Skip bad blocks
	213	*/
	214	for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) {
	215	nand_read_page(mtd, block, page, dst);
	216	dst += CFG_NAND_PAGE_SIZE;
	217	}
	218
	219	blockcopy_count++;
	220	}
	221
	222	block++;
	223	}
	224
	225	return 0;
	226	}
	227
64852d09 SR	228	/*
	229	* The main entry for NAND booting. It's necessary that SDRAM is already
	230	* configured and available since this code loads the main U-Boot image
	231	* from NAND into SDRAM and starts it from there.
	232	*/
887e2ec9 SR	233	void nand_boot(void)
887e2ec9 SR	234	{
887e2ec9 SR	235	struct nand_chip nand_chip;
	236	nand_info_t nand_info;
	237	int ret;
	238	void (*uboot)(void);
	239
887e2ec9 SR	240	/*
	241	* Init board specific nand support
	242	*/
	243	nand_info.priv = &nand_chip;
	244	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_NAND_BASE;
	245	nand_chip.dev_ready = NULL; /* preset to NULL */
	246	board_nand_init(&nand_chip);
	247
	248	/*
	249	* Load U-Boot image from NAND into RAM
	250	*/
d12ae808	251	ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
887e2ec9 SR	252	(uchar *)CFG_NAND_U_BOOT_DST);
	253
	254	/*
	255	* Jump to U-Boot image
	256	*/
	257	uboot = (void (*)(void))CFG_NAND_U_BOOT_START;
	258	(*uboot)();
	259	}