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ad5bb451 WD |
1 | /* |
2 | * Copyright (C) 2002 Wolfgang Denk <wd@denx.de> | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
ad5bb451 WD |
5 | */ |
6 | ||
7 | #include <config.h> | |
8 | ||
ad5bb451 WD |
9 | #if defined(CONFIG_MPC823) || \ |
10 | defined(CONFIG_MPC850) || \ | |
11 | defined(CONFIG_MPC855) || \ | |
12 | defined(CONFIG_MPC860) || \ | |
13 | defined(CONFIG_MPC862) | |
14 | ||
15 | #include <post.h> | |
16 | #include <ppc_asm.tmpl> | |
17 | #include <ppc_defs.h> | |
18 | #include <asm/cache.h> | |
19 | ||
6d0f6bcf | 20 | #if CONFIG_POST & CONFIG_SYS_POST_CACHE |
ad5bb451 WD |
21 | |
22 | .text | |
23 | ||
24 | cache_post_dinvalidate: | |
25 | lis r10, IDC_INVALL@h | |
26 | mtspr DC_CST, r10 | |
27 | blr | |
28 | ||
29 | cache_post_iinvalidate: | |
30 | lis r10, IDC_INVALL@h | |
31 | mtspr IC_CST, r10 | |
32 | isync | |
33 | blr | |
34 | ||
35 | cache_post_ddisable: | |
36 | lis r10, IDC_DISABLE@h | |
37 | mtspr DC_CST, r10 | |
38 | blr | |
39 | ||
40 | cache_post_dwb: | |
41 | lis r10, IDC_ENABLE@h | |
42 | mtspr DC_CST, r10 | |
43 | lis r10, DC_CFWT@h | |
44 | mtspr DC_CST, r10 | |
45 | blr | |
46 | ||
47 | cache_post_dwt: | |
48 | lis r10, IDC_ENABLE@h | |
49 | mtspr DC_CST, r10 | |
50 | lis r10, DC_SFWT@h | |
51 | mtspr DC_CST, r10 | |
52 | blr | |
53 | ||
54 | cache_post_idisable: | |
55 | lis r10, IDC_DISABLE@h | |
56 | mtspr IC_CST, r10 | |
57 | isync | |
58 | blr | |
59 | ||
60 | cache_post_ienable: | |
61 | lis r10, IDC_ENABLE@h | |
62 | mtspr IC_CST, r10 | |
63 | isync | |
64 | blr | |
65 | ||
66 | cache_post_iunlock: | |
67 | lis r10, IDC_UNALL@h | |
68 | mtspr IC_CST, r10 | |
69 | isync | |
70 | blr | |
71 | ||
72 | cache_post_ilock: | |
73 | mtspr IC_ADR, r3 | |
74 | lis r10, IDC_LDLCK@h | |
75 | mtspr IC_CST, r10 | |
76 | isync | |
77 | blr | |
78 | ||
79 | /* | |
80 | * turn on the data cache | |
81 | * switch the data cache to write-back or write-through mode | |
82 | * invalidate the data cache | |
83 | * write the negative pattern to a cached area | |
84 | * read the area | |
85 | * | |
86 | * The negative pattern must be read at the last step | |
87 | */ | |
88 | .global cache_post_test1 | |
89 | cache_post_test1: | |
90 | mflr r0 | |
91 | stw r0, 4(r1) | |
92 | ||
93 | stwu r3, -4(r1) | |
94 | stwu r4, -4(r1) | |
95 | ||
96 | bl cache_post_dwb | |
97 | bl cache_post_dinvalidate | |
98 | ||
99 | /* Write the negative pattern to the test area */ | |
100 | lwz r0, 0(r1) | |
101 | mtctr r0 | |
102 | li r0, 0xff | |
103 | lwz r3, 4(r1) | |
104 | subi r3, r3, 1 | |
105 | 1: | |
106 | stbu r0, 1(r3) | |
107 | bdnz 1b | |
108 | ||
109 | /* Read the test area */ | |
110 | lwz r0, 0(r1) | |
111 | mtctr r0 | |
112 | lwz r4, 4(r1) | |
113 | subi r4, r4, 1 | |
114 | li r3, 0 | |
115 | 1: | |
116 | lbzu r0, 1(r4) | |
117 | cmpli cr0, r0, 0xff | |
118 | beq 2f | |
119 | li r3, -1 | |
120 | b 3f | |
121 | 2: | |
122 | bdnz 1b | |
123 | 3: | |
124 | ||
125 | bl cache_post_ddisable | |
126 | bl cache_post_dinvalidate | |
127 | ||
128 | addi r1, r1, 8 | |
129 | ||
130 | lwz r0, 4(r1) | |
131 | mtlr r0 | |
132 | blr | |
133 | ||
134 | /* | |
135 | * turn on the data cache | |
136 | * switch the data cache to write-back or write-through mode | |
137 | * invalidate the data cache | |
138 | * write the zero pattern to a cached area | |
139 | * turn off the data cache | |
140 | * write the negative pattern to the area | |
141 | * turn on the data cache | |
142 | * read the area | |
143 | * | |
144 | * The negative pattern must be read at the last step | |
145 | */ | |
146 | .global cache_post_test2 | |
147 | cache_post_test2: | |
148 | mflr r0 | |
149 | stw r0, 4(r1) | |
150 | ||
151 | stwu r3, -4(r1) | |
152 | stwu r4, -4(r1) | |
153 | ||
154 | bl cache_post_dwb | |
155 | bl cache_post_dinvalidate | |
156 | ||
157 | /* Write the zero pattern to the test area */ | |
158 | lwz r0, 0(r1) | |
159 | mtctr r0 | |
160 | li r0, 0 | |
161 | lwz r3, 4(r1) | |
162 | subi r3, r3, 1 | |
163 | 1: | |
164 | stbu r0, 1(r3) | |
165 | bdnz 1b | |
166 | ||
167 | bl cache_post_ddisable | |
168 | ||
169 | /* Write the negative pattern to the test area */ | |
170 | lwz r0, 0(r1) | |
171 | mtctr r0 | |
172 | li r0, 0xff | |
173 | lwz r3, 4(r1) | |
174 | subi r3, r3, 1 | |
175 | 1: | |
176 | stbu r0, 1(r3) | |
177 | bdnz 1b | |
178 | ||
179 | bl cache_post_dwb | |
180 | ||
181 | /* Read the test area */ | |
182 | lwz r0, 0(r1) | |
183 | mtctr r0 | |
184 | lwz r4, 4(r1) | |
185 | subi r4, r4, 1 | |
186 | li r3, 0 | |
187 | 1: | |
188 | lbzu r0, 1(r4) | |
189 | cmpli cr0, r0, 0xff | |
190 | beq 2f | |
191 | li r3, -1 | |
192 | b 3f | |
193 | 2: | |
194 | bdnz 1b | |
195 | 3: | |
196 | ||
197 | bl cache_post_ddisable | |
198 | bl cache_post_dinvalidate | |
199 | ||
200 | addi r1, r1, 8 | |
201 | ||
202 | lwz r0, 4(r1) | |
203 | mtlr r0 | |
204 | blr | |
205 | ||
206 | /* | |
207 | * turn on the data cache | |
208 | * switch the data cache to write-through mode | |
209 | * invalidate the data cache | |
210 | * write the zero pattern to a cached area | |
211 | * flush the data cache | |
212 | * write the negative pattern to the area | |
213 | * turn off the data cache | |
214 | * read the area | |
215 | * | |
216 | * The negative pattern must be read at the last step | |
217 | */ | |
218 | .global cache_post_test3 | |
219 | cache_post_test3: | |
220 | mflr r0 | |
221 | stw r0, 4(r1) | |
222 | ||
223 | stwu r3, -4(r1) | |
224 | stwu r4, -4(r1) | |
225 | ||
226 | bl cache_post_ddisable | |
227 | bl cache_post_dinvalidate | |
228 | ||
229 | /* Write the zero pattern to the test area */ | |
230 | lwz r0, 0(r1) | |
231 | mtctr r0 | |
232 | li r0, 0 | |
233 | lwz r3, 4(r1) | |
234 | subi r3, r3, 1 | |
235 | 1: | |
236 | stbu r0, 1(r3) | |
237 | bdnz 1b | |
238 | ||
239 | bl cache_post_dwt | |
240 | bl cache_post_dinvalidate | |
241 | ||
242 | /* Write the negative pattern to the test area */ | |
243 | lwz r0, 0(r1) | |
244 | mtctr r0 | |
245 | li r0, 0xff | |
246 | lwz r3, 4(r1) | |
247 | subi r3, r3, 1 | |
248 | 1: | |
249 | stbu r0, 1(r3) | |
250 | bdnz 1b | |
251 | ||
252 | bl cache_post_ddisable | |
253 | bl cache_post_dinvalidate | |
254 | ||
255 | /* Read the test area */ | |
256 | lwz r0, 0(r1) | |
257 | mtctr r0 | |
258 | lwz r4, 4(r1) | |
259 | subi r4, r4, 1 | |
260 | li r3, 0 | |
261 | 1: | |
262 | lbzu r0, 1(r4) | |
263 | cmpli cr0, r0, 0xff | |
264 | beq 2f | |
265 | li r3, -1 | |
266 | b 3f | |
267 | 2: | |
268 | bdnz 1b | |
269 | 3: | |
270 | ||
271 | addi r1, r1, 8 | |
272 | ||
273 | lwz r0, 4(r1) | |
274 | mtlr r0 | |
275 | blr | |
276 | ||
277 | /* | |
278 | * turn on the data cache | |
279 | * switch the data cache to write-back mode | |
280 | * invalidate the data cache | |
281 | * write the negative pattern to a cached area | |
282 | * flush the data cache | |
283 | * write the zero pattern to the area | |
284 | * invalidate the data cache | |
285 | * read the area | |
286 | * | |
287 | * The negative pattern must be read at the last step | |
288 | */ | |
289 | .global cache_post_test4 | |
290 | cache_post_test4: | |
291 | mflr r0 | |
292 | stw r0, 4(r1) | |
293 | ||
294 | stwu r3, -4(r1) | |
295 | stwu r4, -4(r1) | |
296 | ||
297 | bl cache_post_ddisable | |
298 | bl cache_post_dinvalidate | |
299 | ||
300 | /* Write the negative pattern to the test area */ | |
301 | lwz r0, 0(r1) | |
302 | mtctr r0 | |
303 | li r0, 0xff | |
304 | lwz r3, 4(r1) | |
305 | subi r3, r3, 1 | |
306 | 1: | |
307 | stbu r0, 1(r3) | |
308 | bdnz 1b | |
309 | ||
310 | bl cache_post_dwb | |
311 | bl cache_post_dinvalidate | |
312 | ||
313 | /* Write the zero pattern to the test area */ | |
314 | lwz r0, 0(r1) | |
315 | mtctr r0 | |
316 | li r0, 0 | |
317 | lwz r3, 4(r1) | |
318 | subi r3, r3, 1 | |
319 | 1: | |
320 | stbu r0, 1(r3) | |
321 | bdnz 1b | |
322 | ||
323 | bl cache_post_ddisable | |
324 | bl cache_post_dinvalidate | |
325 | ||
326 | /* Read the test area */ | |
327 | lwz r0, 0(r1) | |
328 | mtctr r0 | |
329 | lwz r4, 4(r1) | |
330 | subi r4, r4, 1 | |
331 | li r3, 0 | |
332 | 1: | |
333 | lbzu r0, 1(r4) | |
334 | cmpli cr0, r0, 0xff | |
335 | beq 2f | |
336 | li r3, -1 | |
337 | b 3f | |
338 | 2: | |
339 | bdnz 1b | |
340 | 3: | |
341 | ||
342 | addi r1, r1, 8 | |
343 | ||
344 | lwz r0, 4(r1) | |
345 | mtlr r0 | |
346 | blr | |
347 | ||
348 | cache_post_test5_1: | |
349 | li r3, 0 | |
350 | cache_post_test5_2: | |
351 | li r3, -1 | |
352 | ||
353 | /* | |
354 | * turn on the instruction cache | |
355 | * unlock the entire instruction cache | |
356 | * invalidate the instruction cache | |
357 | * lock a branch instruction in the instruction cache | |
358 | * replace the branch instruction with "nop" | |
359 | * jump to the branch instruction | |
360 | * check that the branch instruction was executed | |
361 | */ | |
362 | .global cache_post_test5 | |
363 | cache_post_test5: | |
364 | mflr r0 | |
365 | stw r0, 4(r1) | |
366 | ||
367 | bl cache_post_ienable | |
368 | bl cache_post_iunlock | |
369 | bl cache_post_iinvalidate | |
370 | ||
371 | /* Compute r9 = cache_post_test5_reloc */ | |
372 | bl cache_post_test5_reloc | |
373 | cache_post_test5_reloc: | |
374 | mflr r9 | |
375 | ||
376 | /* Copy the test instruction to cache_post_test5_data */ | |
377 | lis r3, (cache_post_test5_1 - cache_post_test5_reloc)@h | |
378 | ori r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l | |
379 | add r3, r3, r9 | |
380 | lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h | |
381 | ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l | |
382 | add r4, r4, r9 | |
383 | lwz r0, 0(r3) | |
384 | stw r0, 0(r4) | |
385 | ||
386 | bl cache_post_iinvalidate | |
387 | ||
388 | /* Lock the branch instruction */ | |
389 | lis r3, (cache_post_test5_data - cache_post_test5_reloc)@h | |
390 | ori r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l | |
391 | add r3, r3, r9 | |
392 | bl cache_post_ilock | |
393 | ||
394 | /* Replace the test instruction */ | |
395 | lis r3, (cache_post_test5_2 - cache_post_test5_reloc)@h | |
396 | ori r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l | |
397 | add r3, r3, r9 | |
398 | lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h | |
399 | ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l | |
400 | add r4, r4, r9 | |
401 | lwz r0, 0(r3) | |
402 | stw r0, 0(r4) | |
403 | ||
404 | bl cache_post_iinvalidate | |
405 | ||
406 | /* Execute to the test instruction */ | |
407 | cache_post_test5_data: | |
408 | nop | |
409 | ||
410 | bl cache_post_iunlock | |
411 | ||
412 | lwz r0, 4(r1) | |
413 | mtlr r0 | |
414 | blr | |
415 | ||
416 | cache_post_test6_1: | |
417 | li r3, -1 | |
418 | cache_post_test6_2: | |
419 | li r3, 0 | |
420 | ||
421 | /* | |
422 | * turn on the instruction cache | |
423 | * unlock the entire instruction cache | |
424 | * invalidate the instruction cache | |
425 | * lock a branch instruction in the instruction cache | |
426 | * replace the branch instruction with "nop" | |
427 | * jump to the branch instruction | |
428 | * check that the branch instruction was executed | |
429 | */ | |
430 | .global cache_post_test6 | |
431 | cache_post_test6: | |
432 | mflr r0 | |
433 | stw r0, 4(r1) | |
434 | ||
435 | bl cache_post_ienable | |
436 | bl cache_post_iunlock | |
437 | bl cache_post_iinvalidate | |
438 | ||
439 | /* Compute r9 = cache_post_test6_reloc */ | |
440 | bl cache_post_test6_reloc | |
441 | cache_post_test6_reloc: | |
442 | mflr r9 | |
443 | ||
444 | /* Copy the test instruction to cache_post_test6_data */ | |
445 | lis r3, (cache_post_test6_1 - cache_post_test6_reloc)@h | |
446 | ori r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l | |
447 | add r3, r3, r9 | |
448 | lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h | |
449 | ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l | |
450 | add r4, r4, r9 | |
451 | lwz r0, 0(r3) | |
452 | stw r0, 0(r4) | |
453 | ||
454 | bl cache_post_iinvalidate | |
455 | ||
456 | /* Replace the test instruction */ | |
457 | lis r3, (cache_post_test6_2 - cache_post_test6_reloc)@h | |
458 | ori r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l | |
459 | add r3, r3, r9 | |
460 | lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h | |
461 | ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l | |
462 | add r4, r4, r9 | |
463 | lwz r0, 0(r3) | |
464 | stw r0, 0(r4) | |
465 | ||
466 | bl cache_post_iinvalidate | |
467 | ||
468 | /* Execute to the test instruction */ | |
469 | cache_post_test6_data: | |
470 | nop | |
471 | ||
472 | lwz r0, 4(r1) | |
473 | mtlr r0 | |
474 | blr | |
475 | ||
476 | #endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */ | |
6d0f6bcf | 477 | #endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */ |