[people/ms/u-boot.git] / post / cpu / ppc4xx / ether.c

/*
 * (C) Copyright 2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Author: Igor Lisitsin <igor@emcraft.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

/*
 * Ethernet test
 *
 * The Ethernet Media Access Controllers (EMAC) are tested in the
 * internal loopback mode.
 * The controllers are configured accordingly and several packets
 * are transmitted. The configurable test parameters are:
 *   MIN_PACKET_LENGTH - minimum size of packet to transmit
 *   MAX_PACKET_LENGTH - maximum size of packet to transmit
 *   CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
 *     is tested with a different frame length. Starting with
 *     MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
 *     Defaults to 10 and can be overridden in the board config header.
 */

#include <post.h>

#if CONFIG_POST & CONFIG_SYS_POST_ETHER

#include <asm/cache.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/ppc4xx-mal.h>
#include <asm/ppc4xx-emac.h>
#include <malloc.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Get count of EMAC devices (doesn't have to be the max. possible number
 * supported by the cpu)
 *
 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
 * 405EX/405EXr eval board, using the same binary.
 */
#if defined(CONFIG_BOARD_EMAC_COUNT)
#define LAST_EMAC_NUM	board_emac_count()
#else /* CONFIG_BOARD_EMAC_COUNT */
#if defined(CONFIG_HAS_ETH3)
#define LAST_EMAC_NUM	4
#elif defined(CONFIG_HAS_ETH2)
#define LAST_EMAC_NUM	3
#elif defined(CONFIG_HAS_ETH1)
#define LAST_EMAC_NUM	2
#else
#define LAST_EMAC_NUM	1
#endif
#endif /* CONFIG_BOARD_EMAC_COUNT */

#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_MFR_ETH_CLK_SEL_V(n)	((0x01<<27) / (n+1))
#endif

#define MIN_PACKET_LENGTH	64
#define MAX_PACKET_LENGTH	1514
#ifndef CONFIG_SYS_POST_ETH_LOOPS
#define CONFIG_SYS_POST_ETH_LOOPS	10
#endif
#define PACKET_INCR	((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
			 CONFIG_SYS_POST_ETH_LOOPS)

static volatile mal_desc_t tx __cacheline_aligned;
static volatile mal_desc_t rx __cacheline_aligned;
static char *tx_buf;
static char *rx_buf;

int board_emac_count(void);

static void ether_post_init (int devnum, int hw_addr)
{
	int i;
#if defined(CONFIG_440GX) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
	unsigned mode_reg;
	sys_info_t sysinfo;
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
	unsigned long mfr;
#endif

#if defined(CONFIG_440GX) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
	/* Need to get the OPB frequency so we can access the PHY */
	get_sys_info (&sysinfo);
#endif

#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
	/* provide clocks for EMAC internal loopback  */
	mfsdr (SDR0_MFR, mfr);
	mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
	mtsdr (SDR0_MFR, mfr);
	sync ();
#endif
	/* reset emac */
	out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
	sync ();

	for (i = 0;; i++) {
		if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST))
			break;
		if (i >= 1000) {
			printf ("Timeout resetting EMAC\n");
			break;
		}
		udelay (1000);
	}
#if defined(CONFIG_440GX) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
	/* Whack the M1 register */
	mode_reg = 0x0;
	if (sysinfo.freqOPB <= 50000000);
	else if (sysinfo.freqOPB <= 66666667)
		mode_reg |= EMAC_MR1_OBCI_66;
	else if (sysinfo.freqOPB <= 83333333)
		mode_reg |= EMAC_MR1_OBCI_83;
	else if (sysinfo.freqOPB <= 100000000)
		mode_reg |= EMAC_MR1_OBCI_100;
	else
		mode_reg |= EMAC_MR1_OBCI_GT100;

	out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg);

#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */

	/* set the Mal configuration reg */
#if defined(CONFIG_440GX) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
	mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
	       MAL_CR_PLBLT_DEFAULT | 0x00330000);
#else
	mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
	if (get_pvr() == PVR_440GP_RB) {
		mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
	}
#endif
	/* setup buffer descriptors */
	tx.ctrl = MAL_TX_CTRL_WRAP;
	tx.data_len = 0;
	tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);

	rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
	rx.data_len = 0;
	rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
	flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
	flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));

	switch (devnum) {
	case 1:
		/* setup MAL tx & rx channel pointers */
#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
		mtdcr (MAL0_TXCTP2R, &tx);
#else
		mtdcr (MAL0_TXCTP1R, &tx);
#endif
#if defined(CONFIG_440)
		mtdcr (MAL0_TXBADDR, 0x0);
		mtdcr (MAL0_RXBADDR, 0x0);
#endif
		mtdcr (MAL0_RXCTP1R, &rx);
		/* set RX buffer size */
		mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16);
		break;
	case 0:
	default:
		/* setup MAL tx & rx channel pointers */
#if defined(CONFIG_440)
		mtdcr (MAL0_TXBADDR, 0x0);
		mtdcr (MAL0_RXBADDR, 0x0);
#endif
		mtdcr (MAL0_TXCTP0R, &tx);
		mtdcr (MAL0_RXCTP0R, &rx);
		/* set RX buffer size */
		mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16);
		break;
	}

	/* Enable MAL transmit and receive channels */
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
	mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2)));
#else
	mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum));
#endif
	mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum));

	/* set internal loopback mode */
#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
	out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 |
		  EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
		  EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
		  in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
#else
	out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE |
		  EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
		  EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
		  in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
#endif

	/* set transmit enable & receive enable */
	out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE);

	/* enable broadcast address */
	out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE);

	/* set transmit request threshold register */
	out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000);	/* 256 byte threshold */

	/* set receive	low/high water mark register */
#if defined(CONFIG_440)
	/* 440s has a 64 byte burst length */
	out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000);
#else
	/* 405s have a 16 byte burst length */
	out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
#endif /* defined(CONFIG_440) */
	out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000);

	/* Set fifo limit entry in tx mode 0 */
	out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003);
	/* Frame gap set */
	out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008);
	sync ();
}

static void ether_post_halt (int devnum, int hw_addr)
{
	int i = 0;
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
	unsigned long mfr;
#endif

	/* 1st reset MAL channel */
	/* Note: writing a 0 to a channel has no effect */
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
	mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2));
#else
	mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum);
#endif
	mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum);

	/* wait for reset */
	while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) {
		if (i++ >= 1000)
			break;
		udelay (1000);
	}
	/* emac reset */
	out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);

#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
	/* remove clocks for EMAC internal loopback  */
	mfsdr (SDR0_MFR, mfr);
	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
	mtsdr (SDR0_MFR, mfr);
#endif
}

static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
{
	int i = 0;

	while (tx.ctrl & MAL_TX_CTRL_READY) {
		if (i++ > 100) {
			printf ("TX timeout\n");
			return;
		}
		udelay (1000);
		invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
	}
	tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
		EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
	tx.data_len = length;
	memcpy (tx.data_ptr, packet, length);
	flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
	flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
	sync ();

	out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0);
	sync ();
}

static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
{
	int length;
	int i = 0;

	while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
		if (i++ > 100) {
			printf ("RX timeout\n");
			return 0;
		}
		udelay (1000);
		invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
	}
	length = rx.data_len - 4;
	if (length <= max_length) {
		invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
		memcpy(packet, rx.data_ptr, length);
	}
	sync ();

	rx.ctrl |= MAL_RX_CTRL_EMPTY;
	flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
	sync ();

	return length;
}

  /*
   * Test routines
   */

static void packet_fill (char *packet, int length)
{
	char c = (char) length;
	int i;

	/* set up ethernet header */
	memset (packet, 0xff, 14);

	for (i = 14; i < length; i++) {
		packet[i] = c++;
	}
}

static int packet_check (char *packet, int length)
{
	char c = (char) length;
	int i;

	for (i = 14; i < length; i++) {
		if (packet[i] != c++)
			return -1;
	}

	return 0;
}

	char packet_send[MAX_PACKET_LENGTH];
	char packet_recv[MAX_PACKET_LENGTH];
static int test_ctlr (int devnum, int hw_addr)
{
	int res = -1;
	int length;
	int l;

	ether_post_init (devnum, hw_addr);

	for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH;
	     l -= PACKET_INCR) {
		packet_fill (packet_send, l);

		ether_post_send (devnum, hw_addr, packet_send, l);

		length = ether_post_recv (devnum, hw_addr, packet_recv,
					  sizeof (packet_recv));

		if (length != l || packet_check (packet_recv, length) < 0) {
			goto Done;
		}
	}

	res = 0;

Done:

	ether_post_halt (devnum, hw_addr);

	if (res != 0) {
		post_log ("EMAC%d test failed\n", devnum);
	}

	return res;
}

int ether_post_test (int flags)
{
	int res = 0;
	int i;

	/* Allocate tx & rx packet buffers */
	tx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
	rx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);

	if (!tx_buf || !rx_buf) {
		printf ("Failed to allocate packet buffers\n");
		res = -1;
		goto out_free;
	}

	for (i = 0; i < LAST_EMAC_NUM; i++) {
		if (test_ctlr (i, i*0x100))
			res = -1;
	}

out_free:
	free (tx_buf);
	free (rx_buf);

	return res;
}

#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */
Commit	Line	Data
b4489621 SP	1	/*
	2	* (C) Copyright 2007
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* Author: Igor Lisitsin <igor@emcraft.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
b4489621 SP	8	*/
	9
	10	#include <common.h>
	11
	12	/*
	13	* Ethernet test
	14	*
	15	* The Ethernet Media Access Controllers (EMAC) are tested in the
	16	* internal loopback mode.
	17	* The controllers are configured accordingly and several packets
	18	* are transmitted. The configurable test parameters are:
	19	* MIN_PACKET_LENGTH - minimum size of packet to transmit
	20	* MAX_PACKET_LENGTH - maximum size of packet to transmit
ac69243d SR	21	* CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
	22	* is tested with a different frame length. Starting with
	23	* MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
62a3b7dd	24	* Defaults to 10 and can be overridden in the board config header.
b4489621 SP	25	*/
b4489621 SP	26
b4489621 SP	27	#include <post.h>
b4489621 SP	28
6d0f6bcf	29	#if CONFIG_POST & CONFIG_SYS_POST_ETHER
b4489621 SP	30
	31	#include <asm/cache.h>
	32	#include <asm/io.h>
	33	#include <asm/processor.h>
b36df561 SR	34	#include <asm/ppc4xx-mal.h>
b36df561 SR	35	#include <asm/ppc4xx-emac.h>
b4489621 SP	36	#include <malloc.h>
	37
	38	DECLARE_GLOBAL_DATA_PTR;
	39
7d47cee2 SR	40	/*
	41	* Get count of EMAC devices (doesn't have to be the max. possible number
	42	* supported by the cpu)
	43	*
	44	* CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
	45	* EMAC count is possible. As it is needed for the Kilauea/Haleakala
	46	* 405EX/405EXr eval board, using the same binary.
	47	*/
	48	#if defined(CONFIG_BOARD_EMAC_COUNT)
	49	#define LAST_EMAC_NUM board_emac_count()
	50	#else /* CONFIG_BOARD_EMAC_COUNT */
	51	#if defined(CONFIG_HAS_ETH3)
	52	#define LAST_EMAC_NUM 4
	53	#elif defined(CONFIG_HAS_ETH2)
	54	#define LAST_EMAC_NUM 3
	55	#elif defined(CONFIG_HAS_ETH1)
	56	#define LAST_EMAC_NUM 2
	57	#else
	58	#define LAST_EMAC_NUM 1
	59	#endif
	60	#endif /* CONFIG_BOARD_EMAC_COUNT */
	61
b4489621 SP	62	#if defined(CONFIG_440SPE) \|\| defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
	63	#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
	64	#endif
	65
	66	#define MIN_PACKET_LENGTH 64
ac69243d SR	67	#define MAX_PACKET_LENGTH 1514
	68	#ifndef CONFIG_SYS_POST_ETH_LOOPS
	69	#define CONFIG_SYS_POST_ETH_LOOPS 10
	70	#endif
	71	#define PACKET_INCR ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
	72	CONFIG_SYS_POST_ETH_LOOPS)
b4489621 SP	73
	74	static volatile mal_desc_t tx __cacheline_aligned;
	75	static volatile mal_desc_t rx __cacheline_aligned;
	76	static char *tx_buf;
	77	static char *rx_buf;
	78
7d47cee2 SR	79	int board_emac_count(void);
7d47cee2 SR	80
b4489621 SP	81	static void ether_post_init (int devnum, int hw_addr)
	82	{
	83	int i;
b4489621 SP	84	#if defined(CONFIG_440GX) \|\| \
	85	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
	86	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
c5a172a5	87	unsigned mode_reg;
b4489621 SP	88	sys_info_t sysinfo;
	89	#endif
	90	#if defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| defined(CONFIG_440SPE)
	91	unsigned long mfr;
	92	#endif
	93
	94	#if defined(CONFIG_440GX) \|\| \
	95	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
	96	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
	97	/* Need to get the OPB frequency so we can access the PHY */
	98	get_sys_info (&sysinfo);
	99	#endif
	100
	101	#if defined(CONFIG_440SPE) \|\| defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
	102	/* provide clocks for EMAC internal loopback */
d1c3b275	103	mfsdr (SDR0_MFR, mfr);
b4489621	104	mfr \|= SDR0_MFR_ETH_CLK_SEL_V(devnum);
d1c3b275	105	mtsdr (SDR0_MFR, mfr);
b4489621 SP	106	sync ();
	107	#endif
	108	/* reset emac */
ddc922ff	109	out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
b4489621 SP	110	sync ();
	111
	112	for (i = 0;; i++) {
ddc922ff	113	if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST))
b4489621 SP	114	break;
	115	if (i >= 1000) {
	116	printf ("Timeout resetting EMAC\n");
	117	break;
	118	}
	119	udelay (1000);
	120	}
	121	#if defined(CONFIG_440GX) \|\| \
	122	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
	123	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
	124	/* Whack the M1 register */
	125	mode_reg = 0x0;
	126	if (sysinfo.freqOPB <= 50000000);
	127	else if (sysinfo.freqOPB <= 66666667)
ddc922ff	128	mode_reg \|= EMAC_MR1_OBCI_66;
b4489621	129	else if (sysinfo.freqOPB <= 83333333)
ddc922ff	130	mode_reg \|= EMAC_MR1_OBCI_83;
b4489621	131	else if (sysinfo.freqOPB <= 100000000)
ddc922ff	132	mode_reg \|= EMAC_MR1_OBCI_100;
b4489621	133	else
ddc922ff	134	mode_reg \|= EMAC_MR1_OBCI_GT100;
b4489621	135
ddc922ff	136	out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg);
b4489621 SP	137
	138	#endif /* defined(CONFIG_440GX) \|\| defined(CONFIG_440SP) */
	139
	140	/* set the Mal configuration reg */
	141	#if defined(CONFIG_440GX) \|\| \
	142	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
	143	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
d1c3b275	144	mtdcr (MAL0_CFG, MAL_CR_PLBB \| MAL_CR_OPBBL \| MAL_CR_LEA \|
b4489621 SP	145	MAL_CR_PLBLT_DEFAULT \| 0x00330000);
b4489621 SP	146	#else
d1c3b275	147	mtdcr (MAL0_CFG, MAL_CR_PLBB \| MAL_CR_OPBBL \| MAL_CR_LEA \| MAL_CR_PLBLT_DEFAULT);
b4489621 SP	148	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
b4489621 SP	149	if (get_pvr() == PVR_440GP_RB) {
d1c3b275	150	mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
b4489621 SP	151	}
	152	#endif
	153	/* setup buffer descriptors */
	154	tx.ctrl = MAL_TX_CTRL_WRAP;
	155	tx.data_len = 0;
	156	tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
	157
	158	rx.ctrl = MAL_TX_CTRL_WRAP \| MAL_RX_CTRL_EMPTY;
	159	rx.data_len = 0;
	160	rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
f71b2888 SR	161	flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
f71b2888 SR	162	flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
b4489621 SP	163
	164	switch (devnum) {
	165	case 1:
	166	/* setup MAL tx & rx channel pointers */
	167	#if defined (CONFIG_405EP) \|\| defined (CONFIG_440EP) \|\| defined (CONFIG_440GR)
d1c3b275	168	mtdcr (MAL0_TXCTP2R, &tx);
b4489621	169	#else
d1c3b275	170	mtdcr (MAL0_TXCTP1R, &tx);
b4489621 SP	171	#endif
b4489621 SP	172	#if defined(CONFIG_440)
d1c3b275 SR	173	mtdcr (MAL0_TXBADDR, 0x0);
d1c3b275 SR	174	mtdcr (MAL0_RXBADDR, 0x0);
b4489621	175	#endif
d1c3b275	176	mtdcr (MAL0_RXCTP1R, &rx);
b4489621	177	/* set RX buffer size */
d1c3b275	178	mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16);
b4489621 SP	179	break;
	180	case 0:
	181	default:
	182	/* setup MAL tx & rx channel pointers */
	183	#if defined(CONFIG_440)
d1c3b275 SR	184	mtdcr (MAL0_TXBADDR, 0x0);
d1c3b275 SR	185	mtdcr (MAL0_RXBADDR, 0x0);
b4489621	186	#endif
d1c3b275 SR	187	mtdcr (MAL0_TXCTP0R, &tx);
d1c3b275 SR	188	mtdcr (MAL0_RXCTP0R, &rx);
b4489621	189	/* set RX buffer size */
d1c3b275	190	mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16);
b4489621 SP	191	break;
	192	}
	193
	194	/* Enable MAL transmit and receive channels */
	195	#if defined(CONFIG_405EP) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
d1c3b275	196	mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2)));
b4489621	197	#else
d1c3b275	198	mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum));
b4489621	199	#endif
d1c3b275	200	mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum));
b4489621 SP	201
b4489621 SP	202	/* set internal loopback mode */
6d0f6bcf	203	#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
ddc922ff NG	204	out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE \| 0 \|
	205	EMAC_MR1_RFS_4K \| EMAC_MR1_TX_FIFO_2K \|
	206	EMAC_MR1_MF_100MBPS \| EMAC_MR1_IST \|
	207	in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
c5a172a5	208	#else
ddc922ff NG	209	out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE \| EMAC_MR1_ILE \|
	210	EMAC_MR1_RFS_4K \| EMAC_MR1_TX_FIFO_2K \|
	211	EMAC_MR1_MF_100MBPS \| EMAC_MR1_IST \|
	212	in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
c5a172a5	213	#endif
b4489621 SP	214
b4489621 SP	215	/* set transmit enable & receive enable */
ddc922ff	216	out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE \| EMAC_MR0_RXE);
b4489621 SP	217
b4489621 SP	218	/* enable broadcast address */
ddc922ff	219	out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE);
b4489621 SP	220
b4489621 SP	221	/* set transmit request threshold register */
ddc922ff	222	out_be32 ((void)(EMAC0_TRTR + hw_addr), 0x18000000); / 256 byte threshold */
b4489621 SP	223
	224	/* set receive low/high water mark register */
	225	#if defined(CONFIG_440)
	226	/* 440s has a 64 byte burst length */
ddc922ff	227	out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000);
b4489621 SP	228	#else
b4489621 SP	229	/* 405s have a 16 byte burst length */
ddc922ff	230	out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
b4489621	231	#endif /* defined(CONFIG_440) */
ddc922ff	232	out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000);
b4489621 SP	233
b4489621 SP	234	/* Set fifo limit entry in tx mode 0 */
ddc922ff	235	out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003);
b4489621	236	/* Frame gap set */
ddc922ff	237	out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008);
b4489621 SP	238	sync ();
	239	}
	240
	241	static void ether_post_halt (int devnum, int hw_addr)
	242	{
	243	int i = 0;
	244	#if defined(CONFIG_440SPE) \|\| defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
	245	unsigned long mfr;
	246	#endif
	247
	248	/* 1st reset MAL channel */
	249	/* Note: writing a 0 to a channel has no effect */
	250	#if defined(CONFIG_405EP) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
d1c3b275	251	mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2));
b4489621	252	#else
d1c3b275	253	mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum);
b4489621	254	#endif
d1c3b275	255	mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum);
b4489621 SP	256
b4489621 SP	257	/* wait for reset */
d1c3b275	258	while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) {
b4489621 SP	259	if (i++ >= 1000)
	260	break;
	261	udelay (1000);
	262	}
	263	/* emac reset */
ddc922ff	264	out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
b4489621 SP	265
	266	#if defined(CONFIG_440SPE) \|\| defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
	267	/* remove clocks for EMAC internal loopback */
d1c3b275	268	mfsdr (SDR0_MFR, mfr);
b4489621	269	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
d1c3b275	270	mtsdr (SDR0_MFR, mfr);
b4489621 SP	271	#endif
	272	}
	273
	274	static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
	275	{
	276	int i = 0;
	277
	278	while (tx.ctrl & MAL_TX_CTRL_READY) {
	279	if (i++ > 100) {
	280	printf ("TX timeout\n");
	281	return;
	282	}
	283	udelay (1000);
f71b2888	284	invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
b4489621 SP	285	}
	286	tx.ctrl = MAL_TX_CTRL_READY \| MAL_TX_CTRL_WRAP \| MAL_TX_CTRL_LAST \|
	287	EMAC_TX_CTRL_GFCS \| EMAC_TX_CTRL_GP;
	288	tx.data_len = length;
	289	memcpy (tx.data_ptr, packet, length);
f71b2888 SR	290	flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
f71b2888 SR	291	flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
b4489621 SP	292	sync ();
b4489621 SP	293
ddc922ff	294	out_be32 ((void)(EMAC0_TMR0 + hw_addr), in_be32 ((void)(EMAC0_TMR0 + hw_addr)) \| EMAC_TMR0_GNP0);
b4489621 SP	295	sync ();
	296	}
	297
	298	static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
	299	{
	300	int length;
	301	int i = 0;
	302
	303	while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
	304	if (i++ > 100) {
	305	printf ("RX timeout\n");
	306	return 0;
	307	}
	308	udelay (1000);
f71b2888	309	invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
b4489621 SP	310	}
b4489621 SP	311	length = rx.data_len - 4;
f71b2888 SR	312	if (length <= max_length) {
f71b2888 SR	313	invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
b4489621	314	memcpy(packet, rx.data_ptr, length);
f71b2888	315	}
b4489621 SP	316	sync ();
	317
	318	rx.ctrl \|= MAL_RX_CTRL_EMPTY;
f71b2888	319	flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
b4489621 SP	320	sync ();
	321
	322	return length;
	323	}
	324
	325	/*
	326	* Test routines
	327	*/
	328
	329	static void packet_fill (char *packet, int length)
	330	{
	331	char c = (char) length;
	332	int i;
	333
	334	/* set up ethernet header */
	335	memset (packet, 0xff, 14);
	336
	337	for (i = 14; i < length; i++) {
	338	packet[i] = c++;
	339	}
	340	}
	341
	342	static int packet_check (char *packet, int length)
	343	{
	344	char c = (char) length;
	345	int i;
	346
	347	for (i = 14; i < length; i++) {
	348	if (packet[i] != c++)
	349	return -1;
	350	}
	351
	352	return 0;
	353	}
	354
ac69243d SR	355	char packet_send[MAX_PACKET_LENGTH];
ac69243d SR	356	char packet_recv[MAX_PACKET_LENGTH];
b4489621 SP	357	static int test_ctlr (int devnum, int hw_addr)
	358	{
	359	int res = -1;
b4489621	360	int length;
b4489621 SP	361	int l;
	362
	363	ether_post_init (devnum, hw_addr);
	364
ac69243d SR	365	for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH;
	366	l -= PACKET_INCR) {
	367	packet_fill (packet_send, l);
b4489621	368
ac69243d	369	ether_post_send (devnum, hw_addr, packet_send, l);
b4489621	370
ac69243d SR	371	length = ether_post_recv (devnum, hw_addr, packet_recv,
ac69243d SR	372	sizeof (packet_recv));
b4489621	373
ac69243d SR	374	if (length != l \|\| packet_check (packet_recv, length) < 0) {
ac69243d SR	375	goto Done;
b4489621 SP	376	}
	377	}
	378
	379	res = 0;
	380
	381	Done:
	382
	383	ether_post_halt (devnum, hw_addr);
	384
	385	if (res != 0) {
	386	post_log ("EMAC%d test failed\n", devnum);
	387	}
	388
	389	return res;
	390	}
	391
	392	int ether_post_test (int flags)
	393	{
	394	int res = 0;
7d47cee2	395	int i;
b4489621 SP	396
b4489621 SP	397	/* Allocate tx & rx packet buffers */
6d0f6bcf JCPV	398	tx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
6d0f6bcf JCPV	399	rx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
b4489621 SP	400
	401	if (!tx_buf \|\| !rx_buf) {
	402	printf ("Failed to allocate packet buffers\n");
	403	res = -1;
	404	goto out_free;
	405	}
	406
7d47cee2 SR	407	for (i = 0; i < LAST_EMAC_NUM; i++) {
	408	if (test_ctlr (i, i*0x100))
	409	res = -1;
	410	}
b4489621 SP	411
	412	out_free:
	413	free (tx_buf);
	414	free (rx_buf);
	415
	416	return res;
	417	}
	418
6d0f6bcf	419	#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */