[people/ms/u-boot.git] / post / cpu / ppc4xx / spr.c

/*
 * (C) Copyright 2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Author: Igor Lisitsin <igor@emcraft.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

/*
 * SPR test
 *
 * The test checks the contents of Special Purpose Registers (SPR) listed
 * in the spr_test_list array below.
 * Each SPR value is read using mfspr instruction, some bits are masked
 * according to the table and the resulting value is compared to the
 * corresponding table value.
 */

#include <post.h>

#if CONFIG_POST & CONFIG_SYS_POST_SPR

#include <asm/processor.h>

#ifdef CONFIG_4xx_DCACHE
#include <asm/mmu.h>

DECLARE_GLOBAL_DATA_PTR;
#endif

static struct {
	int number;
	char * name;
	unsigned long mask;
	unsigned long value;
} spr_test_list [] = {
	/* Standard Special-Purpose Registers */

	{0x001,	"XER",		0x00000000,	0x00000000},
	{0x008,	"LR",		0x00000000,	0x00000000},
	{0x009,	"CTR",		0x00000000,	0x00000000},
	{0x016,	"DEC",		0x00000000,	0x00000000},
	{0x01a,	"SRR0",		0x00000000,	0x00000000},
	{0x01b,	"SRR1",		0x00000000,	0x00000000},
	{0x110,	"SPRG0",	0x00000000,	0x00000000},
	{0x111,	"SPRG1",	0x00000000,	0x00000000},
	{0x112,	"SPRG2",	0x00000000,	0x00000000},
	{0x113,	"SPRG3",	0x00000000,	0x00000000},
	{0x11f,	"PVR",		0x00000000,	0x00000000},

	/* Additional Special-Purpose Registers.
	 * The values must match the initialization
	 * values from arch/powerpc/cpu/ppc4xx/start.S
	 */
	{0x30,	"PID",		0x00000000,	0x00000000},
	{0x3a,	"CSRR0",	0x00000000,	0x00000000},
	{0x3b,	"CSRR1",	0x00000000,	0x00000000},
	{0x3d,	"DEAR",		0x00000000,	0x00000000},
	{0x3e,	"ESR",		0x00000000,	0x00000000},
#ifdef CONFIG_440
	{0x3f,	"IVPR",		0xffff0000,	0x00000000},
#endif
	{0x100,	"USPRG0",	0x00000000,	0x00000000},
	{0x104,	"SPRG4",	0x00000000,	0x00000000},
	{0x105,	"SPRG5",	0x00000000,	0x00000000},
	{0x106,	"SPRG6",	0x00000000,	0x00000000},
	{0x107,	"SPRG7",	0x00000000,	0x00000000},
	{0x10c,	"TBL",		0x00000000,	0x00000000},
	{0x10d,	"TBU",		0x00000000,	0x00000000},
#ifdef CONFIG_440
	{0x11e,	"PIR",		0x0000000f,	0x00000000},
#endif
	{0x130,	"DBSR",		0x00000000,	0x00000000},
	{0x134,	"DBCR0",	0x00000000,	0x00000000},
	{0x135,	"DBCR1",	0x00000000,	0x00000000},
	{0x136,	"DBCR2",	0x00000000,	0x00000000},
	{0x138,	"IAC1",		0x00000000,	0x00000000},
	{0x139,	"IAC2",		0x00000000,	0x00000000},
	{0x13a,	"IAC3",		0x00000000,	0x00000000},
	{0x13b,	"IAC4",		0x00000000,	0x00000000},
	{0x13c,	"DAC1",		0x00000000,	0x00000000},
	{0x13d,	"DAC2",		0x00000000,	0x00000000},
	{0x13e,	"DVC1",		0x00000000,	0x00000000},
	{0x13f,	"DVC2",		0x00000000,	0x00000000},
	{0x150,	"TSR",		0x00000000,	0x00000000},
	{0x154,	"TCR",		0x00000000,	0x00000000},
#ifdef CONFIG_440
	{0x190,	"IVOR0",	0x0000fff0,	0x00000100},
	{0x191,	"IVOR1",	0x0000fff0,	0x00000200},
	{0x192,	"IVOR2",	0x0000fff0,	0x00000300},
	{0x193,	"IVOR3",	0x0000fff0,	0x00000400},
	{0x194,	"IVOR4",	0x0000fff0,	0x00000500},
	{0x195,	"IVOR5",	0x0000fff0,	0x00000600},
	{0x196,	"IVOR6",	0x0000fff0,	0x00000700},
	{0x197,	"IVOR7",	0x0000fff0,	0x00000800},
	{0x198,	"IVOR8",	0x0000fff0,	0x00000c00},
	{0x199,	"IVOR9",	0x00000000,	0x00000000},
	{0x19a,	"IVOR10",	0x0000fff0,	0x00000900},
	{0x19b,	"IVOR11",	0x00000000,	0x00000000},
	{0x19c,	"IVOR12",	0x00000000,	0x00000000},
	{0x19d,	"IVOR13",	0x0000fff0,	0x00001300},
	{0x19e,	"IVOR14",	0x0000fff0,	0x00001400},
	{0x19f,	"IVOR15",	0x0000fff0,	0x00002000},
#endif
	{0x23a,	"MCSRR0",	0x00000000,	0x00000000},
	{0x23b,	"MCSRR1",	0x00000000,	0x00000000},
	{0x23c,	"MCSR",		0x00000000,	0x00000000},
	{0x370,	"INV0",		0x00000000,	0x00000000},
	{0x371,	"INV1",		0x00000000,	0x00000000},
	{0x372,	"INV2",		0x00000000,	0x00000000},
	{0x373,	"INV3",		0x00000000,	0x00000000},
	{0x374,	"ITV0",		0x00000000,	0x00000000},
	{0x375,	"ITV1",		0x00000000,	0x00000000},
	{0x376,	"ITV2",		0x00000000,	0x00000000},
	{0x377,	"ITV3",		0x00000000,	0x00000000},
	{0x378,	"CCR1",		0x00000000,	0x00000000},
	{0x390,	"DNV0",		0x00000000,	0x00000000},
	{0x391,	"DNV1",		0x00000000,	0x00000000},
	{0x392,	"DNV2",		0x00000000,	0x00000000},
	{0x393,	"DNV3",		0x00000000,	0x00000000},
	{0x394,	"DTV0",		0x00000000,	0x00000000},
	{0x395,	"DTV1",		0x00000000,	0x00000000},
	{0x396,	"DTV2",		0x00000000,	0x00000000},
	{0x397,	"DTV3",		0x00000000,	0x00000000},
#ifdef CONFIG_440
	{0x398,	"DVLIM",	0x0fc1f83f,	0x0001f800},
	{0x399,	"IVLIM",	0x0fc1f83f,	0x0001f800},
#endif
	{0x39b,	"RSTCFG",	0x00000000,	0x00000000},
	{0x39c,	"DCDBTRL",	0x00000000,	0x00000000},
	{0x39d,	"DCDBTRH",	0x00000000,	0x00000000},
	{0x39e,	"ICDBTRL",	0x00000000,	0x00000000},
	{0x39f,	"ICDBTRH",	0x00000000,	0x00000000},
	{0x3b2,	"MMUCR",	0x00000000,	0x00000000},
	{0x3b3,	"CCR0",		0x00000000,	0x00000000},
	{0x3d3,	"ICDBDR",	0x00000000,	0x00000000},
	{0x3f3,	"DBDR",		0x00000000,	0x00000000},
};

static int spr_test_list_size = ARRAY_SIZE(spr_test_list);

int spr_post_test (int flags)
{
	int ret = 0;
	int i;

	unsigned long code[] = {
		0x7c6002a6,				/* mfspr r3,SPR */
		0x4e800020				/* blr          */
	};
	unsigned long (*get_spr) (void) = (void *) code;

#ifdef CONFIG_4xx_DCACHE
	/* disable cache */
	change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
#endif
	for (i = 0; i < spr_test_list_size; i++) {
		int num = spr_test_list[i].number;

		/* mfspr r3,num */
		code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);

		asm volatile ("isync");

		if ((get_spr () & spr_test_list[i].mask) !=
			(spr_test_list[i].value & spr_test_list[i].mask)) {
			post_log ("The value of %s special register "
				  "is incorrect: 0x%08X\n",
					spr_test_list[i].name, get_spr ());
			ret = -1;
		}
	}
#ifdef CONFIG_4xx_DCACHE
	/* enable cache */
	change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
#endif

	return ret;
}

#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */
Commit	Line	Data
a11e0696 IL	1	/*
	2	* (C) Copyright 2007
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
b4489621 SP	5	* Author: Igor Lisitsin <igor@emcraft.com>
b4489621 SP	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
a11e0696 IL	8	*/
	9
	10	#include <common.h>
	11
	12	/*
	13	* SPR test
	14	*
	15	* The test checks the contents of Special Purpose Registers (SPR) listed
	16	* in the spr_test_list array below.
	17	* Each SPR value is read using mfspr instruction, some bits are masked
	18	* according to the table and the resulting value is compared to the
	19	* corresponding table value.
	20	*/
	21
a11e0696 IL	22	#include <post.h>
a11e0696 IL	23
6d0f6bcf	24	#if CONFIG_POST & CONFIG_SYS_POST_SPR
a11e0696	25
b4489621 SP	26	#include <asm/processor.h>
b4489621 SP	27
60ec654c AG	28	#ifdef CONFIG_4xx_DCACHE
	29	#include <asm/mmu.h>
	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32	#endif
	33
4ef218f6 WD	34	static struct {
	35	int number;
	36	char * name;
	37	unsigned long mask;
	38	unsigned long value;
a11e0696 IL	39	} spr_test_list [] = {
	40	/* Standard Special-Purpose Registers */
	41
	42	{0x001, "XER", 0x00000000, 0x00000000},
	43	{0x008, "LR", 0x00000000, 0x00000000},
	44	{0x009, "CTR", 0x00000000, 0x00000000},
	45	{0x016, "DEC", 0x00000000, 0x00000000},
	46	{0x01a, "SRR0", 0x00000000, 0x00000000},
	47	{0x01b, "SRR1", 0x00000000, 0x00000000},
	48	{0x110, "SPRG0", 0x00000000, 0x00000000},
	49	{0x111, "SPRG1", 0x00000000, 0x00000000},
	50	{0x112, "SPRG2", 0x00000000, 0x00000000},
	51	{0x113, "SPRG3", 0x00000000, 0x00000000},
	52	{0x11f, "PVR", 0x00000000, 0x00000000},
	53
b4489621	54	/* Additional Special-Purpose Registers.
4ef218f6	55	* The values must match the initialization
a47a12be	56	* values from arch/powerpc/cpu/ppc4xx/start.S
b4489621	57	*/
a11e0696 IL	58	{0x30, "PID", 0x00000000, 0x00000000},
	59	{0x3a, "CSRR0", 0x00000000, 0x00000000},
	60	{0x3b, "CSRR1", 0x00000000, 0x00000000},
	61	{0x3d, "DEAR", 0x00000000, 0x00000000},
	62	{0x3e, "ESR", 0x00000000, 0x00000000},
f2302d44	63	#ifdef CONFIG_440
a11e0696	64	{0x3f, "IVPR", 0xffff0000, 0x00000000},
f2302d44	65	#endif
a11e0696 IL	66	{0x100, "USPRG0", 0x00000000, 0x00000000},
	67	{0x104, "SPRG4", 0x00000000, 0x00000000},
	68	{0x105, "SPRG5", 0x00000000, 0x00000000},
	69	{0x106, "SPRG6", 0x00000000, 0x00000000},
	70	{0x107, "SPRG7", 0x00000000, 0x00000000},
	71	{0x10c, "TBL", 0x00000000, 0x00000000},
	72	{0x10d, "TBU", 0x00000000, 0x00000000},
17bef680	73	#ifdef CONFIG_440
a11e0696	74	{0x11e, "PIR", 0x0000000f, 0x00000000},
17bef680	75	#endif
a11e0696 IL	76	{0x130, "DBSR", 0x00000000, 0x00000000},
	77	{0x134, "DBCR0", 0x00000000, 0x00000000},
	78	{0x135, "DBCR1", 0x00000000, 0x00000000},
	79	{0x136, "DBCR2", 0x00000000, 0x00000000},
	80	{0x138, "IAC1", 0x00000000, 0x00000000},
	81	{0x139, "IAC2", 0x00000000, 0x00000000},
	82	{0x13a, "IAC3", 0x00000000, 0x00000000},
	83	{0x13b, "IAC4", 0x00000000, 0x00000000},
	84	{0x13c, "DAC1", 0x00000000, 0x00000000},
	85	{0x13d, "DAC2", 0x00000000, 0x00000000},
	86	{0x13e, "DVC1", 0x00000000, 0x00000000},
	87	{0x13f, "DVC2", 0x00000000, 0x00000000},
	88	{0x150, "TSR", 0x00000000, 0x00000000},
	89	{0x154, "TCR", 0x00000000, 0x00000000},
17bef680	90	#ifdef CONFIG_440
b4489621 SP	91	{0x190, "IVOR0", 0x0000fff0, 0x00000100},
	92	{0x191, "IVOR1", 0x0000fff0, 0x00000200},
	93	{0x192, "IVOR2", 0x0000fff0, 0x00000300},
	94	{0x193, "IVOR3", 0x0000fff0, 0x00000400},
	95	{0x194, "IVOR4", 0x0000fff0, 0x00000500},
	96	{0x195, "IVOR5", 0x0000fff0, 0x00000600},
	97	{0x196, "IVOR6", 0x0000fff0, 0x00000700},
	98	{0x197, "IVOR7", 0x0000fff0, 0x00000800},
	99	{0x198, "IVOR8", 0x0000fff0, 0x00000c00},
a11e0696	100	{0x199, "IVOR9", 0x00000000, 0x00000000},
b4489621	101	{0x19a, "IVOR10", 0x0000fff0, 0x00000900},
a11e0696 IL	102	{0x19b, "IVOR11", 0x00000000, 0x00000000},
a11e0696 IL	103	{0x19c, "IVOR12", 0x00000000, 0x00000000},
b4489621 SP	104	{0x19d, "IVOR13", 0x0000fff0, 0x00001300},
	105	{0x19e, "IVOR14", 0x0000fff0, 0x00001400},
	106	{0x19f, "IVOR15", 0x0000fff0, 0x00002000},
17bef680	107	#endif
a11e0696 IL	108	{0x23a, "MCSRR0", 0x00000000, 0x00000000},
	109	{0x23b, "MCSRR1", 0x00000000, 0x00000000},
	110	{0x23c, "MCSR", 0x00000000, 0x00000000},
	111	{0x370, "INV0", 0x00000000, 0x00000000},
	112	{0x371, "INV1", 0x00000000, 0x00000000},
	113	{0x372, "INV2", 0x00000000, 0x00000000},
	114	{0x373, "INV3", 0x00000000, 0x00000000},
	115	{0x374, "ITV0", 0x00000000, 0x00000000},
	116	{0x375, "ITV1", 0x00000000, 0x00000000},
	117	{0x376, "ITV2", 0x00000000, 0x00000000},
	118	{0x377, "ITV3", 0x00000000, 0x00000000},
	119	{0x378, "CCR1", 0x00000000, 0x00000000},
	120	{0x390, "DNV0", 0x00000000, 0x00000000},
	121	{0x391, "DNV1", 0x00000000, 0x00000000},
	122	{0x392, "DNV2", 0x00000000, 0x00000000},
	123	{0x393, "DNV3", 0x00000000, 0x00000000},
	124	{0x394, "DTV0", 0x00000000, 0x00000000},
	125	{0x395, "DTV1", 0x00000000, 0x00000000},
	126	{0x396, "DTV2", 0x00000000, 0x00000000},
	127	{0x397, "DTV3", 0x00000000, 0x00000000},
17bef680	128	#ifdef CONFIG_440
b4489621 SP	129	{0x398, "DVLIM", 0x0fc1f83f, 0x0001f800},
b4489621 SP	130	{0x399, "IVLIM", 0x0fc1f83f, 0x0001f800},
17bef680	131	#endif
a11e0696 IL	132	{0x39b, "RSTCFG", 0x00000000, 0x00000000},
	133	{0x39c, "DCDBTRL", 0x00000000, 0x00000000},
	134	{0x39d, "DCDBTRH", 0x00000000, 0x00000000},
	135	{0x39e, "ICDBTRL", 0x00000000, 0x00000000},
	136	{0x39f, "ICDBTRH", 0x00000000, 0x00000000},
	137	{0x3b2, "MMUCR", 0x00000000, 0x00000000},
	138	{0x3b3, "CCR0", 0x00000000, 0x00000000},
	139	{0x3d3, "ICDBDR", 0x00000000, 0x00000000},
	140	{0x3f3, "DBDR", 0x00000000, 0x00000000},
	141	};
	142
d2397817	143	static int spr_test_list_size = ARRAY_SIZE(spr_test_list);
a11e0696 IL	144
	145	int spr_post_test (int flags)
	146	{
	147	int ret = 0;
	148	int i;
	149
	150	unsigned long code[] = {
	151	0x7c6002a6, /* mfspr r3,SPR */
	152	0x4e800020 /* blr */
	153	};
	154	unsigned long (get_spr) (void) = (void ) code;
	155
60ec654c AG	156	#ifdef CONFIG_4xx_DCACHE
	157	/* disable cache */
	158	change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
	159	#endif
a11e0696 IL	160	for (i = 0; i < spr_test_list_size; i++) {
	161	int num = spr_test_list[i].number;
	162
	163	/* mfspr r3,num */
	164	code[0] = 0x7c6002a6 \| ((num & 0x1F) << 16) \| ((num & 0x3E0) << 6);
	165
	166	asm volatile ("isync");
	167
	168	if ((get_spr () & spr_test_list[i].mask) !=
	169	(spr_test_list[i].value & spr_test_list[i].mask)) {
	170	post_log ("The value of %s special register "
	171	"is incorrect: 0x%08X\n",
	172	spr_test_list[i].name, get_spr ());
	173	ret = -1;
	174	}
	175	}
60ec654c AG	176	#ifdef CONFIG_4xx_DCACHE
	177	/* enable cache */
	178	change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
	179	#endif
a11e0696 IL	180
	181	return ret;
	182	}
b4489621	183
6d0f6bcf	184	#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */