projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ad5bb451 WD |
1 | /* |
| 2 | * (C) Copyright 2002 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| ad5bb451 WD |
6 | */ |
| 7 | ||
| 8 | #include <common.h> | |
| 9 | ||
| 10 | /* | |
| 11 | * CPU test | |
| 12 | * | |
| 13 | * This test checks the arithmetic logic unit (ALU) of CPU. | |
| 14 | * It tests independently various groups of instructions using | |
| 15 | * run-time modification of the code to reduce the memory footprint. | |
| 16 | * For more details refer to post/cpu/ *.c files. | |
| 17 | */ | |
| 18 | ||
| ad5bb451 WD |
19 | #include <watchdog.h> |
| 20 | #include <post.h> | |
| 3db93b8b | 21 | #include <asm/mmu.h> |
| ad5bb451 | 22 | |
| 6d0f6bcf | 23 | #if CONFIG_POST & CONFIG_SYS_POST_CPU |
| ad5bb451 WD |
24 | |
| 25 | extern int cpu_post_test_cmp (void); | |
| 26 | extern int cpu_post_test_cmpi (void); | |
| 27 | extern int cpu_post_test_two (void); | |
| 28 | extern int cpu_post_test_twox (void); | |
| 29 | extern int cpu_post_test_three (void); | |
| 30 | extern int cpu_post_test_threex (void); | |
| 31 | extern int cpu_post_test_threei (void); | |
| 32 | extern int cpu_post_test_andi (void); | |
| 33 | extern int cpu_post_test_srawi (void); | |
| 34 | extern int cpu_post_test_rlwnm (void); | |
| 35 | extern int cpu_post_test_rlwinm (void); | |
| 36 | extern int cpu_post_test_rlwimi (void); | |
| 37 | extern int cpu_post_test_store (void); | |
| 38 | extern int cpu_post_test_load (void); | |
| 39 | extern int cpu_post_test_cr (void); | |
| 40 | extern int cpu_post_test_b (void); | |
| 41 | extern int cpu_post_test_multi (void); | |
| 42 | extern int cpu_post_test_string (void); | |
| 43 | extern int cpu_post_test_complex (void); | |
| 44 | ||
| 3db93b8b SR |
45 | DECLARE_GLOBAL_DATA_PTR; |
| 46 | ||
| ad5bb451 WD |
47 | ulong cpu_post_makecr (long v) |
| 48 | { | |
| 49 | ulong cr = 0; | |
| 50 | ||
| 51 | if (v < 0) | |
| 52 | cr |= 0x80000000; | |
| 53 | if (v > 0) | |
| 54 | cr |= 0x40000000; | |
| 55 | if (v == 0) | |
| 56 | cr |= 0x20000000; | |
| 57 | ||
| 58 | return cr; | |
| 59 | } | |
| 60 | ||
| 61 | int cpu_post_test (int flags) | |
| 62 | { | |
| 63 | int ic = icache_status (); | |
| 64 | int ret = 0; | |
| 65 | ||
| 66 | WATCHDOG_RESET(); | |
| 67 | if (ic) | |
| 68 | icache_disable (); | |
| 3db93b8b SR |
69 | #ifdef CONFIG_4xx_DCACHE |
| 70 | /* disable cache */ | |
| 71 | change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); | |
| 72 | #endif | |
| ad5bb451 WD |
73 | |
| 74 | if (ret == 0) | |
| 75 | ret = cpu_post_test_cmp (); | |
| 76 | if (ret == 0) | |
| 77 | ret = cpu_post_test_cmpi (); | |
| 78 | if (ret == 0) | |
| 79 | ret = cpu_post_test_two (); | |
| 80 | if (ret == 0) | |
| 81 | ret = cpu_post_test_twox (); | |
| 82 | WATCHDOG_RESET(); | |
| 83 | if (ret == 0) | |
| 84 | ret = cpu_post_test_three (); | |
| 85 | if (ret == 0) | |
| 86 | ret = cpu_post_test_threex (); | |
| 87 | if (ret == 0) | |
| 88 | ret = cpu_post_test_threei (); | |
| 89 | if (ret == 0) | |
| 90 | ret = cpu_post_test_andi (); | |
| 91 | WATCHDOG_RESET(); | |
| 92 | if (ret == 0) | |
| 93 | ret = cpu_post_test_srawi (); | |
| 94 | if (ret == 0) | |
| 95 | ret = cpu_post_test_rlwnm (); | |
| 96 | if (ret == 0) | |
| 97 | ret = cpu_post_test_rlwinm (); | |
| 98 | if (ret == 0) | |
| 99 | ret = cpu_post_test_rlwimi (); | |
| 100 | WATCHDOG_RESET(); | |
| 101 | if (ret == 0) | |
| 102 | ret = cpu_post_test_store (); | |
| 103 | if (ret == 0) | |
| 104 | ret = cpu_post_test_load (); | |
| 105 | if (ret == 0) | |
| 106 | ret = cpu_post_test_cr (); | |
| 107 | if (ret == 0) | |
| 108 | ret = cpu_post_test_b (); | |
| 109 | WATCHDOG_RESET(); | |
| 110 | if (ret == 0) | |
| 111 | ret = cpu_post_test_multi (); | |
| 112 | WATCHDOG_RESET(); | |
| 113 | if (ret == 0) | |
| 114 | ret = cpu_post_test_string (); | |
| 115 | if (ret == 0) | |
| 116 | ret = cpu_post_test_complex (); | |
| 117 | WATCHDOG_RESET(); | |
| 118 | ||
| 119 | if (ic) | |
| 120 | icache_enable (); | |
| 3db93b8b SR |
121 | #ifdef CONFIG_4xx_DCACHE |
| 122 | /* enable cache */ | |
| 123 | change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); | |
| 124 | #endif | |
| ad5bb451 WD |
125 | |
| 126 | WATCHDOG_RESET(); | |
| 127 | ||
| 128 | return ret; | |
| 129 | } | |
| 130 | ||
| 6d0f6bcf | 131 | #endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */ |