[people/ms/u-boot.git] / post / lib_powerpc / rlwinm.c

/*
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

/*
 * CPU test
 * Shift instructions:		rlwinm
 *
 * The test contains a pre-built table of instructions, operands and
 * expected results. For each table entry, the test will cyclically use
 * different sets of operand registers and result registers.
 */

#include <post.h>
#include "cpu_asm.h"

#if CONFIG_POST & CONFIG_SYS_POST_CPU

extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
extern ulong cpu_post_makecr (long v);

static struct cpu_post_rlwinm_s
{
    ulong cmd;
    ulong op1;
    uchar op2;
    uchar mb;
    uchar me;
    ulong res;
} cpu_post_rlwinm_table[] =
{
   {
	OP_RLWINM,
	0xffff0000,
	24,
	16,
	23,
	0x0000ff00
   },
};
static unsigned int cpu_post_rlwinm_size = ARRAY_SIZE(cpu_post_rlwinm_table);

int cpu_post_test_rlwinm (void)
{
    int ret = 0;
    unsigned int i, reg;
    int flag = disable_interrupts();

    for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++)
    {
	struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i;

	for (reg = 0; reg < 32 && ret == 0; reg++)
	{
	    unsigned int reg0 = (reg + 0) % 32;
	    unsigned int reg1 = (reg + 1) % 32;
	    unsigned int stk = reg < 16 ? 31 : 15;
	    unsigned long code[] =
	    {
		ASM_STW(stk, 1, -4),
		ASM_ADDI(stk, 1, -16),
		ASM_STW(3, stk, 8),
		ASM_STW(reg0, stk, 4),
		ASM_STW(reg1, stk, 0),
		ASM_LWZ(reg0, stk, 8),
		ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
		ASM_STW(reg1, stk, 8),
		ASM_LWZ(reg1, stk, 0),
		ASM_LWZ(reg0, stk, 4),
		ASM_LWZ(3, stk, 8),
		ASM_ADDI(1, stk, 16),
		ASM_LWZ(stk, 1, -4),
		ASM_BLR,
	    };
	    unsigned long codecr[] =
	    {
		ASM_STW(stk, 1, -4),
		ASM_ADDI(stk, 1, -16),
		ASM_STW(3, stk, 8),
		ASM_STW(reg0, stk, 4),
		ASM_STW(reg1, stk, 0),
		ASM_LWZ(reg0, stk, 8),
		ASM_113(test->cmd, reg1, reg0, test->op2, test->mb,
		    test->me) | BIT_C,
		ASM_STW(reg1, stk, 8),
		ASM_LWZ(reg1, stk, 0),
		ASM_LWZ(reg0, stk, 4),
		ASM_LWZ(3, stk, 8),
		ASM_ADDI(1, stk, 16),
		ASM_LWZ(stk, 1, -4),
		ASM_BLR,
	    };
	    ulong res;
	    ulong cr;

	    if (ret == 0)
	    {
		cr = 0;
		cpu_post_exec_21 (code, & cr, & res, test->op1);

		ret = res == test->res && cr == 0 ? 0 : -1;

		if (ret != 0)
		{
		    post_log ("Error at rlwinm test %d !\n", i);
		}
	    }

	    if (ret == 0)
	    {
		cpu_post_exec_21 (codecr, & cr, & res, test->op1);

		ret = res == test->res &&
		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;

		if (ret != 0)
		{
		    post_log ("Error at rlwinm test %d !\n", i);
		}
	    }
	}
    }

    if (flag)
	enable_interrupts();

    return ret;
}

#endif
Commit	Line	Data
ad5bb451 WD	1	/*
	2	* (C) Copyright 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
ad5bb451 WD	6	*/
	7
	8	#include <common.h>
	9
	10	/*
	11	* CPU test
	12	* Shift instructions: rlwinm
	13	*
	14	* The test contains a pre-built table of instructions, operands and
	15	* expected results. For each table entry, the test will cyclically use
	16	* different sets of operand registers and result registers.
	17	*/
	18
ad5bb451 WD	19	#include <post.h>
	20	#include "cpu_asm.h"
	21
6d0f6bcf	22	#if CONFIG_POST & CONFIG_SYS_POST_CPU
ad5bb451 WD	23
	24	extern void cpu_post_exec_21 (ulong code, ulong cr, ulong *res, ulong op1);
	25	extern ulong cpu_post_makecr (long v);
	26
	27	static struct cpu_post_rlwinm_s
	28	{
	29	ulong cmd;
	30	ulong op1;
	31	uchar op2;
	32	uchar mb;
	33	uchar me;
	34	ulong res;
	35	} cpu_post_rlwinm_table[] =
	36	{
	37	{
53677ef1	38	OP_RLWINM,
ad5bb451 WD	39	0xffff0000,
	40	24,
	41	16,
	42	23,
	43	0x0000ff00
	44	},
	45	};
d2397817	46	static unsigned int cpu_post_rlwinm_size = ARRAY_SIZE(cpu_post_rlwinm_table);
ad5bb451 WD	47
	48	int cpu_post_test_rlwinm (void)
	49	{
	50	int ret = 0;
	51	unsigned int i, reg;
	52	int flag = disable_interrupts();
	53
	54	for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++)
	55	{
	56	struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i;
	57
	58	for (reg = 0; reg < 32 && ret == 0; reg++)
	59	{
	60	unsigned int reg0 = (reg + 0) % 32;
	61	unsigned int reg1 = (reg + 1) % 32;
	62	unsigned int stk = reg < 16 ? 31 : 15;
53677ef1	63	unsigned long code[] =
ad5bb451 WD	64	{
	65	ASM_STW(stk, 1, -4),
	66	ASM_ADDI(stk, 1, -16),
	67	ASM_STW(3, stk, 8),
	68	ASM_STW(reg0, stk, 4),
	69	ASM_STW(reg1, stk, 0),
	70	ASM_LWZ(reg0, stk, 8),
	71	ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
	72	ASM_STW(reg1, stk, 8),
	73	ASM_LWZ(reg1, stk, 0),
	74	ASM_LWZ(reg0, stk, 4),
	75	ASM_LWZ(3, stk, 8),
	76	ASM_ADDI(1, stk, 16),
	77	ASM_LWZ(stk, 1, -4),
	78	ASM_BLR,
	79	};
53677ef1	80	unsigned long codecr[] =
ad5bb451 WD	81	{
	82	ASM_STW(stk, 1, -4),
	83	ASM_ADDI(stk, 1, -16),
	84	ASM_STW(3, stk, 8),
	85	ASM_STW(reg0, stk, 4),
	86	ASM_STW(reg1, stk, 0),
	87	ASM_LWZ(reg0, stk, 8),
	88	ASM_113(test->cmd, reg1, reg0, test->op2, test->mb,
	89	test->me) \| BIT_C,
	90	ASM_STW(reg1, stk, 8),
	91	ASM_LWZ(reg1, stk, 0),
	92	ASM_LWZ(reg0, stk, 4),
	93	ASM_LWZ(3, stk, 8),
	94	ASM_ADDI(1, stk, 16),
	95	ASM_LWZ(stk, 1, -4),
	96	ASM_BLR,
	97	};
	98	ulong res;
	99	ulong cr;
	100
	101	if (ret == 0)
	102	{
53677ef1 WD	103	cr = 0;
53677ef1 WD	104	cpu_post_exec_21 (code, & cr, & res, test->op1);
ad5bb451	105
53677ef1	106	ret = res == test->res && cr == 0 ? 0 : -1;
ad5bb451	107
53677ef1 WD	108	if (ret != 0)
53677ef1 WD	109	{
93e14596	110	post_log ("Error at rlwinm test %d !\n", i);
53677ef1	111	}
ad5bb451 WD	112	}
	113
	114	if (ret == 0)
	115	{
53677ef1	116	cpu_post_exec_21 (codecr, & cr, & res, test->op1);
ad5bb451	117
53677ef1	118	ret = res == test->res &&
ad5bb451 WD	119	(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
ad5bb451 WD	120
53677ef1 WD	121	if (ret != 0)
53677ef1 WD	122	{
93e14596 WD	123	post_log ("Error at rlwinm test %d !\n", i);
93e14596 WD	124	}
ad5bb451 WD	125	}
	126	}
	127	}
	128
	129	if (flag)
53677ef1	130	enable_interrupts();
ad5bb451 WD	131
	132	return ret;
	133	}
	134
	135	#endif