[people/ms/u-boot.git] / post / lib_powerpc / three.c

/*
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

/*
 * CPU test
 * Ternary instructions		instr rD,rA,rB
 *
 * Arithmetic instructions:	add, addc, adde, subf, subfc, subfe,
 *				mullw, mulhw, mulhwu, divw, divwu
 *
 * The test contains a pre-built table of instructions, operands and
 * expected results. For each table entry, the test will cyclically use
 * different sets of operand registers and result registers.
 */

#include <post.h>
#include "cpu_asm.h"

#if CONFIG_POST & CONFIG_SYS_POST_CPU

extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
    ulong op2);
extern ulong cpu_post_makecr (long v);

static struct cpu_post_three_s
{
    ulong cmd;
    ulong op1;
    ulong op2;
    ulong res;
} cpu_post_three_table[] =
{
    {
	OP_ADD,
	100,
	200,
	300
    },
    {
	OP_ADD,
	100,
	-200,
	-100
    },
    {
	OP_ADDC,
	100,
	200,
	300
    },
    {
	OP_ADDC,
	100,
	-200,
	-100
    },
    {
	OP_ADDE,
	100,
	200,
	300
    },
    {
	OP_ADDE,
	100,
	-200,
	-100
    },
    {
	OP_SUBF,
	100,
	200,
	100
    },
    {
	OP_SUBF,
	300,
	200,
	-100
    },
    {
	OP_SUBFC,
	100,
	200,
	100
    },
    {
	OP_SUBFC,
	300,
	200,
	-100
    },
    {
	OP_SUBFE,
	100,
	200,
	200 + ~100
    },
    {
	OP_SUBFE,
	300,
	200,
	200 + ~300
    },
    {
	OP_MULLW,
	200,
	300,
	200 * 300
    },
    {
	OP_MULHW,
	0x10000000,
	0x10000000,
	0x1000000
    },
    {
	OP_MULHWU,
	0x80000000,
	0x80000000,
	0x40000000
    },
    {
	OP_DIVW,
	-20,
	5,
	-4
    },
    {
	OP_DIVWU,
	0x8000,
	0x200,
	0x40
    },
};
static unsigned int cpu_post_three_size = ARRAY_SIZE(cpu_post_three_table);

int cpu_post_test_three (void)
{
    int ret = 0;
    unsigned int i, reg;
    int flag = disable_interrupts();

    for (i = 0; i < cpu_post_three_size && ret == 0; i++)
    {
	struct cpu_post_three_s *test = cpu_post_three_table + i;

	for (reg = 0; reg < 32 && ret == 0; reg++)
	{
	    unsigned int reg0 = (reg + 0) % 32;
	    unsigned int reg1 = (reg + 1) % 32;
	    unsigned int reg2 = (reg + 2) % 32;
	    unsigned int stk = reg < 16 ? 31 : 15;
	    unsigned long code[] =
	    {
		ASM_STW(stk, 1, -4),
		ASM_ADDI(stk, 1, -24),
		ASM_STW(3, stk, 12),
		ASM_STW(4, stk, 16),
		ASM_STW(reg0, stk, 8),
		ASM_STW(reg1, stk, 4),
		ASM_STW(reg2, stk, 0),
		ASM_LWZ(reg1, stk, 12),
		ASM_LWZ(reg0, stk, 16),
		ASM_12(test->cmd, reg2, reg1, reg0),
		ASM_STW(reg2, stk, 12),
		ASM_LWZ(reg2, stk, 0),
		ASM_LWZ(reg1, stk, 4),
		ASM_LWZ(reg0, stk, 8),
		ASM_LWZ(3, stk, 12),
		ASM_ADDI(1, stk, 24),
		ASM_LWZ(stk, 1, -4),
		ASM_BLR,
	    };
	    unsigned long codecr[] =
	    {
		ASM_STW(stk, 1, -4),
		ASM_ADDI(stk, 1, -24),
		ASM_STW(3, stk, 12),
		ASM_STW(4, stk, 16),
		ASM_STW(reg0, stk, 8),
		ASM_STW(reg1, stk, 4),
		ASM_STW(reg2, stk, 0),
		ASM_LWZ(reg1, stk, 12),
		ASM_LWZ(reg0, stk, 16),
		ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C,
		ASM_STW(reg2, stk, 12),
		ASM_LWZ(reg2, stk, 0),
		ASM_LWZ(reg1, stk, 4),
		ASM_LWZ(reg0, stk, 8),
		ASM_LWZ(3, stk, 12),
		ASM_ADDI(1, stk, 24),
		ASM_LWZ(stk, 1, -4),
		ASM_BLR,
	    };
	    ulong res;
	    ulong cr;

	    if (ret == 0)
	    {
		cr = 0;
		cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);

		ret = res == test->res && cr == 0 ? 0 : -1;

		if (ret != 0)
		{
		    post_log ("Error at three test %d !\n", i);
		}
	    }

	    if (ret == 0)
	    {
		cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);

		ret = res == test->res &&
		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;

		if (ret != 0)
		{
		    post_log ("Error at three test %d !\n", i);
		}
	    }
	}
    }

    if (flag)
	enable_interrupts();

    return ret;
}

#endif
Commit	Line	Data
ad5bb451 WD	1	/*
	2	* (C) Copyright 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
ad5bb451 WD	6	*/
	7
	8	#include <common.h>
	9
	10	/*
	11	* CPU test
	12	* Ternary instructions instr rD,rA,rB
	13	*
	14	* Arithmetic instructions: add, addc, adde, subf, subfc, subfe,
	15	* mullw, mulhw, mulhwu, divw, divwu
	16	*
	17	* The test contains a pre-built table of instructions, operands and
	18	* expected results. For each table entry, the test will cyclically use
	19	* different sets of operand registers and result registers.
	20	*/
	21
ad5bb451 WD	22	#include <post.h>
	23	#include "cpu_asm.h"
	24
6d0f6bcf	25	#if CONFIG_POST & CONFIG_SYS_POST_CPU
ad5bb451 WD	26
	27	extern void cpu_post_exec_22 (ulong code, ulong cr, ulong *res, ulong op1,
	28	ulong op2);
	29	extern ulong cpu_post_makecr (long v);
	30
	31	static struct cpu_post_three_s
	32	{
	33	ulong cmd;
	34	ulong op1;
	35	ulong op2;
	36	ulong res;
	37	} cpu_post_three_table[] =
	38	{
	39	{
53677ef1	40	OP_ADD,
ad5bb451 WD	41	100,
	42	200,
	43	300
	44	},
	45	{
53677ef1	46	OP_ADD,
ad5bb451 WD	47	100,
	48	-200,
	49	-100
	50	},
	51	{
53677ef1	52	OP_ADDC,
ad5bb451 WD	53	100,
	54	200,
	55	300
	56	},
	57	{
53677ef1	58	OP_ADDC,
ad5bb451 WD	59	100,
	60	-200,
	61	-100
	62	},
	63	{
53677ef1	64	OP_ADDE,
ad5bb451 WD	65	100,
	66	200,
	67	300
	68	},
	69	{
53677ef1	70	OP_ADDE,
ad5bb451 WD	71	100,
	72	-200,
	73	-100
	74	},
	75	{
53677ef1	76	OP_SUBF,
ad5bb451 WD	77	100,
	78	200,
	79	100
	80	},
	81	{
53677ef1	82	OP_SUBF,
ad5bb451 WD	83	300,
	84	200,
	85	-100
	86	},
	87	{
53677ef1	88	OP_SUBFC,
ad5bb451 WD	89	100,
	90	200,
	91	100
	92	},
	93	{
53677ef1	94	OP_SUBFC,
ad5bb451 WD	95	300,
	96	200,
	97	-100
	98	},
	99	{
53677ef1	100	OP_SUBFE,
ad5bb451 WD	101	100,
	102	200,
	103	200 + ~100
	104	},
	105	{
53677ef1	106	OP_SUBFE,
ad5bb451 WD	107	300,
	108	200,
	109	200 + ~300
	110	},
	111	{
53677ef1	112	OP_MULLW,
ad5bb451 WD	113	200,
	114	300,
	115	200 * 300
	116	},
	117	{
53677ef1	118	OP_MULHW,
ad5bb451 WD	119	0x10000000,
	120	0x10000000,
	121	0x1000000
	122	},
	123	{
53677ef1	124	OP_MULHWU,
ad5bb451 WD	125	0x80000000,
	126	0x80000000,
	127	0x40000000
	128	},
	129	{
53677ef1	130	OP_DIVW,
ad5bb451 WD	131	-20,
	132	5,
	133	-4
	134	},
	135	{
53677ef1	136	OP_DIVWU,
ad5bb451 WD	137	0x8000,
	138	0x200,
	139	0x40
	140	},
	141	};
d2397817	142	static unsigned int cpu_post_three_size = ARRAY_SIZE(cpu_post_three_table);
ad5bb451 WD	143
	144	int cpu_post_test_three (void)
	145	{
	146	int ret = 0;
	147	unsigned int i, reg;
	148	int flag = disable_interrupts();
	149
	150	for (i = 0; i < cpu_post_three_size && ret == 0; i++)
	151	{
	152	struct cpu_post_three_s *test = cpu_post_three_table + i;
	153
	154	for (reg = 0; reg < 32 && ret == 0; reg++)
	155	{
	156	unsigned int reg0 = (reg + 0) % 32;
	157	unsigned int reg1 = (reg + 1) % 32;
	158	unsigned int reg2 = (reg + 2) % 32;
	159	unsigned int stk = reg < 16 ? 31 : 15;
53677ef1	160	unsigned long code[] =
ad5bb451 WD	161	{
	162	ASM_STW(stk, 1, -4),
	163	ASM_ADDI(stk, 1, -24),
	164	ASM_STW(3, stk, 12),
	165	ASM_STW(4, stk, 16),
	166	ASM_STW(reg0, stk, 8),
	167	ASM_STW(reg1, stk, 4),
	168	ASM_STW(reg2, stk, 0),
	169	ASM_LWZ(reg1, stk, 12),
	170	ASM_LWZ(reg0, stk, 16),
	171	ASM_12(test->cmd, reg2, reg1, reg0),
	172	ASM_STW(reg2, stk, 12),
	173	ASM_LWZ(reg2, stk, 0),
	174	ASM_LWZ(reg1, stk, 4),
	175	ASM_LWZ(reg0, stk, 8),
	176	ASM_LWZ(3, stk, 12),
	177	ASM_ADDI(1, stk, 24),
	178	ASM_LWZ(stk, 1, -4),
	179	ASM_BLR,
	180	};
53677ef1	181	unsigned long codecr[] =
ad5bb451 WD	182	{
	183	ASM_STW(stk, 1, -4),
	184	ASM_ADDI(stk, 1, -24),
	185	ASM_STW(3, stk, 12),
	186	ASM_STW(4, stk, 16),
	187	ASM_STW(reg0, stk, 8),
	188	ASM_STW(reg1, stk, 4),
	189	ASM_STW(reg2, stk, 0),
	190	ASM_LWZ(reg1, stk, 12),
	191	ASM_LWZ(reg0, stk, 16),
	192	ASM_12(test->cmd, reg2, reg1, reg0) \| BIT_C,
	193	ASM_STW(reg2, stk, 12),
	194	ASM_LWZ(reg2, stk, 0),
	195	ASM_LWZ(reg1, stk, 4),
	196	ASM_LWZ(reg0, stk, 8),
	197	ASM_LWZ(3, stk, 12),
	198	ASM_ADDI(1, stk, 24),
	199	ASM_LWZ(stk, 1, -4),
	200	ASM_BLR,
	201	};
	202	ulong res;
	203	ulong cr;
	204
	205	if (ret == 0)
	206	{
53677ef1 WD	207	cr = 0;
53677ef1 WD	208	cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
ad5bb451	209
53677ef1	210	ret = res == test->res && cr == 0 ? 0 : -1;
ad5bb451	211
53677ef1 WD	212	if (ret != 0)
53677ef1 WD	213	{
93e14596	214	post_log ("Error at three test %d !\n", i);
53677ef1	215	}
ad5bb451 WD	216	}
	217
	218	if (ret == 0)
	219	{
53677ef1	220	cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
ad5bb451	221
53677ef1	222	ret = res == test->res &&
ad5bb451 WD	223	(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
ad5bb451 WD	224
53677ef1 WD	225	if (ret != 0)
53677ef1 WD	226	{
93e14596 WD	227	post_log ("Error at three test %d !\n", i);
93e14596 WD	228	}
ad5bb451 WD	229	}
	230	}
	231	}
	232
	233	if (flag)
53677ef1	234	enable_interrupts();
ad5bb451 WD	235
	236	return ret;
	237	}
	238
	239	#endif