[people/ms/u-boot.git] / post / lib_powerpc / threei.c

/*
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

/*
 * CPU test
 * Ternary instructions		instr rA,rS,UIMM
 *
 * Logic instructions:		ori, oris, xori, xoris
 *
 * The test contains a pre-built table of instructions, operands and
 * expected results. For each table entry, the test will cyclically use
 * different sets of operand registers and result registers.
 */

#include <post.h>
#include "cpu_asm.h"

#if CONFIG_POST & CONFIG_SYS_POST_CPU

extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
extern ulong cpu_post_makecr (long v);

static struct cpu_post_threei_s
{
    ulong cmd;
    ulong op1;
    ushort op2;
    ulong res;
} cpu_post_threei_table[] =
{
    {
	OP_ORI,
	0x80000000,
	0xffff,
	0x8000ffff
    },
    {
	OP_ORIS,
	0x00008000,
	0xffff,
	0xffff8000
    },
    {
	OP_XORI,
	0x8000ffff,
	0xffff,
	0x80000000
    },
    {
	OP_XORIS,
	0x00008000,
	0xffff,
	0xffff8000
    },
};
static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);

int cpu_post_test_threei (void)
{
    int ret = 0;
    unsigned int i, reg;
    int flag = disable_interrupts();

    for (i = 0; i < cpu_post_threei_size && ret == 0; i++)
    {
	struct cpu_post_threei_s *test = cpu_post_threei_table + i;

	for (reg = 0; reg < 32 && ret == 0; reg++)
	{
	    unsigned int reg0 = (reg + 0) % 32;
	    unsigned int reg1 = (reg + 1) % 32;
	    unsigned int stk = reg < 16 ? 31 : 15;
	    unsigned long code[] =
	    {
		ASM_STW(stk, 1, -4),
		ASM_ADDI(stk, 1, -16),
		ASM_STW(3, stk, 8),
		ASM_STW(reg0, stk, 4),
		ASM_STW(reg1, stk, 0),
		ASM_LWZ(reg0, stk, 8),
		ASM_11IX(test->cmd, reg1, reg0, test->op2),
		ASM_STW(reg1, stk, 8),
		ASM_LWZ(reg1, stk, 0),
		ASM_LWZ(reg0, stk, 4),
		ASM_LWZ(3, stk, 8),
		ASM_ADDI(1, stk, 16),
		ASM_LWZ(stk, 1, -4),
		ASM_BLR,
	    };
	    ulong res;
	    ulong cr;

	    cr = 0;
	    cpu_post_exec_21 (code, & cr, & res, test->op1);

	    ret = res == test->res && cr == 0 ? 0 : -1;

	    if (ret != 0)
	    {
		post_log ("Error at threei test %d !\n", i);
	    }
	}
    }

    if (flag)
	enable_interrupts();

    return ret;
}

#endif
Commit	Line	Data
ad5bb451 WD	1	/*
	2	* (C) Copyright 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
ad5bb451 WD	6	*/
	7
	8	#include <common.h>
	9
	10	/*
	11	* CPU test
	12	* Ternary instructions instr rA,rS,UIMM
	13	*
	14	* Logic instructions: ori, oris, xori, xoris
	15	*
	16	* The test contains a pre-built table of instructions, operands and
	17	* expected results. For each table entry, the test will cyclically use
	18	* different sets of operand registers and result registers.
	19	*/
	20
ad5bb451 WD	21	#include <post.h>
	22	#include "cpu_asm.h"
	23
6d0f6bcf	24	#if CONFIG_POST & CONFIG_SYS_POST_CPU
ad5bb451 WD	25
	26	extern void cpu_post_exec_21 (ulong code, ulong cr, ulong *res, ulong op);
	27	extern ulong cpu_post_makecr (long v);
	28
	29	static struct cpu_post_threei_s
	30	{
	31	ulong cmd;
	32	ulong op1;
	33	ushort op2;
	34	ulong res;
	35	} cpu_post_threei_table[] =
	36	{
	37	{
53677ef1	38	OP_ORI,
ad5bb451 WD	39	0x80000000,
	40	0xffff,
	41	0x8000ffff
	42	},
	43	{
53677ef1	44	OP_ORIS,
ad5bb451 WD	45	0x00008000,
	46	0xffff,
	47	0xffff8000
	48	},
	49	{
53677ef1	50	OP_XORI,
ad5bb451 WD	51	0x8000ffff,
	52	0xffff,
	53	0x80000000
	54	},
	55	{
53677ef1	56	OP_XORIS,
ad5bb451 WD	57	0x00008000,
	58	0xffff,
	59	0xffff8000
	60	},
	61	};
d2397817	62	static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);
ad5bb451 WD	63
	64	int cpu_post_test_threei (void)
	65	{
	66	int ret = 0;
	67	unsigned int i, reg;
	68	int flag = disable_interrupts();
	69
	70	for (i = 0; i < cpu_post_threei_size && ret == 0; i++)
	71	{
	72	struct cpu_post_threei_s *test = cpu_post_threei_table + i;
	73
	74	for (reg = 0; reg < 32 && ret == 0; reg++)
	75	{
	76	unsigned int reg0 = (reg + 0) % 32;
	77	unsigned int reg1 = (reg + 1) % 32;
	78	unsigned int stk = reg < 16 ? 31 : 15;
53677ef1	79	unsigned long code[] =
ad5bb451 WD	80	{
	81	ASM_STW(stk, 1, -4),
	82	ASM_ADDI(stk, 1, -16),
	83	ASM_STW(3, stk, 8),
	84	ASM_STW(reg0, stk, 4),
	85	ASM_STW(reg1, stk, 0),
	86	ASM_LWZ(reg0, stk, 8),
	87	ASM_11IX(test->cmd, reg1, reg0, test->op2),
	88	ASM_STW(reg1, stk, 8),
	89	ASM_LWZ(reg1, stk, 0),
	90	ASM_LWZ(reg0, stk, 4),
	91	ASM_LWZ(3, stk, 8),
	92	ASM_ADDI(1, stk, 16),
	93	ASM_LWZ(stk, 1, -4),
	94	ASM_BLR,
	95	};
	96	ulong res;
	97	ulong cr;
	98
53677ef1	99	cr = 0;
ad5bb451 WD	100	cpu_post_exec_21 (code, & cr, & res, test->op1);
	101
	102	ret = res == test->res && cr == 0 ? 0 : -1;
	103
	104	if (ret != 0)
	105	{
93e14596	106	post_log ("Error at threei test %d !\n", i);
ad5bb451 WD	107	}
	108	}
	109	}
	110
	111	if (flag)
53677ef1	112	enable_interrupts();
ad5bb451 WD	113
	114	return ret;
	115	}
	116
	117	#endif