[people/ms/u-boot.git] / post / lib_powerpc / threex.c

/*
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

/*
 * CPU test
 * Ternary instructions		instr rA,rS,rB
 *
 * Logic instructions:		or, orc, xor, nand, nor, eqv
 * Shift instructions:		slw, srw, sraw
 *
 * The test contains a pre-built table of instructions, operands and
 * expected results. For each table entry, the test will cyclically use
 * different sets of operand registers and result registers.
 */

#include <post.h>
#include "cpu_asm.h"

#if CONFIG_POST & CONFIG_SYS_POST_CPU

extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
    ulong op2);
extern ulong cpu_post_makecr (long v);

static struct cpu_post_threex_s
{
    ulong cmd;
    ulong op1;
    ulong op2;
    ulong res;
} cpu_post_threex_table[] =
{
    {
	OP_OR,
	0x1234,
	0x5678,
	0x1234 | 0x5678
    },
    {
	OP_ORC,
	0x1234,
	0x5678,
	0x1234 | ~0x5678
    },
    {
	OP_XOR,
	0x1234,
	0x5678,
	0x1234 ^ 0x5678
    },
    {
	OP_NAND,
	0x1234,
	0x5678,
	~(0x1234 & 0x5678)
    },
    {
	OP_NOR,
	0x1234,
	0x5678,
	~(0x1234 | 0x5678)
    },
    {
	OP_EQV,
	0x1234,
	0x5678,
	~(0x1234 ^ 0x5678)
    },
    {
	OP_SLW,
	0x80,
	16,
	0x800000
    },
    {
	OP_SLW,
	0x80,
	32,
	0
    },
    {
	OP_SRW,
	0x800000,
	16,
	0x80
    },
    {
	OP_SRW,
	0x800000,
	32,
	0
    },
    {
	OP_SRAW,
	0x80000000,
	3,
	0xf0000000
    },
    {
	OP_SRAW,
	0x8000,
	3,
	0x1000
    },
};
static unsigned int cpu_post_threex_size = ARRAY_SIZE(cpu_post_threex_table);

int cpu_post_test_threex (void)
{
    int ret = 0;
    unsigned int i, reg;
    int flag = disable_interrupts();

    for (i = 0; i < cpu_post_threex_size && ret == 0; i++)
    {
	struct cpu_post_threex_s *test = cpu_post_threex_table + i;

	for (reg = 0; reg < 32 && ret == 0; reg++)
	{
	    unsigned int reg0 = (reg + 0) % 32;
	    unsigned int reg1 = (reg + 1) % 32;
	    unsigned int reg2 = (reg + 2) % 32;
	    unsigned int stk = reg < 16 ? 31 : 15;
	    unsigned long code[] =
	    {
		ASM_STW(stk, 1, -4),
		ASM_ADDI(stk, 1, -24),
		ASM_STW(3, stk, 12),
		ASM_STW(4, stk, 16),
		ASM_STW(reg0, stk, 8),
		ASM_STW(reg1, stk, 4),
		ASM_STW(reg2, stk, 0),
		ASM_LWZ(reg1, stk, 12),
		ASM_LWZ(reg0, stk, 16),
		ASM_12X(test->cmd, reg2, reg1, reg0),
		ASM_STW(reg2, stk, 12),
		ASM_LWZ(reg2, stk, 0),
		ASM_LWZ(reg1, stk, 4),
		ASM_LWZ(reg0, stk, 8),
		ASM_LWZ(3, stk, 12),
		ASM_ADDI(1, stk, 24),
		ASM_LWZ(stk, 1, -4),
		ASM_BLR,
	    };
	    unsigned long codecr[] =
	    {
		ASM_STW(stk, 1, -4),
		ASM_ADDI(stk, 1, -24),
		ASM_STW(3, stk, 12),
		ASM_STW(4, stk, 16),
		ASM_STW(reg0, stk, 8),
		ASM_STW(reg1, stk, 4),
		ASM_STW(reg2, stk, 0),
		ASM_LWZ(reg1, stk, 12),
		ASM_LWZ(reg0, stk, 16),
		ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C,
		ASM_STW(reg2, stk, 12),
		ASM_LWZ(reg2, stk, 0),
		ASM_LWZ(reg1, stk, 4),
		ASM_LWZ(reg0, stk, 8),
		ASM_LWZ(3, stk, 12),
		ASM_ADDI(1, stk, 24),
		ASM_LWZ(stk, 1, -4),
		ASM_BLR,
	    };
	    ulong res;
	    ulong cr;

	    if (ret == 0)
	    {
		cr = 0;
		cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);

		ret = res == test->res && cr == 0 ? 0 : -1;

		if (ret != 0)
		{
		    post_log ("Error at threex test %d !\n", i);
		}
	    }

	    if (ret == 0)
	    {
		cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);

		ret = res == test->res &&
		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;

		if (ret != 0)
		{
		    post_log ("Error at threex test %d !\n", i);
		}
	    }
	}
    }

    if (flag)
	enable_interrupts();

    return ret;
}

#endif
Commit	Line	Data
ad5bb451 WD	1	/*
	2	* (C) Copyright 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
ad5bb451 WD	6	*/
	7
	8	#include <common.h>
	9
	10	/*
	11	* CPU test
	12	* Ternary instructions instr rA,rS,rB
	13	*
	14	* Logic instructions: or, orc, xor, nand, nor, eqv
	15	* Shift instructions: slw, srw, sraw
	16	*
	17	* The test contains a pre-built table of instructions, operands and
	18	* expected results. For each table entry, the test will cyclically use
	19	* different sets of operand registers and result registers.
	20	*/
	21
ad5bb451 WD	22	#include <post.h>
	23	#include "cpu_asm.h"
	24
6d0f6bcf	25	#if CONFIG_POST & CONFIG_SYS_POST_CPU
ad5bb451 WD	26
	27	extern void cpu_post_exec_22 (ulong code, ulong cr, ulong *res, ulong op1,
	28	ulong op2);
	29	extern ulong cpu_post_makecr (long v);
	30
	31	static struct cpu_post_threex_s
	32	{
	33	ulong cmd;
	34	ulong op1;
	35	ulong op2;
	36	ulong res;
	37	} cpu_post_threex_table[] =
	38	{
	39	{
53677ef1	40	OP_OR,
ad5bb451 WD	41	0x1234,
	42	0x5678,
	43	0x1234 \| 0x5678
	44	},
	45	{
53677ef1	46	OP_ORC,
ad5bb451 WD	47	0x1234,
	48	0x5678,
	49	0x1234 \| ~0x5678
	50	},
	51	{
53677ef1	52	OP_XOR,
ad5bb451 WD	53	0x1234,
	54	0x5678,
	55	0x1234 ^ 0x5678
	56	},
	57	{
53677ef1	58	OP_NAND,
ad5bb451 WD	59	0x1234,
	60	0x5678,
	61	~(0x1234 & 0x5678)
	62	},
	63	{
53677ef1	64	OP_NOR,
ad5bb451 WD	65	0x1234,
	66	0x5678,
	67	~(0x1234 \| 0x5678)
	68	},
	69	{
53677ef1	70	OP_EQV,
ad5bb451 WD	71	0x1234,
	72	0x5678,
	73	~(0x1234 ^ 0x5678)
	74	},
	75	{
53677ef1	76	OP_SLW,
ad5bb451 WD	77	0x80,
	78	16,
	79	0x800000
	80	},
	81	{
53677ef1	82	OP_SLW,
ad5bb451 WD	83	0x80,
	84	32,
	85	0
	86	},
	87	{
53677ef1	88	OP_SRW,
ad5bb451 WD	89	0x800000,
	90	16,
	91	0x80
	92	},
	93	{
53677ef1	94	OP_SRW,
ad5bb451 WD	95	0x800000,
	96	32,
	97	0
	98	},
	99	{
53677ef1	100	OP_SRAW,
ad5bb451 WD	101	0x80000000,
	102	3,
	103	0xf0000000
	104	},
	105	{
53677ef1	106	OP_SRAW,
ad5bb451 WD	107	0x8000,
	108	3,
	109	0x1000
	110	},
	111	};
d2397817	112	static unsigned int cpu_post_threex_size = ARRAY_SIZE(cpu_post_threex_table);
ad5bb451 WD	113
	114	int cpu_post_test_threex (void)
	115	{
	116	int ret = 0;
	117	unsigned int i, reg;
	118	int flag = disable_interrupts();
	119
	120	for (i = 0; i < cpu_post_threex_size && ret == 0; i++)
	121	{
	122	struct cpu_post_threex_s *test = cpu_post_threex_table + i;
	123
	124	for (reg = 0; reg < 32 && ret == 0; reg++)
	125	{
	126	unsigned int reg0 = (reg + 0) % 32;
	127	unsigned int reg1 = (reg + 1) % 32;
	128	unsigned int reg2 = (reg + 2) % 32;
	129	unsigned int stk = reg < 16 ? 31 : 15;
53677ef1	130	unsigned long code[] =
ad5bb451 WD	131	{
	132	ASM_STW(stk, 1, -4),
	133	ASM_ADDI(stk, 1, -24),
	134	ASM_STW(3, stk, 12),
	135	ASM_STW(4, stk, 16),
	136	ASM_STW(reg0, stk, 8),
	137	ASM_STW(reg1, stk, 4),
	138	ASM_STW(reg2, stk, 0),
	139	ASM_LWZ(reg1, stk, 12),
	140	ASM_LWZ(reg0, stk, 16),
	141	ASM_12X(test->cmd, reg2, reg1, reg0),
	142	ASM_STW(reg2, stk, 12),
	143	ASM_LWZ(reg2, stk, 0),
	144	ASM_LWZ(reg1, stk, 4),
	145	ASM_LWZ(reg0, stk, 8),
	146	ASM_LWZ(3, stk, 12),
	147	ASM_ADDI(1, stk, 24),
	148	ASM_LWZ(stk, 1, -4),
	149	ASM_BLR,
	150	};
53677ef1	151	unsigned long codecr[] =
ad5bb451 WD	152	{
	153	ASM_STW(stk, 1, -4),
	154	ASM_ADDI(stk, 1, -24),
	155	ASM_STW(3, stk, 12),
	156	ASM_STW(4, stk, 16),
	157	ASM_STW(reg0, stk, 8),
	158	ASM_STW(reg1, stk, 4),
	159	ASM_STW(reg2, stk, 0),
	160	ASM_LWZ(reg1, stk, 12),
	161	ASM_LWZ(reg0, stk, 16),
	162	ASM_12X(test->cmd, reg2, reg1, reg0) \| BIT_C,
	163	ASM_STW(reg2, stk, 12),
	164	ASM_LWZ(reg2, stk, 0),
	165	ASM_LWZ(reg1, stk, 4),
	166	ASM_LWZ(reg0, stk, 8),
	167	ASM_LWZ(3, stk, 12),
	168	ASM_ADDI(1, stk, 24),
	169	ASM_LWZ(stk, 1, -4),
	170	ASM_BLR,
	171	};
	172	ulong res;
	173	ulong cr;
	174
	175	if (ret == 0)
	176	{
53677ef1 WD	177	cr = 0;
53677ef1 WD	178	cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
ad5bb451	179
53677ef1	180	ret = res == test->res && cr == 0 ? 0 : -1;
ad5bb451	181
53677ef1 WD	182	if (ret != 0)
53677ef1 WD	183	{
93e14596	184	post_log ("Error at threex test %d !\n", i);
53677ef1	185	}
ad5bb451 WD	186	}
	187
	188	if (ret == 0)
	189	{
53677ef1	190	cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
ad5bb451	191
53677ef1	192	ret = res == test->res &&
ad5bb451 WD	193	(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
ad5bb451 WD	194
53677ef1 WD	195	if (ret != 0)
53677ef1 WD	196	{
93e14596 WD	197	post_log ("Error at threex test %d !\n", i);
93e14596 WD	198	}
ad5bb451 WD	199	}
	200	}
	201	}
	202
	203	if (flag)
53677ef1	204	enable_interrupts();
ad5bb451 WD	205
	206	return ret;
	207	}
	208
	209	#endif