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CommitLineData
8edcde5e
SB
1/*
2 * (C) Copyright 2009
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * (C) Copyright 2008
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
8 *
3765b3e7 9 * SPDX-License-Identifier: GPL-2.0+
8edcde5e
SB
10 */
11
f86ed6a8 12#include "imagetool.h"
8edcde5e
SB
13#include <image.h>
14#include "imximage.h"
15
0187c985
SB
16#define UNDEFINED 0xFFFFFFFF
17
8edcde5e
SB
18/*
19 * Supported commands for configuration file
20 */
21static table_entry_t imximage_cmds[] = {
8a1edd7d 22 {CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
6cb83829 23 {CMD_BOOT_OFFSET, "BOOT_OFFSET", "Boot offset", },
0b7f7c33
AA
24 {CMD_WRITE_DATA, "DATA", "Reg Write Data", },
25 {CMD_WRITE_CLR_BIT, "CLR_BIT", "Reg clear bit", },
26 {CMD_CHECK_BITS_SET, "CHECK_BITS_SET", "Reg Check bits set", },
27 {CMD_CHECK_BITS_CLR, "CHECK_BITS_CLR", "Reg Check bits clr", },
0187c985 28 {CMD_CSF, "CSF", "Command Sequence File", },
8a1edd7d 29 {CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
b55e4f48 30 {CMD_PLUGIN, "PLUGIN", "file plugin_addr", },
8a1edd7d 31 {-1, "", "", },
8edcde5e
SB
32};
33
34/*
35 * Supported Boot options for configuration file
36 * this is needed to set the correct flash offset
37 */
377e367a 38static table_entry_t imximage_boot_offset[] = {
8edcde5e 39 {FLASH_OFFSET_ONENAND, "onenand", "OneNAND Flash",},
bd25864c 40 {FLASH_OFFSET_NAND, "nand", "NAND Flash", },
19b409c0
DB
41 {FLASH_OFFSET_NOR, "nor", "NOR Flash", },
42 {FLASH_OFFSET_SATA, "sata", "SATA Disk", },
bd25864c
DB
43 {FLASH_OFFSET_SD, "sd", "SD Card", },
44 {FLASH_OFFSET_SPI, "spi", "SPI Flash", },
9598f8c3 45 {FLASH_OFFSET_QSPI, "qspi", "QSPI NOR Flash",},
8edcde5e
SB
46 {-1, "", "Invalid", },
47};
48
377e367a
SB
49/*
50 * Supported Boot options for configuration file
51 * this is needed to determine the initial load size
52 */
53static table_entry_t imximage_boot_loadsize[] = {
54 {FLASH_LOADSIZE_ONENAND, "onenand", "OneNAND Flash",},
55 {FLASH_LOADSIZE_NAND, "nand", "NAND Flash", },
56 {FLASH_LOADSIZE_NOR, "nor", "NOR Flash", },
57 {FLASH_LOADSIZE_SATA, "sata", "SATA Disk", },
58 {FLASH_LOADSIZE_SD, "sd", "SD Card", },
59 {FLASH_LOADSIZE_SPI, "spi", "SPI Flash", },
9598f8c3 60 {FLASH_LOADSIZE_QSPI, "qspi", "QSPI NOR Flash",},
377e367a
SB
61 {-1, "", "Invalid", },
62};
63
8a1edd7d
LHR
64/*
65 * IMXIMAGE version definition for i.MX chips
66 */
67static table_entry_t imximage_versions[] = {
68 {IMXIMAGE_V1, "", " (i.MX25/35/51 compatible)", },
0b7f7c33 69 {IMXIMAGE_V2, "", " (i.MX53/6/7 compatible)", },
8a1edd7d
LHR
70 {-1, "", " (Invalid)", },
71};
8edcde5e
SB
72
73static struct imx_header imximage_header;
8a1edd7d 74static uint32_t imximage_version;
0187c985
SB
75/*
76 * Image Vector Table Offset
77 * Initialized to a wrong not 4-bytes aligned address to
78 * check if it is was set by the cfg file.
79 */
80static uint32_t imximage_ivt_offset = UNDEFINED;
81static uint32_t imximage_csf_size = UNDEFINED;
377e367a
SB
82/* Initial Load Region Size */
83static uint32_t imximage_init_loadsize;
b55e4f48
PF
84static uint32_t imximage_iram_free_start;
85static uint32_t imximage_plugin_size;
86static uint32_t plugin_image;
8a1edd7d
LHR
87
88static set_dcd_val_t set_dcd_val;
0b7f7c33 89static set_dcd_param_t set_dcd_param;
8a1edd7d
LHR
90static set_dcd_rst_t set_dcd_rst;
91static set_imx_hdr_t set_imx_hdr;
4d5fa985 92static uint32_t max_dcd_entries;
24331982 93static uint32_t *header_size_ptr;
0187c985 94static uint32_t *csf_ptr;
8edcde5e
SB
95
96static uint32_t get_cfg_value(char *token, char *name, int linenr)
97{
98 char *endptr;
99 uint32_t value;
100
101 errno = 0;
102 value = strtoul(token, &endptr, 16);
103 if (errno || (token == endptr)) {
104 fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
105 name, linenr, token);
106 exit(EXIT_FAILURE);
107 }
108 return value;
109}
110
8a1edd7d 111static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
8edcde5e 112{
8a1edd7d
LHR
113 imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1;
114 imx_header_v2_t *hdr_v2 = &imx_hdr->header.hdr_v2;
115 flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
116 flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
117
118 /* Try to detect V1 */
119 if ((fhdr_v1->app_code_barker == APP_CODE_BARKER) &&
120 (hdr_v1->dcd_table.preamble.barker == DCD_BARKER))
121 return IMXIMAGE_V1;
122
123 /* Try to detect V2 */
124 if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
b55e4f48
PF
125 (hdr_v2->data.dcd_table.header.tag == DCD_HEADER_TAG))
126 return IMXIMAGE_V2;
127
128 if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
129 hdr_v2->boot_data.plugin)
8a1edd7d
LHR
130 return IMXIMAGE_V2;
131
132 return IMXIMAGE_VER_INVALID;
8edcde5e
SB
133}
134
8a1edd7d 135static void err_imximage_version(int version)
8edcde5e 136{
8a1edd7d
LHR
137 fprintf(stderr,
138 "Error: Unsupported imximage version:%d\n", version);
8edcde5e 139
8a1edd7d
LHR
140 exit(EXIT_FAILURE);
141}
8edcde5e 142
8a1edd7d
LHR
143static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
144 int fld, uint32_t value, uint32_t off)
145{
146 dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
147
148 switch (fld) {
149 case CFG_REG_SIZE:
150 /* Byte, halfword, word */
151 if ((value != 1) && (value != 2) && (value != 4)) {
152 fprintf(stderr, "Error: %s[%d] - "
153 "Invalid register size " "(%d)\n",
154 name, lineno, value);
155 exit(EXIT_FAILURE);
156 }
157 dcd_v1->addr_data[off].type = value;
158 break;
159 case CFG_REG_ADDRESS:
160 dcd_v1->addr_data[off].addr = value;
161 break;
162 case CFG_REG_VALUE:
163 dcd_v1->addr_data[off].value = value;
164 break;
165 default:
166 break;
8edcde5e 167
8a1edd7d
LHR
168 }
169}
8edcde5e 170
61903b75
TK
171static struct dcd_v2_cmd *gd_last_cmd;
172
0b7f7c33
AA
173static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len,
174 int32_t cmd)
175{
b55e4f48 176 dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.data.dcd_table;
61903b75
TK
177 struct dcd_v2_cmd *d = gd_last_cmd;
178 struct dcd_v2_cmd *d2;
179 int len;
180
181 if (!d)
182 d = &dcd_v2->dcd_cmd;
183 d2 = d;
184 len = be16_to_cpu(d->write_dcd_command.length);
185 if (len > 4)
186 d2 = (struct dcd_v2_cmd *)(((char *)d) + len);
0b7f7c33
AA
187
188 switch (cmd) {
189 case CMD_WRITE_DATA:
61903b75
TK
190 if ((d->write_dcd_command.tag == DCD_WRITE_DATA_COMMAND_TAG) &&
191 (d->write_dcd_command.param == DCD_WRITE_DATA_PARAM))
192 break;
193 d = d2;
194 d->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
195 d->write_dcd_command.length = cpu_to_be16(4);
196 d->write_dcd_command.param = DCD_WRITE_DATA_PARAM;
0b7f7c33
AA
197 break;
198 case CMD_WRITE_CLR_BIT:
61903b75
TK
199 if ((d->write_dcd_command.tag == DCD_WRITE_DATA_COMMAND_TAG) &&
200 (d->write_dcd_command.param == DCD_WRITE_CLR_BIT_PARAM))
201 break;
202 d = d2;
203 d->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
204 d->write_dcd_command.length = cpu_to_be16(4);
205 d->write_dcd_command.param = DCD_WRITE_CLR_BIT_PARAM;
0b7f7c33
AA
206 break;
207 /*
208 * Check data command only supports one entry,
0b7f7c33
AA
209 */
210 case CMD_CHECK_BITS_SET:
61903b75
TK
211 d = d2;
212 d->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
213 d->write_dcd_command.length = cpu_to_be16(4);
214 d->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
0b7f7c33
AA
215 break;
216 case CMD_CHECK_BITS_CLR:
61903b75
TK
217 d = d2;
218 d->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
219 d->write_dcd_command.length = cpu_to_be16(4);
0782a880 220 d->write_dcd_command.param = DCD_CHECK_BITS_CLR_PARAM;
0b7f7c33
AA
221 break;
222 default:
223 break;
224 }
61903b75 225 gd_last_cmd = d;
0b7f7c33
AA
226}
227
8a1edd7d
LHR
228static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
229 int fld, uint32_t value, uint32_t off)
230{
61903b75
TK
231 struct dcd_v2_cmd *d = gd_last_cmd;
232 int len;
233
234 len = be16_to_cpu(d->write_dcd_command.length);
235 off = (len - 4) >> 3;
8a1edd7d
LHR
236
237 switch (fld) {
238 case CFG_REG_ADDRESS:
61903b75 239 d->addr_data[off].addr = cpu_to_be32(value);
8a1edd7d
LHR
240 break;
241 case CFG_REG_VALUE:
61903b75
TK
242 d->addr_data[off].value = cpu_to_be32(value);
243 off++;
244 d->write_dcd_command.length = cpu_to_be16((off << 3) + 4);
8a1edd7d
LHR
245 break;
246 default:
247 break;
248
249 }
8edcde5e
SB
250}
251
8a1edd7d
LHR
252/*
253 * Complete setting up the rest field of DCD of V1
254 * such as barker code and DCD data length.
255 */
256static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
257 char *name, int lineno)
8edcde5e 258{
8a1edd7d
LHR
259 dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
260
8a1edd7d
LHR
261 dcd_v1->preamble.barker = DCD_BARKER;
262 dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
263}
264
265/*
266 * Complete setting up the reset field of DCD of V2
267 * such as DCD tag, version, length, etc.
268 */
269static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
270 char *name, int lineno)
271{
b55e4f48
PF
272 if (!imxhdr->header.hdr_v2.boot_data.plugin) {
273 dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.data.dcd_table;
274 struct dcd_v2_cmd *d = gd_last_cmd;
275 int len;
276
277 if (!d)
278 d = &dcd_v2->dcd_cmd;
279 len = be16_to_cpu(d->write_dcd_command.length);
280 if (len > 4)
281 d = (struct dcd_v2_cmd *)(((char *)d) + len);
282
283 len = (char *)d - (char *)&dcd_v2->header;
b55e4f48
PF
284 dcd_v2->header.tag = DCD_HEADER_TAG;
285 dcd_v2->header.length = cpu_to_be16(len);
286 dcd_v2->header.version = DCD_VERSION;
287 }
8a1edd7d
LHR
288}
289
290static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
ad0826dc 291 uint32_t entry_point, uint32_t flash_offset)
8a1edd7d
LHR
292{
293 imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
294 flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
295 dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
ab857f26 296 uint32_t hdr_base;
24331982
TK
297 uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
298 - ((char *)imxhdr));
8a1edd7d 299
8a1edd7d
LHR
300 /* Set magic number */
301 fhdr_v1->app_code_barker = APP_CODE_BARKER;
302
97f17fa6 303 hdr_base = entry_point - imximage_init_loadsize + flash_offset;
ab857f26 304 fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
ad0826dc 305 fhdr_v1->app_code_jump_vector = entry_point;
8a1edd7d 306
ab857f26
TK
307 fhdr_v1->dcd_ptr_ptr = hdr_base + offsetof(flash_header_v1_t, dcd_ptr);
308 fhdr_v1->dcd_ptr = hdr_base + offsetof(imx_header_v1_t, dcd_table);
8a1edd7d 309
8a1edd7d
LHR
310 /* Security feature are not supported */
311 fhdr_v1->app_code_csf = 0;
312 fhdr_v1->super_root_key = 0;
24331982 313 header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
8a1edd7d
LHR
314}
315
316static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
ad0826dc 317 uint32_t entry_point, uint32_t flash_offset)
8a1edd7d
LHR
318{
319 imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
320 flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
ab857f26 321 uint32_t hdr_base;
8a1edd7d 322
8a1edd7d
LHR
323 /* Set magic number */
324 fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
325 fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
326 fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
327
b55e4f48
PF
328 if (!hdr_v2->boot_data.plugin) {
329 fhdr_v2->entry = entry_point;
330 fhdr_v2->reserved1 = 0;
331 fhdr_v2->reserved1 = 0;
332 hdr_base = entry_point - imximage_init_loadsize +
333 flash_offset;
334 fhdr_v2->self = hdr_base;
335 if (dcd_len > 0)
336 fhdr_v2->dcd_ptr = hdr_base +
337 offsetof(imx_header_v2_t, data);
338 else
339 fhdr_v2->dcd_ptr = 0;
340 fhdr_v2->boot_data_ptr = hdr_base
341 + offsetof(imx_header_v2_t, boot_data);
342 hdr_v2->boot_data.start = entry_point - imximage_init_loadsize;
343
344 fhdr_v2->csf = 0;
345
346 header_size_ptr = &hdr_v2->boot_data.size;
347 csf_ptr = &fhdr_v2->csf;
348 } else {
349 imx_header_v2_t *next_hdr_v2;
350 flash_header_v2_t *next_fhdr_v2;
351
352 if (imximage_csf_size != 0) {
353 fprintf(stderr, "Error: Header v2: SECURE_BOOT is only supported in DCD mode!");
354 exit(EXIT_FAILURE);
355 }
356
357 fhdr_v2->entry = imximage_iram_free_start +
358 flash_offset + sizeof(flash_header_v2_t) +
359 sizeof(boot_data_t);
360
361 fhdr_v2->reserved1 = 0;
362 fhdr_v2->reserved2 = 0;
363 fhdr_v2->self = imximage_iram_free_start + flash_offset;
364
b893c989 365 fhdr_v2->dcd_ptr = 0;
8a1edd7d 366
b55e4f48
PF
367 fhdr_v2->boot_data_ptr = fhdr_v2->self +
368 offsetof(imx_header_v2_t, boot_data);
369
370 hdr_v2->boot_data.start = imximage_iram_free_start;
371 /*
372 * The actural size of plugin image is "imximage_plugin_size +
373 * sizeof(flash_header_v2_t) + sizeof(boot_data_t)", plus the
374 * flash_offset space.The ROM code only need to copy this size
375 * to run the plugin code. However, later when copy the whole
376 * U-Boot image to DDR, the ROM code use memcpy to copy the
377 * first part of the image, and use the storage read function
378 * to get the remaining part. This requires the dividing point
379 * must be multiple of storage sector size. Here we set the
380 * first section to be MAX_PLUGIN_CODE_SIZE(64KB) for this
381 * purpose.
382 */
383 hdr_v2->boot_data.size = MAX_PLUGIN_CODE_SIZE;
384
385 /* Security feature are not supported */
386 fhdr_v2->csf = 0;
387
388 next_hdr_v2 = (imx_header_v2_t *)((char *)hdr_v2 +
389 imximage_plugin_size);
390
391 next_fhdr_v2 = &next_hdr_v2->fhdr;
392
393 next_fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
394 next_fhdr_v2->header.length =
395 cpu_to_be16(sizeof(flash_header_v2_t));
396 next_fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
397
398 next_fhdr_v2->entry = entry_point;
399 hdr_base = entry_point - sizeof(struct imx_header);
400 next_fhdr_v2->reserved1 = 0;
401 next_fhdr_v2->reserved2 = 0;
402 next_fhdr_v2->self = hdr_base + imximage_plugin_size;
403
404 next_fhdr_v2->dcd_ptr = 0;
405 next_fhdr_v2->boot_data_ptr = next_fhdr_v2->self +
406 offsetof(imx_header_v2_t, boot_data);
407
408 next_hdr_v2->boot_data.start = hdr_base - flash_offset;
409
410 header_size_ptr = &next_hdr_v2->boot_data.size;
0187c985 411
b55e4f48
PF
412 next_hdr_v2->boot_data.plugin = 0;
413
414 next_fhdr_v2->csf = 0;
415 }
8a1edd7d
LHR
416}
417
72048bc3 418static void set_hdr_func(void)
8a1edd7d
LHR
419{
420 switch (imximage_version) {
421 case IMXIMAGE_V1:
422 set_dcd_val = set_dcd_val_v1;
0b7f7c33 423 set_dcd_param = NULL;
8a1edd7d
LHR
424 set_dcd_rst = set_dcd_rst_v1;
425 set_imx_hdr = set_imx_hdr_v1;
4d5fa985 426 max_dcd_entries = MAX_HW_CFG_SIZE_V1;
8a1edd7d
LHR
427 break;
428 case IMXIMAGE_V2:
61903b75 429 gd_last_cmd = NULL;
8a1edd7d 430 set_dcd_val = set_dcd_val_v2;
0b7f7c33 431 set_dcd_param = set_dcd_param_v2;
8a1edd7d
LHR
432 set_dcd_rst = set_dcd_rst_v2;
433 set_imx_hdr = set_imx_hdr_v2;
4d5fa985 434 max_dcd_entries = MAX_HW_CFG_SIZE_V2;
8a1edd7d
LHR
435 break;
436 default:
437 err_imximage_version(imximage_version);
438 break;
439 }
440}
8edcde5e 441
8a1edd7d
LHR
442static void print_hdr_v1(struct imx_header *imx_hdr)
443{
444 imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1;
445 flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
446 dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
447 uint32_t size, length, ver;
448
449 size = dcd_v1->preamble.length;
450 if (size > (MAX_HW_CFG_SIZE_V1 * sizeof(dcd_type_addr_data_t))) {
8edcde5e
SB
451 fprintf(stderr,
452 "Error: Image corrupt DCD size %d exceed maximum %d\n",
5b28e913 453 (uint32_t)(size / sizeof(dcd_type_addr_data_t)),
8a1edd7d
LHR
454 MAX_HW_CFG_SIZE_V1);
455 exit(EXIT_FAILURE);
456 }
457
458 length = dcd_v1->preamble.length / sizeof(dcd_type_addr_data_t);
459 ver = detect_imximage_version(imx_hdr);
460
461 printf("Image Type: Freescale IMX Boot Image\n");
462 printf("Image Ver: %x", ver);
463 printf("%s\n", get_table_entry_name(imximage_versions, NULL, ver));
464 printf("Data Size: ");
465 genimg_print_size(dcd_v1->addr_data[length].type);
466 printf("Load Address: %08x\n", (uint32_t)fhdr_v1->app_dest_ptr);
467 printf("Entry Point: %08x\n", (uint32_t)fhdr_v1->app_code_jump_vector);
468}
469
470static void print_hdr_v2(struct imx_header *imx_hdr)
471{
472 imx_header_v2_t *hdr_v2 = &imx_hdr->header.hdr_v2;
473 flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
b55e4f48
PF
474 dcd_v2_t *dcd_v2 = &hdr_v2->data.dcd_table;
475 uint32_t size, version, plugin;
8a1edd7d 476
b55e4f48
PF
477 plugin = hdr_v2->boot_data.plugin;
478 if (!plugin) {
479 size = be16_to_cpu(dcd_v2->header.length);
480 if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) {
481 fprintf(stderr,
482 "Error: Image corrupt DCD size %d exceed maximum %d\n",
483 (uint32_t)(size / sizeof(dcd_addr_data_t)),
484 MAX_HW_CFG_SIZE_V2);
485 exit(EXIT_FAILURE);
486 }
8edcde5e
SB
487 }
488
8a1edd7d 489 version = detect_imximage_version(imx_hdr);
8edcde5e
SB
490
491 printf("Image Type: Freescale IMX Boot Image\n");
8a1edd7d
LHR
492 printf("Image Ver: %x", version);
493 printf("%s\n", get_table_entry_name(imximage_versions, NULL, version));
b55e4f48
PF
494 printf("Mode: %s\n", plugin ? "PLUGIN" : "DCD");
495 if (!plugin) {
496 printf("Data Size: ");
497 genimg_print_size(hdr_v2->boot_data.size);
498 printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
499 printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
500 if (fhdr_v2->csf && (imximage_ivt_offset != UNDEFINED) &&
501 (imximage_csf_size != UNDEFINED)) {
e5491f3e
EN
502 uint16_t dcdlen;
503 int offs;
504
505 dcdlen = hdr_v2->data.dcd_table.header.length;
506 offs = (char *)&hdr_v2->data.dcd_table
507 - (char *)hdr_v2;
508
b55e4f48
PF
509 printf("HAB Blocks: %08x %08x %08x\n",
510 (uint32_t)fhdr_v2->self, 0,
511 hdr_v2->boot_data.size - imximage_ivt_offset -
512 imximage_csf_size);
e5491f3e
EN
513 printf("DCD Blocks: 00910000 %08x %08x\n",
514 offs, be16_to_cpu(dcdlen));
b55e4f48
PF
515 }
516 } else {
517 imx_header_v2_t *next_hdr_v2;
518 flash_header_v2_t *next_fhdr_v2;
519
520 /*First Header*/
521 printf("Plugin Data Size: ");
522 genimg_print_size(hdr_v2->boot_data.size);
523 printf("Plugin Code Size: ");
524 genimg_print_size(imximage_plugin_size);
525 printf("Plugin Load Address: %08x\n", hdr_v2->boot_data.start);
526 printf("Plugin Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
527
528 /*Second Header*/
529 next_hdr_v2 = (imx_header_v2_t *)((char *)hdr_v2 +
530 imximage_plugin_size);
531 next_fhdr_v2 = &next_hdr_v2->fhdr;
532 printf("U-Boot Data Size: ");
533 genimg_print_size(next_hdr_v2->boot_data.size);
534 printf("U-Boot Load Address: %08x\n",
535 next_hdr_v2->boot_data.start);
536 printf("U-Boot Entry Point: %08x\n",
537 (uint32_t)next_fhdr_v2->entry);
0187c985 538 }
8edcde5e
SB
539}
540
b55e4f48
PF
541static void copy_plugin_code(struct imx_header *imxhdr, char *plugin_file)
542{
2a380ccc 543 int ifd;
b55e4f48
PF
544 struct stat sbuf;
545 char *plugin_buf = imxhdr->header.hdr_v2.data.plugin_code;
546 char *ptr;
547
548 ifd = open(plugin_file, O_RDONLY|O_BINARY);
2a380ccc
PF
549 if (ifd < 0) {
550 fprintf(stderr, "Can't open %s: %s\n",
551 plugin_file,
552 strerror(errno));
553 exit(EXIT_FAILURE);
554 }
555
b55e4f48
PF
556 if (fstat(ifd, &sbuf) < 0) {
557 fprintf(stderr, "Can't stat %s: %s\n",
558 plugin_file,
559 strerror(errno));
560 exit(EXIT_FAILURE);
561 }
562
563 ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, ifd, 0);
564 if (ptr == MAP_FAILED) {
565 fprintf(stderr, "Can't read %s: %s\n",
566 plugin_file,
567 strerror(errno));
568 exit(EXIT_FAILURE);
569 }
570
571 if (sbuf.st_size > MAX_PLUGIN_CODE_SIZE) {
572 printf("plugin binary size too large\n");
573 exit(EXIT_FAILURE);
574 }
575
576 memcpy(plugin_buf, ptr, sbuf.st_size);
577 imximage_plugin_size = sbuf.st_size;
578
579 (void) munmap((void *)ptr, sbuf.st_size);
580 (void) close(ifd);
581
582 imxhdr->header.hdr_v2.boot_data.plugin = 1;
583}
584
8a1edd7d
LHR
585static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
586 char *name, int lineno, int fld, int dcd_len)
587{
588 int value;
589 static int cmd_ver_first = ~0;
590
591 switch (cmd) {
592 case CMD_IMAGE_VERSION:
593 imximage_version = get_cfg_value(token, name, lineno);
594 if (cmd_ver_first == 0) {
595 fprintf(stderr, "Error: %s[%d] - IMAGE_VERSION "
596 "command need be the first before other "
597 "valid command in the file\n", name, lineno);
598 exit(EXIT_FAILURE);
599 }
600 cmd_ver_first = 1;
72048bc3 601 set_hdr_func();
8a1edd7d
LHR
602 break;
603 case CMD_BOOT_FROM:
377e367a 604 imximage_ivt_offset = get_table_entry_id(imximage_boot_offset,
8a1edd7d 605 "imximage boot option", token);
3150f92c 606 if (imximage_ivt_offset == -1) {
8a1edd7d
LHR
607 fprintf(stderr, "Error: %s[%d] -Invalid boot device"
608 "(%s)\n", name, lineno, token);
609 exit(EXIT_FAILURE);
610 }
377e367a
SB
611
612 imximage_init_loadsize =
613 get_table_entry_id(imximage_boot_loadsize,
614 "imximage boot option", token);
615
616 if (imximage_init_loadsize == -1) {
617 fprintf(stderr,
618 "Error: %s[%d] -Invalid boot device(%s)\n",
619 name, lineno, token);
620 exit(EXIT_FAILURE);
621 }
01390aff
SB
622
623 /*
624 * The SOC loads from the storage starting at address 0
625 * then ensures that the load size contains the offset
626 */
627 if (imximage_init_loadsize < imximage_ivt_offset)
628 imximage_init_loadsize = imximage_ivt_offset;
8a1edd7d
LHR
629 if (unlikely(cmd_ver_first != 1))
630 cmd_ver_first = 0;
631 break;
6cb83829 632 case CMD_BOOT_OFFSET:
3150f92c 633 imximage_ivt_offset = get_cfg_value(token, name, lineno);
6cb83829
MV
634 if (unlikely(cmd_ver_first != 1))
635 cmd_ver_first = 0;
636 break;
0b7f7c33
AA
637 case CMD_WRITE_DATA:
638 case CMD_WRITE_CLR_BIT:
639 case CMD_CHECK_BITS_SET:
640 case CMD_CHECK_BITS_CLR:
8a1edd7d 641 value = get_cfg_value(token, name, lineno);
0b7f7c33
AA
642 if (set_dcd_param)
643 (*set_dcd_param)(imxhdr, dcd_len, cmd);
8a1edd7d
LHR
644 (*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
645 if (unlikely(cmd_ver_first != 1))
646 cmd_ver_first = 0;
647 break;
0187c985
SB
648 case CMD_CSF:
649 if (imximage_version != 2) {
650 fprintf(stderr,
651 "Error: %s[%d] - CSF only supported for VERSION 2(%s)\n",
652 name, lineno, token);
653 exit(EXIT_FAILURE);
654 }
655 imximage_csf_size = get_cfg_value(token, name, lineno);
656 if (unlikely(cmd_ver_first != 1))
657 cmd_ver_first = 0;
658 break;
b55e4f48
PF
659 case CMD_PLUGIN:
660 plugin_image = 1;
661 copy_plugin_code(imxhdr, token);
662 break;
8a1edd7d
LHR
663 }
664}
665
666static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
667 char *token, char *name, int lineno, int fld, int *dcd_len)
668{
669 int value;
670
671 switch (fld) {
672 case CFG_COMMAND:
673 *cmd = get_table_entry_id(imximage_cmds,
674 "imximage commands", token);
675 if (*cmd < 0) {
676 fprintf(stderr, "Error: %s[%d] - Invalid command"
677 "(%s)\n", name, lineno, token);
678 exit(EXIT_FAILURE);
679 }
680 break;
681 case CFG_REG_SIZE:
682 parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld, *dcd_len);
683 break;
684 case CFG_REG_ADDRESS:
685 case CFG_REG_VALUE:
0b7f7c33
AA
686 switch(*cmd) {
687 case CMD_WRITE_DATA:
688 case CMD_WRITE_CLR_BIT:
689 case CMD_CHECK_BITS_SET:
690 case CMD_CHECK_BITS_CLR:
691
692 value = get_cfg_value(token, name, lineno);
693 if (set_dcd_param)
694 (*set_dcd_param)(imxhdr, *dcd_len, *cmd);
695 (*set_dcd_val)(imxhdr, name, lineno, fld, value,
696 *dcd_len);
697
698 if (fld == CFG_REG_VALUE) {
699 (*dcd_len)++;
700 if (*dcd_len > max_dcd_entries) {
701 fprintf(stderr, "Error: %s[%d] -"
702 "DCD table exceeds maximum size(%d)\n",
703 name, lineno, max_dcd_entries);
704 exit(EXIT_FAILURE);
705 }
4d5fa985 706 }
0b7f7c33 707 break;
b55e4f48
PF
708 case CMD_PLUGIN:
709 value = get_cfg_value(token, name, lineno);
710 imximage_iram_free_start = value;
711 break;
0b7f7c33
AA
712 default:
713 break;
4d5fa985 714 }
8a1edd7d
LHR
715 break;
716 default:
717 break;
718 }
719}
720static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
8edcde5e
SB
721{
722 FILE *fd = NULL;
723 char *line = NULL;
724 char *token, *saveptr1, *saveptr2;
725 int lineno = 0;
8a1edd7d 726 int fld;
0ad22703 727 size_t len;
8edcde5e 728 int dcd_len = 0;
8edcde5e
SB
729 int32_t cmd;
730
731 fd = fopen(name, "r");
732 if (fd == 0) {
733 fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
734 exit(EXIT_FAILURE);
735 }
736
01390aff
SB
737 /*
738 * Very simple parsing, line starting with # are comments
8edcde5e
SB
739 * and are dropped
740 */
741 while ((getline(&line, &len, fd)) > 0) {
742 lineno++;
743
744 token = strtok_r(line, "\r\n", &saveptr1);
745 if (token == NULL)
746 continue;
747
748 /* Check inside the single line */
749 for (fld = CFG_COMMAND, cmd = CMD_INVALID,
750 line = token; ; line = NULL, fld++) {
751 token = strtok_r(line, " \t", &saveptr2);
752 if (token == NULL)
753 break;
754
755 /* Drop all text starting with '#' as comments */
756 if (token[0] == '#')
757 break;
758
8a1edd7d
LHR
759 parse_cfg_fld(imxhdr, &cmd, token, name,
760 lineno, fld, &dcd_len);
8edcde5e
SB
761 }
762
8edcde5e 763 }
8a1edd7d
LHR
764
765 (*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
8edcde5e
SB
766 fclose(fd);
767
8d8cc828 768 /* Exit if there is no BOOT_FROM field specifying the flash_offset */
3150f92c 769 if (imximage_ivt_offset == FLASH_OFFSET_UNDEFINED) {
8d8cc828
TK
770 fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
771 exit(EXIT_FAILURE);
772 }
5b28e913 773 return dcd_len;
8edcde5e
SB
774}
775
8edcde5e 776
8a1edd7d
LHR
777static int imximage_check_image_types(uint8_t type)
778{
779 if (type == IH_TYPE_IMXIMAGE)
780 return EXIT_SUCCESS;
781 else
782 return EXIT_FAILURE;
783}
8edcde5e 784
8a1edd7d 785static int imximage_verify_header(unsigned char *ptr, int image_size,
f86ed6a8 786 struct image_tool_params *params)
8a1edd7d
LHR
787{
788 struct imx_header *imx_hdr = (struct imx_header *) ptr;
8edcde5e 789
8a1edd7d
LHR
790 if (detect_imximage_version(imx_hdr) == IMXIMAGE_VER_INVALID)
791 return -FDT_ERR_BADSTRUCTURE;
8edcde5e 792
8a1edd7d
LHR
793 return 0;
794}
8edcde5e 795
8a1edd7d
LHR
796static void imximage_print_header(const void *ptr)
797{
798 struct imx_header *imx_hdr = (struct imx_header *) ptr;
799 uint32_t version = detect_imximage_version(imx_hdr);
800
801 switch (version) {
802 case IMXIMAGE_V1:
803 print_hdr_v1(imx_hdr);
804 break;
805 case IMXIMAGE_V2:
806 print_hdr_v2(imx_hdr);
807 break;
808 default:
809 err_imximage_version(version);
810 break;
811 }
812}
8edcde5e 813
8a1edd7d 814static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
f86ed6a8 815 struct image_tool_params *params)
8a1edd7d
LHR
816{
817 struct imx_header *imxhdr = (struct imx_header *)ptr;
818 uint32_t dcd_len;
b55e4f48 819 uint32_t header_size;
8edcde5e 820
8a1edd7d
LHR
821 /*
822 * In order to not change the old imx cfg file
823 * by adding VERSION command into it, here need
824 * set up function ptr group to V1 by default.
825 */
826 imximage_version = IMXIMAGE_V1;
49d3e272 827 /* Be able to detect if the cfg file has no BOOT_FROM tag */
3150f92c 828 imximage_ivt_offset = FLASH_OFFSET_UNDEFINED;
0187c985 829 imximage_csf_size = 0;
72048bc3 830 set_hdr_func();
8edcde5e 831
8a1edd7d
LHR
832 /* Parse dcd configuration file */
833 dcd_len = parse_cfg_file(imxhdr, params->imagename);
8edcde5e 834
97f17fa6
MK
835 if (imximage_version == IMXIMAGE_V1)
836 header_size = sizeof(flash_header_v1_t);
837 else {
b55e4f48
PF
838 header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
839 if (!plugin_image)
840 header_size += sizeof(dcd_v2_t);
841 else
842 header_size += MAX_PLUGIN_CODE_SIZE;
03ea24b2
YL
843 }
844
97f17fa6
MK
845 if (imximage_init_loadsize < imximage_ivt_offset + header_size)
846 imximage_init_loadsize = imximage_ivt_offset + header_size;
847
8a1edd7d 848 /* Set the imx header */
3150f92c 849 (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset);
1411fb37
FE
850
851 /*
852 * ROM bug alert
895d9966
MV
853 *
854 * MX53 only loads 512 byte multiples in case of SD boot.
855 * MX53 only loads NAND page multiples in case of NAND boot and
856 * supports up to 4096 byte large pages, thus align to 4096.
857 *
858 * The remaining fraction of a block bytes would not be loaded!
1411fb37 859 */
de979804 860 *header_size_ptr = ROUND((sbuf->st_size + imximage_ivt_offset), 4096);
0187c985
SB
861
862 if (csf_ptr && imximage_csf_size) {
863 *csf_ptr = params->ep - imximage_init_loadsize +
864 *header_size_ptr;
865 *header_size_ptr += imximage_csf_size;
866 }
8edcde5e
SB
867}
868
f86ed6a8 869int imximage_check_params(struct image_tool_params *params)
8edcde5e
SB
870{
871 if (!params)
872 return CFG_INVALID;
873 if (!strlen(params->imagename)) {
874 fprintf(stderr, "Error: %s - Configuration file not specified, "
875 "it is needed for imximage generation\n",
876 params->cmdname);
877 return CFG_INVALID;
878 }
879 /*
880 * Check parameters:
881 * XIP is not allowed and verify that incompatible
882 * parameters are not sent at the same time
883 * For example, if list is required a data image must not be provided
884 */
885 return (params->dflag && (params->fflag || params->lflag)) ||
886 (params->fflag && (params->dflag || params->lflag)) ||
887 (params->lflag && (params->dflag || params->fflag)) ||
888 (params->xflag) || !(strlen(params->imagename));
889}
890
f86ed6a8 891static int imximage_generate(struct image_tool_params *params,
01390aff
SB
892 struct image_type_params *tparams)
893{
894 struct imx_header *imxhdr;
895 size_t alloc_len;
896 struct stat sbuf;
897 char *datafile = params->datafile;
b55e4f48 898 uint32_t pad_len, header_size;
01390aff
SB
899
900 memset(&imximage_header, 0, sizeof(imximage_header));
901
902 /*
903 * In order to not change the old imx cfg file
904 * by adding VERSION command into it, here need
905 * set up function ptr group to V1 by default.
906 */
907 imximage_version = IMXIMAGE_V1;
908 /* Be able to detect if the cfg file has no BOOT_FROM tag */
909 imximage_ivt_offset = FLASH_OFFSET_UNDEFINED;
910 imximage_csf_size = 0;
72048bc3 911 set_hdr_func();
01390aff
SB
912
913 /* Parse dcd configuration file */
914 parse_cfg_file(&imximage_header, params->imagename);
915
97f17fa6
MK
916 if (imximage_version == IMXIMAGE_V1)
917 header_size = sizeof(imx_header_v1_t);
918 else {
b55e4f48
PF
919 header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
920 if (!plugin_image)
921 header_size += sizeof(dcd_v2_t);
922 else
923 header_size += MAX_PLUGIN_CODE_SIZE;
01390aff
SB
924 }
925
97f17fa6
MK
926 if (imximage_init_loadsize < imximage_ivt_offset + header_size)
927 imximage_init_loadsize = imximage_ivt_offset + header_size;
928
929 alloc_len = imximage_init_loadsize - imximage_ivt_offset;
930
b55e4f48 931 if (alloc_len < header_size) {
01390aff
SB
932 fprintf(stderr, "%s: header error\n",
933 params->cmdname);
934 exit(EXIT_FAILURE);
935 }
936
937 imxhdr = malloc(alloc_len);
938
939 if (!imxhdr) {
940 fprintf(stderr, "%s: malloc return failure: %s\n",
941 params->cmdname, strerror(errno));
942 exit(EXIT_FAILURE);
943 }
944
945 memset(imxhdr, 0, alloc_len);
946
947 tparams->header_size = alloc_len;
948 tparams->hdr = imxhdr;
949
950 /* determine data image file length */
951
952 if (stat(datafile, &sbuf) < 0) {
953 fprintf(stderr, "%s: Can't stat %s: %s\n",
954 params->cmdname, datafile, strerror(errno));
955 exit(EXIT_FAILURE);
956 }
957
958 pad_len = ROUND(sbuf.st_size, 4096) - sbuf.st_size;
959
97f17fa6 960 return pad_len;
01390aff
SB
961}
962
963
8edcde5e
SB
964/*
965 * imximage parameters
966 */
a93648d1
GMF
967U_BOOT_IMAGE_TYPE(
968 imximage,
969 "Freescale i.MX Boot Image support",
970 0,
971 NULL,
972 imximage_check_params,
973 imximage_verify_header,
974 imximage_print_header,
975 imximage_set_header,
976 NULL,
977 imximage_check_image_types,
978 NULL,
979 imximage_generate
980);