[people/ms/u-boot.git] / tools / imximage.h

/*
 * (C) Copyright 2009
 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _IMXIMAGE_H_
#define _IMXIMAGE_H_

#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
#define MAX_HW_CFG_SIZE_V1 60  /* Max number of registers imx can set for v1 */
#define APP_CODE_BARKER	0xB1
#define DCD_BARKER	0xB17219E9

/*
 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
 *       imx-common/imximage.cfg because tools/imximage.c can not
 *       cross-include headers from arch/arm/ and vice-versa.
 */
#define CMD_DATA_STR	"DATA"

/* Initial Vector Table Offset */
#define FLASH_OFFSET_UNDEFINED	0xFFFFFFFF
#define FLASH_OFFSET_STANDARD	0x400
#define FLASH_OFFSET_NAND	FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_SD		FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_SPI	FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_ONENAND	0x100
#define FLASH_OFFSET_NOR	0x1000
#define FLASH_OFFSET_SATA	FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_QSPI	0x1000

/* Initial Load Region Size */
#define FLASH_LOADSIZE_UNDEFINED	0xFFFFFFFF
#define FLASH_LOADSIZE_STANDARD		0x1000
#define FLASH_LOADSIZE_NAND		FLASH_LOADSIZE_STANDARD
#define FLASH_LOADSIZE_SD		FLASH_LOADSIZE_STANDARD
#define FLASH_LOADSIZE_SPI		FLASH_LOADSIZE_STANDARD
#define FLASH_LOADSIZE_ONENAND		0x400
#define FLASH_LOADSIZE_NOR		0x0 /* entire image */
#define FLASH_LOADSIZE_SATA		FLASH_LOADSIZE_STANDARD
#define FLASH_LOADSIZE_QSPI		0x0 /* entire image */

/* Command tags and parameters */
#define IVT_HEADER_TAG			0xD1
#define IVT_VERSION			0x40
#define DCD_HEADER_TAG			0xD2
#define DCD_VERSION			0x40
#define DCD_WRITE_DATA_COMMAND_TAG	0xCC
#define DCD_WRITE_DATA_PARAM		0x4
#define DCD_WRITE_CLR_BIT_PARAM	0xC
#define DCD_CHECK_DATA_COMMAND_TAG	0xCF
#define DCD_CHECK_BITS_SET_PARAM	0x14
#define DCD_CHECK_BITS_CLR_PARAM	0x04

enum imximage_cmd {
	CMD_INVALID,
	CMD_IMAGE_VERSION,
	CMD_BOOT_FROM,
	CMD_BOOT_OFFSET,
	CMD_WRITE_DATA,
	CMD_WRITE_CLR_BIT,
	CMD_CHECK_BITS_SET,
	CMD_CHECK_BITS_CLR,
	CMD_CSF,
};

enum imximage_fld_types {
	CFG_INVALID = -1,
	CFG_COMMAND,
	CFG_REG_SIZE,
	CFG_REG_ADDRESS,
	CFG_REG_VALUE
};

enum imximage_version {
	IMXIMAGE_VER_INVALID = -1,
	IMXIMAGE_V1 = 1,
	IMXIMAGE_V2
};

typedef struct {
	uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
	uint32_t addr; /* Address to write to */
	uint32_t value; /* Data to write */
} dcd_type_addr_data_t;

typedef struct {
	uint32_t barker; /* Barker for sanity check */
	uint32_t length; /* Device configuration length (without preamble) */
} dcd_preamble_t;

typedef struct {
	dcd_preamble_t preamble;
	dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
} dcd_v1_t;

typedef struct {
	uint32_t app_code_jump_vector;
	uint32_t app_code_barker;
	uint32_t app_code_csf;
	uint32_t dcd_ptr_ptr;
	uint32_t super_root_key;
	uint32_t dcd_ptr;
	uint32_t app_dest_ptr;
} flash_header_v1_t;

typedef struct {
	uint32_t length; 	/* Length of data to be read from flash */
} flash_cfg_parms_t;

typedef struct {
	flash_header_v1_t fhdr;
	dcd_v1_t dcd_table;
	flash_cfg_parms_t ext_header;
} imx_header_v1_t;

typedef struct {
	uint32_t addr;
	uint32_t value;
} dcd_addr_data_t;

typedef struct {
	uint8_t tag;
	uint16_t length;
	uint8_t version;
} __attribute__((packed)) ivt_header_t;

typedef struct {
	uint8_t tag;
	uint16_t length;
	uint8_t param;
} __attribute__((packed)) write_dcd_command_t;

struct dcd_v2_cmd {
	write_dcd_command_t write_dcd_command;
	dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
};

typedef struct {
	ivt_header_t header;
	struct dcd_v2_cmd dcd_cmd;
	uint32_t padding[1]; /* end up on an 8-byte boundary */
} dcd_v2_t;

typedef struct {
	uint32_t start;
	uint32_t size;
	uint32_t plugin;
} boot_data_t;

typedef struct {
	ivt_header_t header;
	uint32_t entry;
	uint32_t reserved1;
	uint32_t dcd_ptr;
	uint32_t boot_data_ptr;
	uint32_t self;
	uint32_t csf;
	uint32_t reserved2;
} flash_header_v2_t;

typedef struct {
	flash_header_v2_t fhdr;
	boot_data_t boot_data;
	dcd_v2_t dcd_table;
} imx_header_v2_t;

/* The header must be aligned to 4k on MX53 for NAND boot */
struct imx_header {
	union {
		imx_header_v1_t hdr_v1;
		imx_header_v2_t hdr_v2;
	} header;
};

typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
					char *name, int lineno,
					int fld, uint32_t value,
					uint32_t off);

typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len,
					int32_t cmd);

typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
					uint32_t dcd_len,
					char *name, int lineno);

typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
		uint32_t entry_point, uint32_t flash_offset);

#endif /* _IMXIMAGE_H_ */
Commit	Line	Data
8edcde5e SB	1	/*
	2	* (C) Copyright 2009
	3	* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
8edcde5e SB	6	*/
	7
	8	#ifndef _IMXIMAGE_H_
	9	#define _IMXIMAGE_H_
	10
021e79c8	11	#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
8a1edd7d	12	#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
8edcde5e SB	13	#define APP_CODE_BARKER 0xB1
8edcde5e SB	14	#define DCD_BARKER 0xB17219E9
8edcde5e	15
6cb83829 MV	16	/*
	17	* NOTE: This file must be kept in sync with arch/arm/include/asm/\
	18	* imx-common/imximage.cfg because tools/imximage.c can not
	19	* cross-include headers from arch/arm/ and vice-versa.
	20	*/
8edcde5e	21	#define CMD_DATA_STR "DATA"
377e367a SB	22
377e367a SB	23	/* Initial Vector Table Offset */
49d3e272	24	#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
8edcde5e SB	25	#define FLASH_OFFSET_STANDARD 0x400
	26	#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
	27	#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
	28	#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
	29	#define FLASH_OFFSET_ONENAND 0x100
19b409c0 DB	30	#define FLASH_OFFSET_NOR 0x1000
19b409c0 DB	31	#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
9598f8c3	32	#define FLASH_OFFSET_QSPI 0x1000
8edcde5e	33
377e367a SB	34	/* Initial Load Region Size */
	35	#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
	36	#define FLASH_LOADSIZE_STANDARD 0x1000
	37	#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
	38	#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
	39	#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
	40	#define FLASH_LOADSIZE_ONENAND 0x400
	41	#define FLASH_LOADSIZE_NOR 0x0 /* entire image */
	42	#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
9598f8c3	43	#define FLASH_LOADSIZE_QSPI 0x0 /* entire image */
377e367a	44
0b7f7c33 AA	45	/* Command tags and parameters */
	46	#define IVT_HEADER_TAG 0xD1
	47	#define IVT_VERSION 0x40
	48	#define DCD_HEADER_TAG 0xD2
	49	#define DCD_VERSION 0x40
	50	#define DCD_WRITE_DATA_COMMAND_TAG 0xCC
	51	#define DCD_WRITE_DATA_PARAM 0x4
	52	#define DCD_WRITE_CLR_BIT_PARAM 0xC
	53	#define DCD_CHECK_DATA_COMMAND_TAG 0xCF
	54	#define DCD_CHECK_BITS_SET_PARAM 0x14
	55	#define DCD_CHECK_BITS_CLR_PARAM 0x04
8a1edd7d	56
8edcde5e SB	57	enum imximage_cmd {
8edcde5e SB	58	CMD_INVALID,
8a1edd7d	59	CMD_IMAGE_VERSION,
8edcde5e	60	CMD_BOOT_FROM,
6cb83829	61	CMD_BOOT_OFFSET,
0b7f7c33 AA	62	CMD_WRITE_DATA,
	63	CMD_WRITE_CLR_BIT,
	64	CMD_CHECK_BITS_SET,
	65	CMD_CHECK_BITS_CLR,
0187c985	66	CMD_CSF,
8edcde5e SB	67	};
	68
	69	enum imximage_fld_types {
	70	CFG_INVALID = -1,
	71	CFG_COMMAND,
	72	CFG_REG_SIZE,
	73	CFG_REG_ADDRESS,
	74	CFG_REG_VALUE
	75	};
	76
8a1edd7d LHR	77	enum imximage_version {
	78	IMXIMAGE_VER_INVALID = -1,
	79	IMXIMAGE_V1 = 1,
	80	IMXIMAGE_V2
	81	};
8edcde5e SB	82
	83	typedef struct {
	84	uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
	85	uint32_t addr; /* Address to write to */
	86	uint32_t value; /* Data to write */
	87	} dcd_type_addr_data_t;
	88
	89	typedef struct {
	90	uint32_t barker; /* Barker for sanity check */
	91	uint32_t length; /* Device configuration length (without preamble) */
	92	} dcd_preamble_t;
	93
	94	typedef struct {
	95	dcd_preamble_t preamble;
8a1edd7d LHR	96	dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
8a1edd7d LHR	97	} dcd_v1_t;
8edcde5e SB	98
	99	typedef struct {
	100	uint32_t app_code_jump_vector;
	101	uint32_t app_code_barker;
	102	uint32_t app_code_csf;
	103	uint32_t dcd_ptr_ptr;
5b28e913	104	uint32_t super_root_key;
8edcde5e SB	105	uint32_t dcd_ptr;
8edcde5e SB	106	uint32_t app_dest_ptr;
8a1edd7d	107	} flash_header_v1_t;
8edcde5e SB	108
	109	typedef struct {
	110	uint32_t length; /* Length of data to be read from flash */
	111	} flash_cfg_parms_t;
	112
8a1edd7d LHR	113	typedef struct {
	114	flash_header_v1_t fhdr;
	115	dcd_v1_t dcd_table;
8edcde5e	116	flash_cfg_parms_t ext_header;
8a1edd7d LHR	117	} imx_header_v1_t;
	118
	119	typedef struct {
	120	uint32_t addr;
	121	uint32_t value;
	122	} dcd_addr_data_t;
	123
	124	typedef struct {
	125	uint8_t tag;
	126	uint16_t length;
	127	uint8_t version;
	128	} __attribute__((packed)) ivt_header_t;
	129
	130	typedef struct {
	131	uint8_t tag;
	132	uint16_t length;
	133	uint8_t param;
	134	} __attribute__((packed)) write_dcd_command_t;
	135
61903b75	136	struct dcd_v2_cmd {
8a1edd7d LHR	137	write_dcd_command_t write_dcd_command;
8a1edd7d LHR	138	dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
61903b75 TK	139	};
	140
	141	typedef struct {
	142	ivt_header_t header;
	143	struct dcd_v2_cmd dcd_cmd;
699279ca	144	uint32_t padding[1]; /* end up on an 8-byte boundary */
8a1edd7d LHR	145	} dcd_v2_t;
	146
	147	typedef struct {
	148	uint32_t start;
	149	uint32_t size;
	150	uint32_t plugin;
	151	} boot_data_t;
	152
	153	typedef struct {
	154	ivt_header_t header;
	155	uint32_t entry;
	156	uint32_t reserved1;
	157	uint32_t dcd_ptr;
	158	uint32_t boot_data_ptr;
	159	uint32_t self;
	160	uint32_t csf;
	161	uint32_t reserved2;
	162	} flash_header_v2_t;
	163
	164	typedef struct {
	165	flash_header_v2_t fhdr;
	166	boot_data_t boot_data;
	167	dcd_v2_t dcd_table;
	168	} imx_header_v2_t;
	169
895d9966	170	/* The header must be aligned to 4k on MX53 for NAND boot */
8a1edd7d LHR	171	struct imx_header {
	172	union {
	173	imx_header_v1_t hdr_v1;
	174	imx_header_v2_t hdr_v2;
	175	} header;
377e367a	176	};
8edcde5e	177
8a1edd7d LHR	178	typedef void (set_dcd_val_t)(struct imx_header imxhdr,
	179	char *name, int lineno,
	180	int fld, uint32_t value,
	181	uint32_t off);
	182
0b7f7c33 AA	183	typedef void (set_dcd_param_t)(struct imx_header imxhdr, uint32_t dcd_len,
	184	int32_t cmd);
	185
8a1edd7d LHR	186	typedef void (set_dcd_rst_t)(struct imx_header imxhdr,
	187	uint32_t dcd_len,
	188	char *name, int lineno);
	189
ad0826dc TK	190	typedef void (set_imx_hdr_t)(struct imx_header imxhdr, uint32_t dcd_len,
ad0826dc TK	191	uint32_t entry_point, uint32_t flash_offset);
8edcde5e SB	192
8edcde5e SB	193	#endif /* _IMXIMAGE_H_ */