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1 | /* | |
2 | * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> | |
3 | * | |
4 | * (C) Copyright 2007-2011 | |
5 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
6 | * Tom Cubie <tangliang@allwinnertech.com> | |
7 | * | |
8 | * Some init for sunxi platform. | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #include <common.h> | |
14 | #include <mmc.h> | |
15 | #include <i2c.h> | |
16 | #include <serial.h> | |
17 | #ifdef CONFIG_SPL_BUILD | |
18 | #include <spl.h> | |
19 | #endif | |
20 | #include <asm/gpio.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/arch/clock.h> | |
23 | #include <asm/arch/gpio.h> | |
24 | #include <asm/arch/spl.h> | |
25 | #include <asm/arch/sys_proto.h> | |
26 | #include <asm/arch/timer.h> | |
27 | #include <asm/arch/tzpc.h> | |
28 | #include <asm/arch/mmc.h> | |
29 | ||
30 | #include <linux/compiler.h> | |
31 | ||
32 | struct fel_stash { | |
33 | uint32_t sp; | |
34 | uint32_t lr; | |
35 | uint32_t cpsr; | |
36 | uint32_t sctlr; | |
37 | uint32_t vbar; | |
38 | uint32_t cr; | |
39 | }; | |
40 | ||
41 | struct fel_stash fel_stash __attribute__((section(".data"))); | |
42 | ||
43 | static int gpio_init(void) | |
44 | { | |
45 | #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) | |
46 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) | |
47 | /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ | |
48 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); | |
49 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); | |
50 | #endif | |
51 | #if defined(CONFIG_MACH_SUN8I) | |
52 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); | |
53 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); | |
54 | #else | |
55 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); | |
56 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); | |
57 | #endif | |
58 | sunxi_gpio_set_pull(SUNXI_GPF(4), 1); | |
59 | #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) | |
60 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); | |
61 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); | |
62 | sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); | |
63 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) | |
64 | sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); | |
65 | sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); | |
66 | sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); | |
67 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) | |
68 | sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); | |
69 | sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); | |
70 | sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); | |
71 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) | |
72 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); | |
73 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); | |
74 | sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); | |
75 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3) | |
76 | sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); | |
77 | sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); | |
78 | sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); | |
79 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) | |
80 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); | |
81 | sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); | |
82 | sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); | |
83 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) | |
84 | sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); | |
85 | sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); | |
86 | sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); | |
87 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) | |
88 | sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); | |
89 | sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); | |
90 | sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); | |
91 | #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) | |
92 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); | |
93 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); | |
94 | sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); | |
95 | #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) | |
96 | sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); | |
97 | sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); | |
98 | sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); | |
99 | #else | |
100 | #error Unsupported console port number. Please fix pin mux settings in board.c | |
101 | #endif | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | int spl_board_load_image(void) | |
107 | { | |
108 | debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); | |
109 | return_to_fel(fel_stash.sp, fel_stash.lr); | |
110 | ||
111 | return 0; | |
112 | } | |
113 | ||
114 | void s_init(void) | |
115 | { | |
116 | #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23 | |
117 | /* Magic (undocmented) value taken from boot0, without this DRAM | |
118 | * access gets messed up (seems cache related) */ | |
119 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); | |
120 | #endif | |
121 | #if defined CONFIG_MACH_SUN6I || \ | |
122 | defined CONFIG_MACH_SUN7I || \ | |
123 | defined CONFIG_MACH_SUN8I | |
124 | /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ | |
125 | asm volatile( | |
126 | "mrc p15, 0, r0, c1, c0, 1\n" | |
127 | "orr r0, r0, #1 << 6\n" | |
128 | "mcr p15, 0, r0, c1, c0, 1\n"); | |
129 | #endif | |
130 | #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 | |
131 | /* Enable non-secure access to some peripherals */ | |
132 | tzpc_init(); | |
133 | #endif | |
134 | ||
135 | clock_init(); | |
136 | timer_init(); | |
137 | gpio_init(); | |
138 | i2c_init_board(); | |
139 | } | |
140 | ||
141 | #ifdef CONFIG_SPL_BUILD | |
142 | DECLARE_GLOBAL_DATA_PTR; | |
143 | ||
144 | /* The sunxi internal brom will try to loader external bootloader | |
145 | * from mmc0, nand flash, mmc2. | |
146 | */ | |
147 | u32 spl_boot_device(void) | |
148 | { | |
149 | __maybe_unused struct mmc *mmc0, *mmc1; | |
150 | /* | |
151 | * When booting from the SD card or NAND memory, the "eGON.BT0" | |
152 | * signature is expected to be found in memory at the address 0x0004 | |
153 | * (see the "mksunxiboot" tool, which generates this header). | |
154 | * | |
155 | * When booting in the FEL mode over USB, this signature is patched in | |
156 | * memory and replaced with something else by the 'fel' tool. This other | |
157 | * signature is selected in such a way, that it can't be present in a | |
158 | * valid bootable SD card image (because the BROM would refuse to | |
159 | * execute the SPL in this case). | |
160 | * | |
161 | * This checks for the signature and if it is not found returns to | |
162 | * the FEL code in the BROM to wait and receive the main u-boot | |
163 | * binary over USB. If it is found, it determines where SPL was | |
164 | * read from. | |
165 | */ | |
166 | if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ | |
167 | return BOOT_DEVICE_BOARD; | |
168 | ||
169 | /* The BROM will try to boot from mmc0 first, so try that first. */ | |
170 | #ifdef CONFIG_MMC | |
171 | mmc_initialize(gd->bd); | |
172 | mmc0 = find_mmc_device(0); | |
173 | if (sunxi_mmc_has_egon_boot_signature(mmc0)) | |
174 | return BOOT_DEVICE_MMC1; | |
175 | #endif | |
176 | ||
177 | /* Fallback to booting NAND if enabled. */ | |
178 | if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT)) | |
179 | return BOOT_DEVICE_NAND; | |
180 | ||
181 | #ifdef CONFIG_MMC | |
182 | if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) { | |
183 | mmc1 = find_mmc_device(1); | |
184 | if (sunxi_mmc_has_egon_boot_signature(mmc1)) | |
185 | return BOOT_DEVICE_MMC2; | |
186 | } | |
187 | #endif | |
188 | ||
189 | panic("Could not determine boot source\n"); | |
190 | return -1; /* Never reached */ | |
191 | } | |
192 | ||
193 | /* No confirmation data available in SPL yet. Hardcode bootmode */ | |
194 | u32 spl_boot_mode(void) | |
195 | { | |
196 | return MMCSD_MODE_RAW; | |
197 | } | |
198 | ||
199 | void board_init_f(ulong dummy) | |
200 | { | |
201 | spl_init(); | |
202 | preloader_console_init(); | |
203 | ||
204 | #ifdef CONFIG_SPL_I2C_SUPPORT | |
205 | /* Needed early by sunxi_board_init if PMU is enabled */ | |
206 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
207 | #endif | |
208 | sunxi_board_init(); | |
209 | } | |
210 | #endif | |
211 | ||
212 | void reset_cpu(ulong addr) | |
213 | { | |
214 | #ifdef CONFIG_SUNXI_GEN_SUN4I | |
215 | static const struct sunxi_wdog *wdog = | |
216 | &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; | |
217 | ||
218 | /* Set the watchdog for its shortest interval (.5s) and wait */ | |
219 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); | |
220 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); | |
221 | ||
222 | while (1) { | |
223 | /* sun5i sometimes gets stuck without this */ | |
224 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); | |
225 | } | |
226 | #endif | |
227 | #ifdef CONFIG_SUNXI_GEN_SUN6I | |
228 | static const struct sunxi_wdog *wdog = | |
229 | ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; | |
230 | ||
231 | /* Set the watchdog for its shortest interval (.5s) and wait */ | |
232 | writel(WDT_CFG_RESET, &wdog->cfg); | |
233 | writel(WDT_MODE_EN, &wdog->mode); | |
234 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); | |
235 | while (1) { } | |
236 | #endif | |
237 | } | |
238 | ||
239 | #ifndef CONFIG_SYS_DCACHE_OFF | |
240 | void enable_caches(void) | |
241 | { | |
242 | /* Enable D-cache. I-cache is already enabled in start.S */ | |
243 | dcache_enable(); | |
244 | } | |
245 | #endif | |
246 | ||
247 | #ifdef CONFIG_CMD_NET | |
248 | /* | |
249 | * Initializes on-chip ethernet controllers. | |
250 | * to override, implement board_eth_init() | |
251 | */ | |
252 | int cpu_eth_init(bd_t *bis) | |
253 | { | |
254 | __maybe_unused int rc; | |
255 | ||
256 | #ifdef CONFIG_MACPWR | |
257 | gpio_request(CONFIG_MACPWR, "macpwr"); | |
258 | gpio_direction_output(CONFIG_MACPWR, 1); | |
259 | mdelay(200); | |
260 | #endif | |
261 | ||
262 | #ifdef CONFIG_SUNXI_GMAC | |
263 | rc = sunxi_gmac_initialize(bis); | |
264 | if (rc < 0) { | |
265 | printf("sunxi: failed to initialize gmac\n"); | |
266 | return rc; | |
267 | } | |
268 | #endif | |
269 | ||
270 | return 0; | |
271 | } | |
272 | #endif |