| | 1 | /* |
| | 2 | * (C) Copyright 2001, 2002 |
| | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| | 4 | * |
| | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| | 6 | */ |
| | 7 | |
| | 8 | /* |
| | 9 | * board/config.h - configuration options, board specific |
| | 10 | */ |
| | 11 | |
| | 12 | #ifndef __CONFIG_H |
| | 13 | #define __CONFIG_H |
| | 14 | |
| | 15 | /*********************************************************** |
| | 16 | * High Level Configuration Options |
| | 17 | * (easy to change) |
| | 18 | ***********************************************************/ |
| | 19 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
| | 20 | |
| | 21 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
| | 22 | |
| | 23 | /*********************************************************** |
| | 24 | * Note that it may also be a MIP405T board which is a subset of the |
| | 25 | * MIP405 |
| | 26 | ***********************************************************/ |
| | 27 | /*********************************************************** |
| | 28 | * WARNING: |
| | 29 | * CONFIG_BOOT_PCI is only used for first boot-up and should |
| | 30 | * NOT be enabled for production bootloader |
| | 31 | ***********************************************************/ |
| | 32 | /*#define CONFIG_BOOT_PCI 1*/ |
| | 33 | /*********************************************************** |
| | 34 | * Clock |
| | 35 | ***********************************************************/ |
| | 36 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
| | 37 | |
| | 38 | /* |
| | 39 | * BOOTP options |
| | 40 | */ |
| | 41 | #define CONFIG_BOOTP_BOOTFILESIZE |
| | 42 | #define CONFIG_BOOTP_BOOTPATH |
| | 43 | #define CONFIG_BOOTP_GATEWAY |
| | 44 | #define CONFIG_BOOTP_HOSTNAME |
| | 45 | |
| | 46 | /* |
| | 47 | * Command line configuration. |
| | 48 | */ |
| | 49 | #define CONFIG_CMD_IRQ |
| | 50 | #define CONFIG_CMD_PCI |
| | 51 | #define CONFIG_CMD_REGINFO |
| | 52 | #define CONFIG_CMD_SAVES |
| | 53 | |
| | 54 | /************************************************************** |
| | 55 | * I2C Stuff: |
| | 56 | * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address |
| | 57 | * 0x53. |
| | 58 | * The Atmel EEPROM uses 16Bit addressing. |
| | 59 | ***************************************************************/ |
| | 60 | |
| | 61 | #define CONFIG_SYS_I2C |
| | 62 | #define CONFIG_SYS_I2C_PPC4XX |
| | 63 | #define CONFIG_SYS_I2C_PPC4XX_CH0 |
| | 64 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000 |
| | 65 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
| | 66 | |
| | 67 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ |
| | 68 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
| | 69 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
| | 70 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
| | 71 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ |
| | 72 | /* 64 byte page write mode using*/ |
| | 73 | /* last 6 bits of the address */ |
| | 74 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
| | 75 | |
| | 76 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
| | 77 | #define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ |
| | 78 | #define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ |
| | 79 | |
| | 80 | /*************************************************************** |
| | 81 | * Definitions for Serial Presence Detect EEPROM address |
| | 82 | * (to get SDRAM settings) |
| | 83 | ***************************************************************/ |
| | 84 | /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 |
| | 85 | #define SDRAM_EEPROM_READ_ADDRESS 0xA1 |
| | 86 | */ |
| | 87 | /************************************************************** |
| | 88 | * Environment definitions |
| | 89 | **************************************************************/ |
| | 90 | /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ |
| | 91 | /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ |
| | 92 | |
| | 93 | #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ |
| | 94 | #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ |
| | 95 | |
| | 96 | #define CONFIG_IPADDR 10.0.0.100 |
| | 97 | #define CONFIG_SERVERIP 10.0.0.1 |
| | 98 | #define CONFIG_PREBOOT |
| | 99 | /*************************************************************** |
| | 100 | * defines if an overwrite_console function exists |
| | 101 | *************************************************************/ |
| | 102 | /*************************************************************** |
| | 103 | * defines if the overwrite_console should be stored in the |
| | 104 | * environment |
| | 105 | **************************************************************/ |
| | 106 | |
| | 107 | /************************************************************** |
| | 108 | * loads config |
| | 109 | *************************************************************/ |
| | 110 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| | 111 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| | 112 | |
| | 113 | #define CONFIG_MISC_INIT_R |
| | 114 | /*********************************************************** |
| | 115 | * Miscellaneous configurable options |
| | 116 | **********************************************************/ |
| | 117 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| | 118 | #if defined(CONFIG_CMD_KGDB) |
| | 119 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| | 120 | #else |
| | 121 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| | 122 | #endif |
| | 123 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| | 124 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| | 125 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| | 126 | |
| | 127 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
| | 128 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ |
| | 129 | |
| | 130 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| | 131 | #define CONFIG_SYS_NS16550_SERIAL |
| | 132 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| | 133 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
| | 134 | |
| | 135 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
| | 136 | #define CONFIG_SYS_BASE_BAUD 916667 |
| | 137 | |
| | 138 | /* The following table includes the supported baudrates */ |
| | 139 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| | 140 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
| | 141 | 57600, 115200, 230400, 460800, 921600 } |
| | 142 | |
| | 143 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
| | 144 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
| | 145 | |
| | 146 | /*----------------------------------------------------------------------- |
| | 147 | * PCI stuff |
| | 148 | *----------------------------------------------------------------------- |
| | 149 | */ |
| | 150 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
| | 151 | #define PCI_HOST_FORCE 1 /* configure as pci host */ |
| | 152 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
| | 153 | |
| | 154 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
| | 155 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ |
| | 156 | /* resource configuration */ |
| | 157 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
| | 158 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ |
| | 159 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ |
| | 160 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
| | 161 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| | 162 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ |
| | 163 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ |
| | 164 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ |
| | 165 | |
| | 166 | /*----------------------------------------------------------------------- |
| | 167 | * Start addresses for the final memory configuration |
| | 168 | * (Set up by the startup code) |
| | 169 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| | 170 | */ |
| | 171 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| | 172 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 |
| | 173 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| | 174 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ |
| | 175 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ |
| | 176 | |
| | 177 | /* |
| | 178 | * For booting Linux, the board info and command line data |
| | 179 | * have to be in the first 8 MB of memory, since this is |
| | 180 | * the maximum mapped by the Linux kernel during initialization. |
| | 181 | */ |
| | 182 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| | 183 | /*----------------------------------------------------------------------- |
| | 184 | * FLASH organization |
| | 185 | */ |
| | 186 | #define CONFIG_SYS_UPDATE_FLASH_SIZE |
| | 187 | #define CONFIG_SYS_FLASH_PROTECTION |
| | 188 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| | 189 | |
| | 190 | #define CONFIG_SYS_FLASH_CFI |
| | 191 | #define CONFIG_FLASH_CFI_DRIVER |
| | 192 | |
| | 193 | #define CONFIG_FLASH_SHOW_PROGRESS 45 |
| | 194 | |
| | 195 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| | 196 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| | 197 | |
| | 198 | /* |
| | 199 | * JFFS2 partitions |
| | 200 | * |
| | 201 | */ |
| | 202 | /* No command line, one static partition, whole device */ |
| | 203 | #undef CONFIG_CMD_MTDPARTS |
| | 204 | #define CONFIG_JFFS2_DEV "nor0" |
| | 205 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF |
| | 206 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 |
| | 207 | |
| | 208 | /* mtdparts command line support */ |
| | 209 | /* Note: fake mtd_id used, no linux mtd map file */ |
| | 210 | /* |
| | 211 | #define CONFIG_CMD_MTDPARTS |
| | 212 | #define MTDIDS_DEFAULT "nor0=mip405-0" |
| | 213 | #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" |
| | 214 | */ |
| | 215 | |
| | 216 | /*----------------------------------------------------------------------- |
| | 217 | * Logbuffer Configuration |
| | 218 | */ |
| | 219 | #undef CONFIG_LOGBUFFER /* supported but not enabled */ |
| | 220 | /*----------------------------------------------------------------------- |
| | 221 | * Bootcountlimit Configuration |
| | 222 | */ |
| | 223 | #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */ |
| | 224 | |
| | 225 | /*----------------------------------------------------------------------- |
| | 226 | * POST Configuration |
| | 227 | */ |
| | 228 | #if 0 /* enable this if POST is desired (is supported but not enabled) */ |
| | 229 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
| | 230 | CONFIG_SYS_POST_CPU | \ |
| | 231 | CONFIG_SYS_POST_RTC | \ |
| | 232 | CONFIG_SYS_POST_I2C) |
| | 233 | |
| | 234 | #endif |
| | 235 | /* |
| | 236 | * Init Memory Controller: |
| | 237 | */ |
| | 238 | #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ |
| | 239 | #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ |
| | 240 | /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ |
| | 241 | #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ |
| | 242 | |
| | 243 | #define CONFIG_BOARD_EARLY_INIT_R |
| | 244 | |
| | 245 | /* Peripheral Bus Mapping */ |
| | 246 | #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ |
| | 247 | #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/ |
| | 248 | #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ |
| | 249 | |
| | 250 | #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 |
| | 251 | #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 |
| | 252 | |
| | 253 | /*----------------------------------------------------------------------- |
| | 254 | * Definitions for initial stack pointer and data area (in On Chip SRAM) |
| | 255 | */ |
| | 256 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
| | 257 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 |
| | 258 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
| | 259 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ |
| | 260 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ |
| | 261 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| | 262 | /* reserve some memory for POST and BOOT limit info */ |
| | 263 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) |
| | 264 | |
| | 265 | #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ |
| | 266 | #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12) |
| | 267 | #endif |
| | 268 | |
| | 269 | /*********************************************************************** |
| | 270 | * External peripheral base address |
| | 271 | ***********************************************************************/ |
| | 272 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 |
| | 273 | |
| | 274 | /*********************************************************************** |
| | 275 | * Last Stage Init |
| | 276 | ***********************************************************************/ |
| | 277 | #define CONFIG_LAST_STAGE_INIT |
| | 278 | /************************************************************ |
| | 279 | * Ethernet Stuff |
| | 280 | ***********************************************************/ |
| | 281 | #define CONFIG_PPC4xx_EMAC |
| | 282 | #define CONFIG_MII 1 /* MII PHY management */ |
| | 283 | #define CONFIG_PHY_ADDR 1 /* PHY address */ |
| | 284 | #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ |
| | 285 | #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ |
| | 286 | /************************************************************ |
| | 287 | * RTC |
| | 288 | ***********************************************************/ |
| | 289 | #define CONFIG_RTC_MC146818 |
| | 290 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| | 291 | |
| | 292 | /************************************************************ |
| | 293 | * IDE/ATA stuff |
| | 294 | ************************************************************/ |
| | 295 | #if defined(CONFIG_TARGET_MIP405T) |
| | 296 | #define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ |
| | 297 | #else |
| | 298 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
| | 299 | #endif |
| | 300 | |
| | 301 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ |
| | 302 | |
| | 303 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */ |
| | 304 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ |
| | 305 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ |
| | 306 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ |
| | 307 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ |
| | 308 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ |
| | 309 | |
| | 310 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
| | 311 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
| | 312 | #define CONFIG_IDE_RESET /* reset for ide supported... */ |
| | 313 | #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ |
| | 314 | #define CONFIG_SUPPORT_VFAT |
| | 315 | /************************************************************ |
| | 316 | * ATAPI support (experimental) |
| | 317 | ************************************************************/ |
| | 318 | #define CONFIG_ATAPI /* enable ATAPI Support */ |
| | 319 | |
| | 320 | /************************************************************ |
| | 321 | * DISK Partition support |
| | 322 | ************************************************************/ |
| | 323 | |
| | 324 | /************************************************************ |
| | 325 | * Video support |
| | 326 | ************************************************************/ |
| | 327 | #define CONFIG_VIDEO_LOGO |
| | 328 | #undef CONFIG_VIDEO_ONBOARD |
| | 329 | /************************************************************ |
| | 330 | * USB support EXPERIMENTAL |
| | 331 | ************************************************************/ |
| | 332 | #if !defined(CONFIG_TARGET_MIP405T) |
| | 333 | #define CONFIG_USB_UHCI |
| | 334 | |
| | 335 | /* Enable needed helper functions */ |
| | 336 | #endif |
| | 337 | /************************************************************ |
| | 338 | * Debug support |
| | 339 | ************************************************************/ |
| | 340 | #if defined(CONFIG_CMD_KGDB) |
| | 341 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| | 342 | #endif |
| | 343 | |
| | 344 | /************************************************************ |
| | 345 | * support BZIP2 compression |
| | 346 | ************************************************************/ |
| | 347 | #define CONFIG_BZIP2 1 |
| | 348 | |
| | 349 | #endif /* __CONFIG_H */ |
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