[people/ms/u-boot.git] / include / configs / MPC8315ERDB.h

/*
 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
 *
 * Dave Liu <daveliu@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFE000000
#endif

#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */
#define CONFIG_MPC831x		1 /* MPC831x CPU family */
#define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
#define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */

/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN	66666667 /* in Hz */
#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN

/*
 * Hardware Reset Configuration Word
 * if CLKIN is 66.66MHz, then
 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
 */
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_SVCOD_DIV_2 |\
	HRCWL_CSB_TO_CLKIN_2X1 |\
	HRCWL_CORE_TO_CSB_3X1)
#define CONFIG_SYS_HRCW_HIGH_BASE (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_TSEC1M_IN_RGMII |\
	HRCWH_TSEC2M_IN_RGMII |\
	HRCWH_BIG_ENDIAN |\
	HRCWH_LALE_NORMAL)

#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
		       HRCWH_FROM_0XFFF00100 |\
		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
		       HRCWH_RL_EXT_NAND)
#else
#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
		       HRCWH_FROM_0X00000100 |\
		       HRCWH_ROM_LOC_LOCAL_16BIT |\
		       HRCWH_RL_EXT_LEGACY)
#endif

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH		0x00000000
#define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */

#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_HWCONFIG

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * Arbiter Setup
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_LOZ \
				| DDRCDR_NZ_LOZ \
				| DDRCDR_ODT \
				| DDRCDR_Q_DRN)
				/* 0x7b880001 */
/*
 * Manually set up DDR parameters
 * consist of two chips HY5PS12621BFP-C4 from HYNIX
 */
#define CONFIG_SYS_DDR_SIZE		128 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ODT_RD_NEVER \
				| CSCONFIG_ODT_WR_ONLY_CURRENT \
				| CSCONFIG_ROW_BIT_13 \
				| CSCONFIG_COL_BIT_10)
				/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (6 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (4 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_32)
				/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2	0x00000000

/*
 * Memory test
 */
#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00140000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00040000
#define CONFIG_FSL_ELBC		1

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */

					/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)

#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
					| BR_PS_16	/* 16 bit port */ \
					| BR_MS_GPCM	/* MSEL = GPCM */ \
					| BR_V)		/* valid */
#define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
					| OR_UPM_XAM \
					| OR_GPCM_CSNT \
					| OR_GPCM_ACS_DIV2 \
					| OR_GPCM_XACS \
					| OR_GPCM_SCY_15 \
					| OR_GPCM_TRLX_SET \
					| OR_GPCM_EHTR_SET \
					| OR_GPCM_EAD)

#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT	135

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */

/*
 * NAND Flash on the Local Bus
 */

#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE		0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE		0xE0600000
#endif

#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITION
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT			"nand0=e0600000.flash"
#define MTDPARTS_DEFAULT		\
	"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_CMD_NAND			1
#define CONFIG_NAND_FSL_ELBC		1
#define CONFIG_SYS_NAND_BLOCK_SIZE	16384
#define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */

#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000

#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
				| BR_PS_8		/* 8 bit port */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V)			/* valid */
#define CONFIG_SYS_NAND_OR_PRELIM	\
				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
				| OR_FCM_CSCT \
				| OR_FCM_CST \
				| OR_FCM_CHT \
				| OR_FCM_SCY_1 \
				| OR_FCM_TRLX \
				| OR_FCM_EHTR)
				/* 0xFFFF8396 */

#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM

#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
	!defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/* Pass open firmware flat tree */
#define CONFIG_OF_BOARD_SETUP	1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

/*
 * Board info - revision and where boot from
 */
#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
#define CONFIG_SYS_PCI_IO_BASE		0x00000000
#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */

#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000

#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

#define CONFIG_SYS_PCIE2_BASE		0xC0000000
#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000

#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE

#define CONFIG_PCI_PNP		/* do pci plug-and-play */

#define CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */

#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_SYS_SCCR_USBDRCM		3

#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_PHY_TYPE	"utmi"
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_MII		1 /* MII PHY management */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC1"

/*
 * SATA
 */
#define CONFIG_LIBATA
#define CONFIG_FSL_SATA

#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET	0x18000
#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2_OFFSET	0x19000
#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA

#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#endif

/*
 * Environment
 */
#if !defined(CONFIG_SYS_RAMBOOT)
	#define CONFIG_ENV_IS_IN_FLASH	1
	#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
	#define CONFIG_ENV_SIZE		0x2000
#else
	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */

#if defined(CONFIG_CMD_KGDB)
	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
#else
	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
#endif

				/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
				/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE | \
				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * MMU Setup
 */
#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_128M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
				| BATU_BL_8M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
				| BATU_BL_32M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATU_BL_128K \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U

/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U

#define CONFIG_SYS_IBAT6L	0
#define CONFIG_SYS_IBAT6U	0
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U

#define CONFIG_SYS_IBAT7L	0
#define CONFIG_SYS_IBAT7U	0
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_BAUDRATE 115200

#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
#undef CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS0\0"						\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=ramfs.83xx\0"					\
	"fdtaddr=780000\0"						\
	"fdtfile=mpc8315erdb.dtb\0"					\
	"usb_phy_type=utmi\0"						\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"


#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
	1	/*
	2	* Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
	3	*
	4	* Dave Liu <daveliu@freescale.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#define CONFIG_DISPLAY_BOARDINFO
	13
	14	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
	15	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
	16	#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
	17	#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
	18	#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
	19
	20	#ifndef CONFIG_SYS_TEXT_BASE
	21	#define CONFIG_SYS_TEXT_BASE 0xFE000000
	22	#endif
	23
	24	#ifndef CONFIG_SYS_MONITOR_BASE
	25	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	26	#endif
	27
	28	/*
	29	* High Level Configuration Options
	30	*/
	31	#define CONFIG_E300 1 /* E300 family */
	32	#define CONFIG_MPC831x 1 /* MPC831x CPU family */
	33	#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
	34	#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
	35
	36	/*
	37	* System Clock Setup
	38	*/
	39	#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
	40	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	41
	42	/*
	43	* Hardware Reset Configuration Word
	44	* if CLKIN is 66.66MHz, then
	45	* CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
	46	*/
	47	#define CONFIG_SYS_HRCW_LOW (\
	48	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	49	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	50	HRCWL_SVCOD_DIV_2 \|\
	51	HRCWL_CSB_TO_CLKIN_2X1 \|\
	52	HRCWL_CORE_TO_CSB_3X1)
	53	#define CONFIG_SYS_HRCW_HIGH_BASE (\
	54	HRCWH_PCI_HOST \|\
	55	HRCWH_PCI1_ARBITER_ENABLE \|\
	56	HRCWH_CORE_ENABLE \|\
	57	HRCWH_BOOTSEQ_DISABLE \|\
	58	HRCWH_SW_WATCHDOG_DISABLE \|\
	59	HRCWH_TSEC1M_IN_RGMII \|\
	60	HRCWH_TSEC2M_IN_RGMII \|\
	61	HRCWH_BIG_ENDIAN \|\
	62	HRCWH_LALE_NORMAL)
	63
	64	#ifdef CONFIG_NAND_SPL
	65	#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \|\
	66	HRCWH_FROM_0XFFF00100 \|\
	67	HRCWH_ROM_LOC_NAND_SP_8BIT \|\
	68	HRCWH_RL_EXT_NAND)
	69	#else
	70	#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \|\
	71	HRCWH_FROM_0X00000100 \|\
	72	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	73	HRCWH_RL_EXT_LEGACY)
	74	#endif
	75
	76	/*
	77	* System IO Config
	78	*/
	79	#define CONFIG_SYS_SICRH 0x00000000
	80	#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
	81
	82	#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
	83	#define CONFIG_HWCONFIG
	84
	85	/*
	86	* IMMR new address
	87	*/
	88	#define CONFIG_SYS_IMMR 0xE0000000
	89
	90	/*
	91	* Arbiter Setup
	92	*/
	93	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
	94	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
	95	#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
	96
	97	/*
	98	* DDR Setup
	99	*/
	100	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
	101	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	102	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	103	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
	104	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
	105	\| DDRCDR_PZ_LOZ \
	106	\| DDRCDR_NZ_LOZ \
	107	\| DDRCDR_ODT \
	108	\| DDRCDR_Q_DRN)
	109	/* 0x7b880001 */
	110	/*
	111	* Manually set up DDR parameters
	112	* consist of two chips HY5PS12621BFP-C4 from HYNIX
	113	*/
	114	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
	115	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
	116	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
	117	\| CSCONFIG_ODT_RD_NEVER \
	118	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
	119	\| CSCONFIG_ROW_BIT_13 \
	120	\| CSCONFIG_COL_BIT_10)
	121	/* 0x80010102 */
	122	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
	123	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	124	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	125	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	126	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	127	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	128	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	129	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	130	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
	131	/* 0x00220802 */
	132	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	133	\| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	134	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	135	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	136	\| (6 << TIMING_CFG1_REFREC_SHIFT) \
	137	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	138	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	139	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
	140	/* 0x27256222 */
	141	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
	142	\| (4 << TIMING_CFG2_CPO_SHIFT) \
	143	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	144	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	145	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	146	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	147	\| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
	148	/* 0x121048c5 */
	149	#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
	150	\| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
	151	/* 0x03600100 */
	152	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
	153	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
	154	\| SDRAM_CFG_DBW_32)
	155	/* 0x43080000 */
	156	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
	157	#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
	158	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
	159	/* ODT 150ohm CL=3, AL=1 on SDRAM */
	160	#define CONFIG_SYS_DDR_MODE2 0x00000000
	161
	162	/*
	163	* Memory test
	164	*/
	165	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	166	#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
	167	#define CONFIG_SYS_MEMTEST_END 0x00140000
	168
	169	/*
	170	* The reserved memory
	171	*/
	172	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
	173	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
	174
	175	/*
	176	* Initial RAM Base Address Setup
	177	*/
	178	#define CONFIG_SYS_INIT_RAM_LOCK 1
	179	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	180	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
	181	#define CONFIG_SYS_GBL_DATA_OFFSET \
	182	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	183
	184	/*
	185	* Local Bus Configuration & Clock Setup
	186	*/
	187	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
	188	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
	189	#define CONFIG_SYS_LBC_LBCR 0x00040000
	190	#define CONFIG_FSL_ELBC 1
	191
	192	/*
	193	* FLASH on the Local Bus
	194	*/
	195	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
	196	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
	197	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	198
	199	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
	200	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
	201	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
	202
	203	/* Window base at flash base */
	204	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
	205	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_8MB)
	206
	207	#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
	208	\| BR_PS_16 /* 16 bit port */ \
	209	\| BR_MS_GPCM /* MSEL = GPCM */ \
	210	\| BR_V) /* valid */
	211	#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
	212	\| OR_UPM_XAM \
	213	\| OR_GPCM_CSNT \
	214	\| OR_GPCM_ACS_DIV2 \
	215	\| OR_GPCM_XACS \
	216	\| OR_GPCM_SCY_15 \
	217	\| OR_GPCM_TRLX_SET \
	218	\| OR_GPCM_EHTR_SET \
	219	\| OR_GPCM_EAD)
	220
	221	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	222	/* 127 64KB sectors and 8 8KB top sectors per device */
	223	#define CONFIG_SYS_MAX_FLASH_SECT 135
	224
	225	#undef CONFIG_SYS_FLASH_CHECKSUM
	226	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	227	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	228
	229	/*
	230	* NAND Flash on the Local Bus
	231	*/
	232
	233	#ifdef CONFIG_NAND_SPL
	234	#define CONFIG_SYS_NAND_BASE 0xFFF00000
	235	#else
	236	#define CONFIG_SYS_NAND_BASE 0xE0600000
	237	#endif
	238
	239	#define CONFIG_MTD_DEVICE
	240	#define CONFIG_MTD_PARTITION
	241	#define CONFIG_CMD_MTDPARTS
	242	#define MTDIDS_DEFAULT "nand0=e0600000.flash"
	243	#define MTDPARTS_DEFAULT \
	244	"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
	245
	246	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	247	#define CONFIG_CMD_NAND 1
	248	#define CONFIG_NAND_FSL_ELBC 1
	249	#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
	250	#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
	251
	252	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
	253	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
	254	#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
	255	#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
	256	#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
	257
	258	#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
	259	\| BR_DECC_CHK_GEN /* Use HW ECC */ \
	260	\| BR_PS_8 /* 8 bit port */ \
	261	\| BR_MS_FCM /* MSEL = FCM */ \
	262	\| BR_V) /* valid */
	263	#define CONFIG_SYS_NAND_OR_PRELIM \
	264	(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
	265	\| OR_FCM_CSCT \
	266	\| OR_FCM_CST \
	267	\| OR_FCM_CHT \
	268	\| OR_FCM_SCY_1 \
	269	\| OR_FCM_TRLX \
	270	\| OR_FCM_EHTR)
	271	/* 0xFFFF8396 */
	272
	273	#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
	274	#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
	275	#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
	276	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
	277
	278	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
	279	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
	280
	281	#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
	282	#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
	283
	284	#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
	285	!defined(CONFIG_NAND_SPL)
	286	#define CONFIG_SYS_RAMBOOT
	287	#else
	288	#undef CONFIG_SYS_RAMBOOT
	289	#endif
	290
	291	/*
	292	* Serial Port
	293	*/
	294	#define CONFIG_CONS_INDEX 1
	295	#define CONFIG_SYS_NS16550_SERIAL
	296	#define CONFIG_SYS_NS16550_REG_SIZE 1
	297	#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
	298
	299	#define CONFIG_SYS_BAUDRATE_TABLE \
	300	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	301
	302	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
	303	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
	304
	305	/* Use the HUSH parser */
	306	#define CONFIG_SYS_HUSH_PARSER
	307
	308	/* Pass open firmware flat tree */
	309	#define CONFIG_OF_BOARD_SETUP 1
	310	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	311
	312	/* I2C */
	313	#define CONFIG_SYS_I2C
	314	#define CONFIG_SYS_I2C_FSL
	315	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	316	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	317	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	318	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
	319
	320	/*
	321	* Board info - revision and where boot from
	322	*/
	323	#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
	324
	325	/*
	326	* Config on-board RTC
	327	*/
	328	#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
	329	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	330
	331	/*
	332	* General PCI
	333	* Addresses are mapped 1-1.
	334	*/
	335	#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
	336	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
	337	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
	338	#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
	339	#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
	340	#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
	341	#define CONFIG_SYS_PCI_IO_BASE 0x00000000
	342	#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
	343	#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
	344
	345	#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
	346	#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
	347	#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
	348
	349	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	350	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
	351	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
	352	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	353	#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
	354	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
	355	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	356	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
	357	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
	358
	359	#define CONFIG_SYS_PCIE2_BASE 0xC0000000
	360	#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
	361	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
	362	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
	363	#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
	364	#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
	365	#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
	366	#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
	367	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
	368
	369	#define CONFIG_PCI
	370	#define CONFIG_PCI_INDIRECT_BRIDGE
	371	#define CONFIG_PCIE
	372
	373	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	374
	375	#define CONFIG_EEPRO100
	376	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	377	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	378
	379	#define CONFIG_HAS_FSL_DR_USB
	380	#define CONFIG_SYS_SCCR_USBDRCM 3
	381
	382	#define CONFIG_CMD_USB
	383	#define CONFIG_USB_STORAGE
	384	#define CONFIG_USB_EHCI
	385	#define CONFIG_USB_EHCI_FSL
	386	#define CONFIG_USB_PHY_TYPE "utmi"
	387	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	388
	389	/*
	390	* TSEC
	391	*/
	392	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
	393	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	394	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
	395	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	396	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
	397
	398	/*
	399	* TSEC ethernet configuration
	400	*/
	401	#define CONFIG_MII 1 /* MII PHY management */
	402	#define CONFIG_TSEC1 1
	403	#define CONFIG_TSEC1_NAME "eTSEC0"
	404	#define CONFIG_TSEC2 1
	405	#define CONFIG_TSEC2_NAME "eTSEC1"
	406	#define TSEC1_PHY_ADDR 0
	407	#define TSEC2_PHY_ADDR 1
	408	#define TSEC1_PHYIDX 0
	409	#define TSEC2_PHYIDX 0
	410	#define TSEC1_FLAGS TSEC_GIGABIT
	411	#define TSEC2_FLAGS TSEC_GIGABIT
	412
	413	/* Options are: eTSEC[0-1] */
	414	#define CONFIG_ETHPRIME "eTSEC1"
	415
	416	/*
	417	* SATA
	418	*/
	419	#define CONFIG_LIBATA
	420	#define CONFIG_FSL_SATA
	421
	422	#define CONFIG_SYS_SATA_MAX_DEVICE 2
	423	#define CONFIG_SATA1
	424	#define CONFIG_SYS_SATA1_OFFSET 0x18000
	425	#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
	426	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
	427	#define CONFIG_SATA2
	428	#define CONFIG_SYS_SATA2_OFFSET 0x19000
	429	#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
	430	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
	431
	432	#ifdef CONFIG_FSL_SATA
	433	#define CONFIG_LBA48
	434	#define CONFIG_CMD_SATA
	435	#define CONFIG_DOS_PARTITION
	436	#define CONFIG_CMD_EXT2
	437	#endif
	438
	439	/*
	440	* Environment
	441	*/
	442	#if !defined(CONFIG_SYS_RAMBOOT)
	443	#define CONFIG_ENV_IS_IN_FLASH 1
	444	#define CONFIG_ENV_ADDR \
	445	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	446	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
	447	#define CONFIG_ENV_SIZE 0x2000
	448	#else
	449	#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
	450	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	451	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
	452	#define CONFIG_ENV_SIZE 0x2000
	453	#endif
	454
	455	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	456	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	457
	458	/*
	459	* BOOTP options
	460	*/
	461	#define CONFIG_BOOTP_BOOTFILESIZE
	462	#define CONFIG_BOOTP_BOOTPATH
	463	#define CONFIG_BOOTP_GATEWAY
	464	#define CONFIG_BOOTP_HOSTNAME
	465
	466	/*
	467	* Command line configuration.
	468	*/
	469	#define CONFIG_CMD_PING
	470	#define CONFIG_CMD_I2C
	471	#define CONFIG_CMD_MII
	472	#define CONFIG_CMD_DATE
	473	#define CONFIG_CMD_PCI
	474
	475	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	476	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
	477
	478	#undef CONFIG_WATCHDOG /* watchdog disabled */
	479
	480	/*
	481	* Miscellaneous configurable options
	482	*/
	483	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	484	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
	485
	486	#if defined(CONFIG_CMD_KGDB)
	487	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	488	#else
	489	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	490	#endif
	491
	492	/* Print Buffer Size */
	493	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	494	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	495	/* Boot Argument Buffer Size */
	496	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	497
	498	/*
	499	* For booting Linux, the board info and command line data
	500	* have to be in the first 256 MB of memory, since this is
	501	* the maximum mapped by the Linux kernel during initialization.
	502	*/
	503	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
	504
	505	/*
	506	* Core HID Setup
	507	*/
	508	#define CONFIG_SYS_HID0_INIT 0x000000000
	509	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	510	HID0_ENABLE_INSTRUCTION_CACHE \| \
	511	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
	512	#define CONFIG_SYS_HID2 HID2_HBE
	513
	514	/*
	515	* MMU Setup
	516	*/
	517	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	518
	519	/* DDR: cache cacheable */
	520	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
	521	\| BATL_PP_RW \
	522	\| BATL_MEMCOHERENCE)
	523	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	524	\| BATU_BL_128M \
	525	\| BATU_VS \
	526	\| BATU_VP)
	527	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	528	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	529
	530	/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
	531	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
	532	\| BATL_PP_RW \
	533	\| BATL_CACHEINHIBIT \
	534	\| BATL_GUARDEDSTORAGE)
	535	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
	536	\| BATU_BL_8M \
	537	\| BATU_VS \
	538	\| BATU_VP)
	539	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	540	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	541
	542	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
	543	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
	544	\| BATL_PP_RW \
	545	\| BATL_MEMCOHERENCE)
	546	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
	547	\| BATU_BL_32M \
	548	\| BATU_VS \
	549	\| BATU_VP)
	550	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
	551	\| BATL_PP_RW \
	552	\| BATL_CACHEINHIBIT \
	553	\| BATL_GUARDEDSTORAGE)
	554	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	555
	556	/* Stack in dcache: cacheable, no memory coherence */
	557	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)
	558	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
	559	\| BATU_BL_128K \
	560	\| BATU_VS \
	561	\| BATU_VP)
	562	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	563	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	564
	565	/* PCI MEM space: cacheable */
	566	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
	567	\| BATL_PP_RW \
	568	\| BATL_MEMCOHERENCE)
	569	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
	570	\| BATU_BL_256M \
	571	\| BATU_VS \
	572	\| BATU_VP)
	573	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	574	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	575
	576	/* PCI MMIO space: cache-inhibit and guarded */
	577	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
	578	\| BATL_PP_RW \
	579	\| BATL_CACHEINHIBIT \
	580	\| BATL_GUARDEDSTORAGE)
	581	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
	582	\| BATU_BL_256M \
	583	\| BATU_VS \
	584	\| BATU_VP)
	585	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	586	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	587
	588	#define CONFIG_SYS_IBAT6L 0
	589	#define CONFIG_SYS_IBAT6U 0
	590	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	591	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	592
	593	#define CONFIG_SYS_IBAT7L 0
	594	#define CONFIG_SYS_IBAT7U 0
	595	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	596	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
	597
	598	#if defined(CONFIG_CMD_KGDB)
	599	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
	600	#endif
	601
	602	/*
	603	* Environment Configuration
	604	*/
	605
	606	#define CONFIG_ENV_OVERWRITE
	607
	608	#if defined(CONFIG_TSEC_ENET)
	609	#define CONFIG_HAS_ETH0
	610	#define CONFIG_HAS_ETH1
	611	#endif
	612
	613	#define CONFIG_BAUDRATE 115200
	614
	615	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
	616
	617	#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
	618	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	619
	620	#define CONFIG_EXTRA_ENV_SETTINGS \
	621	"netdev=eth0\0" \
	622	"consoledev=ttyS0\0" \
	623	"ramdiskaddr=1000000\0" \
	624	"ramdiskfile=ramfs.83xx\0" \
	625	"fdtaddr=780000\0" \
	626	"fdtfile=mpc8315erdb.dtb\0" \
	627	"usb_phy_type=utmi\0" \
	628	""
	629
	630	#define CONFIG_NFSBOOTCOMMAND \
	631	"setenv bootargs root=/dev/nfs rw " \
	632	"nfsroot=$serverip:$rootpath " \
	633	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	634	"$netdev:off " \
	635	"console=$consoledev,$baudrate $othbootargs;" \
	636	"tftp $loadaddr $bootfile;" \
	637	"tftp $fdtaddr $fdtfile;" \
	638	"bootm $loadaddr - $fdtaddr"
	639
	640	#define CONFIG_RAMBOOTCOMMAND \
	641	"setenv bootargs root=/dev/ram rw " \
	642	"console=$consoledev,$baudrate $othbootargs;" \
	643	"tftp $ramdiskaddr $ramdiskfile;" \
	644	"tftp $loadaddr $bootfile;" \
	645	"tftp $fdtaddr $fdtfile;" \
	646	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	647
	648
	649	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	650
	651	#endif /* __CONFIG_H */