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1 | /* | |
2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | /* | |
8 | * mpc8544ds board configuration file | |
9 | * | |
10 | */ | |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | #define CONFIG_DISPLAY_BOARDINFO | |
15 | ||
16 | /* High Level Configuration Options */ | |
17 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
18 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
19 | #define CONFIG_MPC8544 1 | |
20 | #define CONFIG_MPC8544DS 1 | |
21 | ||
22 | #ifndef CONFIG_SYS_TEXT_BASE | |
23 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
24 | #endif | |
25 | ||
26 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ | |
27 | #define CONFIG_PCI1 1 /* PCI controller 1 */ | |
28 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
29 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
30 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
31 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
32 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ | |
33 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
34 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
35 | ||
36 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
37 | ||
38 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
39 | #define CONFIG_ENV_OVERWRITE | |
40 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ | |
41 | ||
42 | #ifndef __ASSEMBLY__ | |
43 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
44 | #endif | |
45 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
46 | ||
47 | /* | |
48 | * These can be toggled for performance analysis, otherwise use default. | |
49 | */ | |
50 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
51 | #define CONFIG_BTB /* toggle branch predition */ | |
52 | ||
53 | /* | |
54 | * Only possible on E500 Version 2 or newer cores. | |
55 | */ | |
56 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
57 | ||
58 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
59 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
60 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
61 | ||
62 | #define CONFIG_SYS_CCSRBAR 0xe0000000 | |
63 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
64 | ||
65 | /* DDR Setup */ | |
66 | #define CONFIG_SYS_FSL_DDR2 | |
67 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
68 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
69 | #define CONFIG_DDR_SPD | |
70 | ||
71 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
72 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
73 | ||
74 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
75 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
76 | #define CONFIG_VERY_BIG_RAM | |
77 | ||
78 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
79 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
80 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
81 | ||
82 | /* I2C addresses of SPD EEPROMs */ | |
83 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
84 | ||
85 | /* Make sure required options are set */ | |
86 | #ifndef CONFIG_SPD_EEPROM | |
87 | #error ("CONFIG_SPD_EEPROM is required") | |
88 | #endif | |
89 | ||
90 | #undef CONFIG_CLOCKS_IN_MHZ | |
91 | ||
92 | /* | |
93 | * Memory map | |
94 | * | |
95 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
96 | * | |
97 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
98 | * | |
99 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
100 | * | |
101 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable | |
102 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
103 | * | |
104 | * Localbus cacheable | |
105 | * | |
106 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable | |
107 | * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 | |
108 | * | |
109 | * Localbus non-cacheable | |
110 | * | |
111 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable | |
112 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
113 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable | |
114 | * | |
115 | */ | |
116 | ||
117 | /* | |
118 | * Local Bus Definitions | |
119 | */ | |
120 | #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ | |
121 | ||
122 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ | |
123 | ||
124 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 | |
125 | #define CONFIG_SYS_BR1_PRELIM 0xfe801001 | |
126 | ||
127 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 | |
128 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
129 | ||
130 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
131 | ||
132 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
133 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
134 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
135 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
136 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
137 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
138 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
139 | ||
140 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
141 | ||
142 | #define CONFIG_FLASH_CFI_DRIVER | |
143 | #define CONFIG_SYS_FLASH_CFI | |
144 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
145 | ||
146 | #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 | |
147 | ||
148 | #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ | |
149 | #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ | |
150 | ||
151 | #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ | |
152 | #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
153 | ||
154 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ | |
155 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ | |
156 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
157 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
158 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
159 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
160 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch | |
161 | * register */ | |
162 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
163 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
164 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
165 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
166 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
167 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ | |
168 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
169 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
170 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
171 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
172 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
173 | #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ | |
174 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ | |
175 | #define PIXIS_VSPEED2_TSEC1SER 0x2 | |
176 | #define PIXIS_VSPEED2_TSEC3SER 0x1 | |
177 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
178 | #define PIXIS_VCFGEN1_TSEC3SER 0x40 | |
179 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) | |
180 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) | |
181 | ||
182 | ||
183 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
184 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ | |
185 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ | |
186 | ||
187 | ||
188 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
189 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
190 | ||
191 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
192 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
193 | ||
194 | /* Serial Port - controlled on board with jumper J8 | |
195 | * open - index 2 | |
196 | * shorted - index 1 | |
197 | */ | |
198 | #define CONFIG_CONS_INDEX 1 | |
199 | #define CONFIG_SYS_NS16550_SERIAL | |
200 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
201 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
202 | ||
203 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
204 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
205 | ||
206 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
207 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
208 | ||
209 | /* I2C */ | |
210 | #define CONFIG_SYS_I2C | |
211 | #define CONFIG_SYS_I2C_FSL | |
212 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
213 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
214 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
215 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
216 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
217 | ||
218 | /* | |
219 | * General PCI | |
220 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
221 | */ | |
222 | #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ | |
223 | #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ | |
224 | #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ | |
225 | #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ | |
226 | ||
227 | #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 | |
228 | #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 | |
229 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 | |
230 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
231 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 | |
232 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
233 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 | |
234 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ | |
235 | ||
236 | /* controller 2, Slot 1, tgtid 1, Base address 9000 */ | |
237 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" | |
238 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 | |
239 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 | |
240 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 | |
241 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
242 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 | |
243 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
244 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 | |
245 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
246 | ||
247 | /* controller 1, Slot 2,tgtid 2, Base address a000 */ | |
248 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" | |
249 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 | |
250 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
251 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
252 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
253 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 | |
254 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
255 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 | |
256 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
257 | ||
258 | /* controller 3, direct to uli, tgtid 3, Base address b000 */ | |
259 | #define CONFIG_SYS_PCIE3_NAME "ULI" | |
260 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 | |
261 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 | |
262 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 | |
263 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ | |
264 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ | |
265 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
266 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ | |
267 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ | |
268 | #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 | |
269 | #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 | |
270 | #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 | |
271 | #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ | |
272 | ||
273 | #if defined(CONFIG_PCI) | |
274 | ||
275 | /*PCIE video card used*/ | |
276 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT | |
277 | ||
278 | /*PCI video card used*/ | |
279 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ | |
280 | ||
281 | /* video */ | |
282 | #define CONFIG_VIDEO | |
283 | ||
284 | #if defined(CONFIG_VIDEO) | |
285 | #define CONFIG_BIOSEMU | |
286 | #define CONFIG_CFB_CONSOLE | |
287 | #define CONFIG_VIDEO_SW_CURSOR | |
288 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
289 | #define CONFIG_ATI_RADEON_FB | |
290 | #define CONFIG_VIDEO_LOGO | |
291 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
292 | #endif | |
293 | ||
294 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
295 | ||
296 | #undef CONFIG_EEPRO100 | |
297 | #undef CONFIG_TULIP | |
298 | ||
299 | #ifndef CONFIG_PCI_PNP | |
300 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS | |
301 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
302 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ | |
303 | #endif | |
304 | ||
305 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
306 | #define CONFIG_DOS_PARTITION | |
307 | #define CONFIG_SCSI_AHCI | |
308 | ||
309 | #ifdef CONFIG_SCSI_AHCI | |
310 | #define CONFIG_LIBATA | |
311 | #define CONFIG_SATA_ULI5288 | |
312 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 | |
313 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
314 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
315 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
316 | #endif /* SCSCI */ | |
317 | ||
318 | #endif /* CONFIG_PCI */ | |
319 | ||
320 | ||
321 | #if defined(CONFIG_TSEC_ENET) | |
322 | ||
323 | #define CONFIG_MII 1 /* MII PHY management */ | |
324 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
325 | #define CONFIG_TSEC1 1 | |
326 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
327 | #define CONFIG_TSEC3 1 | |
328 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
329 | ||
330 | #define CONFIG_PIXIS_SGMII_CMD | |
331 | #define CONFIG_FSL_SGMII_RISER 1 | |
332 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
333 | ||
334 | #define TSEC1_PHY_ADDR 0 | |
335 | #define TSEC3_PHY_ADDR 1 | |
336 | ||
337 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
338 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
339 | ||
340 | #define TSEC1_PHYIDX 0 | |
341 | #define TSEC3_PHYIDX 0 | |
342 | ||
343 | #define CONFIG_ETHPRIME "eTSEC1" | |
344 | ||
345 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
346 | #endif /* CONFIG_TSEC_ENET */ | |
347 | ||
348 | /* | |
349 | * Environment | |
350 | */ | |
351 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
352 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
353 | #define CONFIG_ENV_ADDR 0xfff80000 | |
354 | #else | |
355 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) | |
356 | #endif | |
357 | #define CONFIG_ENV_SIZE 0x2000 | |
358 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ | |
359 | ||
360 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
361 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
362 | ||
363 | /* | |
364 | * BOOTP options | |
365 | */ | |
366 | #define CONFIG_BOOTP_BOOTFILESIZE | |
367 | #define CONFIG_BOOTP_BOOTPATH | |
368 | #define CONFIG_BOOTP_GATEWAY | |
369 | #define CONFIG_BOOTP_HOSTNAME | |
370 | ||
371 | ||
372 | /* | |
373 | * Command line configuration. | |
374 | */ | |
375 | #define CONFIG_CMD_PING | |
376 | #define CONFIG_CMD_I2C | |
377 | #define CONFIG_CMD_MII | |
378 | #define CONFIG_CMD_IRQ | |
379 | #define CONFIG_CMD_REGINFO | |
380 | ||
381 | #if defined(CONFIG_PCI) | |
382 | #define CONFIG_CMD_PCI | |
383 | #define CONFIG_CMD_SCSI | |
384 | #define CONFIG_CMD_EXT2 | |
385 | #endif | |
386 | ||
387 | /* | |
388 | * USB | |
389 | */ | |
390 | #define CONFIG_USB_EHCI | |
391 | ||
392 | #ifdef CONFIG_USB_EHCI | |
393 | #define CONFIG_CMD_USB | |
394 | #define CONFIG_USB_EHCI_PCI | |
395 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
396 | #define CONFIG_USB_STORAGE | |
397 | #define CONFIG_PCI_EHCI_DEVICE 0 | |
398 | #endif | |
399 | ||
400 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
401 | ||
402 | /* | |
403 | * Miscellaneous configurable options | |
404 | */ | |
405 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
406 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
407 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
408 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
409 | #if defined(CONFIG_CMD_KGDB) | |
410 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
411 | #else | |
412 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
413 | #endif | |
414 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
415 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
416 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
417 | ||
418 | /* | |
419 | * For booting Linux, the board info and command line data | |
420 | * have to be in the first 64 MB of memory, since this is | |
421 | * the maximum mapped by the Linux kernel during initialization. | |
422 | */ | |
423 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ | |
424 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
425 | ||
426 | #if defined(CONFIG_CMD_KGDB) | |
427 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
428 | #endif | |
429 | ||
430 | /* | |
431 | * Environment Configuration | |
432 | */ | |
433 | ||
434 | /* The mac addresses for all ethernet interface */ | |
435 | #if defined(CONFIG_TSEC_ENET) | |
436 | #define CONFIG_HAS_ETH0 | |
437 | #define CONFIG_HAS_ETH1 | |
438 | #endif | |
439 | ||
440 | #define CONFIG_IPADDR 192.168.1.251 | |
441 | ||
442 | #define CONFIG_HOSTNAME 8544ds_unknown | |
443 | #define CONFIG_ROOTPATH "/nfs/mpc85xx" | |
444 | #define CONFIG_BOOTFILE "8544ds/uImage.uboot" | |
445 | #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ | |
446 | ||
447 | #define CONFIG_SERVERIP 192.168.1.1 | |
448 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
449 | #define CONFIG_NETMASK 255.255.0.0 | |
450 | ||
451 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
452 | ||
453 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
454 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
455 | ||
456 | #define CONFIG_BAUDRATE 115200 | |
457 | ||
458 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
459 | "netdev=eth0\0" \ | |
460 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
461 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
462 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
463 | " +$filesize; " \ | |
464 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
465 | " +$filesize; " \ | |
466 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
467 | " $filesize; " \ | |
468 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
469 | " +$filesize; " \ | |
470 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
471 | " $filesize\0" \ | |
472 | "consoledev=ttyS0\0" \ | |
473 | "ramdiskaddr=2000000\0" \ | |
474 | "ramdiskfile=8544ds/ramdisk.uboot\0" \ | |
475 | "fdtaddr=c00000\0" \ | |
476 | "fdtfile=8544ds/mpc8544ds.dtb\0" \ | |
477 | "bdev=sda3\0" | |
478 | ||
479 | #define CONFIG_NFSBOOTCOMMAND \ | |
480 | "setenv bootargs root=/dev/nfs rw " \ | |
481 | "nfsroot=$serverip:$rootpath " \ | |
482 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
483 | "console=$consoledev,$baudrate $othbootargs;" \ | |
484 | "tftp $loadaddr $bootfile;" \ | |
485 | "tftp $fdtaddr $fdtfile;" \ | |
486 | "bootm $loadaddr - $fdtaddr" | |
487 | ||
488 | #define CONFIG_RAMBOOTCOMMAND \ | |
489 | "setenv bootargs root=/dev/ram rw " \ | |
490 | "console=$consoledev,$baudrate $othbootargs;" \ | |
491 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
492 | "tftp $loadaddr $bootfile;" \ | |
493 | "tftp $fdtaddr $fdtfile;" \ | |
494 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
495 | ||
496 | #define CONFIG_BOOTCOMMAND \ | |
497 | "setenv bootargs root=/dev/$bdev rw " \ | |
498 | "console=$consoledev,$baudrate $othbootargs;" \ | |
499 | "tftp $loadaddr $bootfile;" \ | |
500 | "tftp $fdtaddr $fdtfile;" \ | |
501 | "bootm $loadaddr - $fdtaddr" | |
502 | ||
503 | #endif /* __CONFIG_H */ |