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1 | /* | |
2 | * Copyright 2004, 2011 Freescale Semiconductor. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | /* | |
8 | * mpc8555cds board configuration file | |
9 | * | |
10 | * Please refer to doc/README.mpc85xxcds for more info. | |
11 | * | |
12 | */ | |
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* High Level Configuration Options */ | |
17 | #define CONFIG_CPM2 1 /* has CPM2 */ | |
18 | ||
19 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
20 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
21 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
22 | #define CONFIG_ENV_OVERWRITE | |
23 | ||
24 | #define CONFIG_FSL_VIA | |
25 | ||
26 | #ifndef __ASSEMBLY__ | |
27 | extern unsigned long get_clock_freq(void); | |
28 | #endif | |
29 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
30 | ||
31 | /* | |
32 | * These can be toggled for performance analysis, otherwise use default. | |
33 | */ | |
34 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
35 | #define CONFIG_BTB /* toggle branch predition */ | |
36 | ||
37 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
38 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
39 | ||
40 | #define CONFIG_SYS_CCSRBAR 0xe0000000 | |
41 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
42 | ||
43 | /* DDR Setup */ | |
44 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
45 | #define CONFIG_DDR_SPD | |
46 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
47 | ||
48 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
49 | ||
50 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
51 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
52 | ||
53 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
54 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
55 | ||
56 | /* I2C addresses of SPD EEPROMs */ | |
57 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
58 | ||
59 | /* Make sure required options are set */ | |
60 | #ifndef CONFIG_SPD_EEPROM | |
61 | #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") | |
62 | #endif | |
63 | ||
64 | #undef CONFIG_CLOCKS_IN_MHZ | |
65 | ||
66 | /* | |
67 | * Local Bus Definitions | |
68 | */ | |
69 | ||
70 | /* | |
71 | * FLASH on the Local Bus | |
72 | * Two banks, 8M each, using the CFI driver. | |
73 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
74 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
75 | * | |
76 | * BR0, BR1: | |
77 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
78 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
79 | * Port Size = 16 bits = BRx[19:20] = 10 | |
80 | * Use GPCM = BRx[24:26] = 000 | |
81 | * Valid = BRx[31] = 1 | |
82 | * | |
83 | * 0 4 8 12 16 20 24 28 | |
84 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
85 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
86 | * | |
87 | * OR0, OR1: | |
88 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
89 | * Reserved ORx[17:18] = 11, confusion here? | |
90 | * CSNT = ORx[20] = 1 | |
91 | * ACS = half cycle delay = ORx[21:22] = 11 | |
92 | * SCY = 6 = ORx[24:27] = 0110 | |
93 | * TRLX = use relaxed timing = ORx[29] = 1 | |
94 | * EAD = use external address latch delay = OR[31] = 1 | |
95 | * | |
96 | * 0 4 8 12 16 20 24 28 | |
97 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
98 | */ | |
99 | ||
100 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ | |
101 | ||
102 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 | |
103 | #define CONFIG_SYS_BR1_PRELIM 0xff001001 | |
104 | ||
105 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 | |
106 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
107 | ||
108 | #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} | |
109 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
110 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
111 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
112 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
113 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
114 | ||
115 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
116 | ||
117 | #define CONFIG_FLASH_CFI_DRIVER | |
118 | #define CONFIG_SYS_FLASH_CFI | |
119 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
120 | ||
121 | /* | |
122 | * SDRAM on the Local Bus | |
123 | */ | |
124 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ | |
125 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
126 | ||
127 | /* | |
128 | * Base Register 2 and Option Register 2 configure SDRAM. | |
129 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. | |
130 | * | |
131 | * For BR2, need: | |
132 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
133 | * port-size = 32-bits = BR2[19:20] = 11 | |
134 | * no parity checking = BR2[21:22] = 00 | |
135 | * SDRAM for MSEL = BR2[24:26] = 011 | |
136 | * Valid = BR[31] = 1 | |
137 | * | |
138 | * 0 4 8 12 16 20 24 28 | |
139 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
140 | * | |
141 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into | |
142 | * FIXME: the top 17 bits of BR2. | |
143 | */ | |
144 | ||
145 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 | |
146 | ||
147 | /* | |
148 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. | |
149 | * | |
150 | * For OR2, need: | |
151 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
152 | * XAM, OR2[17:18] = 11 | |
153 | * 9 columns OR2[19-21] = 010 | |
154 | * 13 rows OR2[23-25] = 100 | |
155 | * EAD set for extra time OR[31] = 1 | |
156 | * | |
157 | * 0 4 8 12 16 20 24 28 | |
158 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
159 | */ | |
160 | ||
161 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 | |
162 | ||
163 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ | |
164 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
165 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
166 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
167 | ||
168 | /* | |
169 | * Common settings for all Local Bus SDRAM commands. | |
170 | * At run time, either BSMA1516 (for CPU 1.1) | |
171 | * or BSMA1617 (for CPU 1.0) (old) | |
172 | * is OR'ed in too. | |
173 | */ | |
174 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ | |
175 | | LSDMR_PRETOACT7 \ | |
176 | | LSDMR_ACTTORW7 \ | |
177 | | LSDMR_BL8 \ | |
178 | | LSDMR_WRC4 \ | |
179 | | LSDMR_CL3 \ | |
180 | | LSDMR_RFEN \ | |
181 | ) | |
182 | ||
183 | /* | |
184 | * The CADMUS registers are connected to CS3 on CDS. | |
185 | * The new memory map places CADMUS at 0xf8000000. | |
186 | * | |
187 | * For BR3, need: | |
188 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
189 | * port-size = 8-bits = BR[19:20] = 01 | |
190 | * no parity checking = BR[21:22] = 00 | |
191 | * GPMC for MSEL = BR[24:26] = 000 | |
192 | * Valid = BR[31] = 1 | |
193 | * | |
194 | * 0 4 8 12 16 20 24 28 | |
195 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 | |
196 | * | |
197 | * For OR3, need: | |
198 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 | |
199 | * disable buffer ctrl OR[19] = 0 | |
200 | * CSNT OR[20] = 1 | |
201 | * ACS OR[21:22] = 11 | |
202 | * XACS OR[23] = 1 | |
203 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe | |
204 | * SETA OR[28] = 0 | |
205 | * TRLX OR[29] = 1 | |
206 | * EHTR OR[30] = 1 | |
207 | * EAD extra time OR[31] = 1 | |
208 | * | |
209 | * 0 4 8 12 16 20 24 28 | |
210 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 | |
211 | */ | |
212 | ||
213 | #define CONFIG_FSL_CADMUS | |
214 | ||
215 | #define CADMUS_BASE_ADDR 0xf8000000 | |
216 | #define CONFIG_SYS_BR3_PRELIM 0xf8000801 | |
217 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 | |
218 | ||
219 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
220 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
221 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ | |
222 | ||
223 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
224 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
225 | ||
226 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
227 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
228 | ||
229 | /* Serial Port */ | |
230 | #define CONFIG_CONS_INDEX 2 | |
231 | #define CONFIG_SYS_NS16550_SERIAL | |
232 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
233 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
234 | ||
235 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
236 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
237 | ||
238 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
239 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
240 | ||
241 | /* | |
242 | * I2C | |
243 | */ | |
244 | #define CONFIG_SYS_I2C | |
245 | #define CONFIG_SYS_I2C_FSL | |
246 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
247 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
248 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
249 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
250 | ||
251 | /* EEPROM */ | |
252 | #define CONFIG_ID_EEPROM | |
253 | #define CONFIG_SYS_I2C_EEPROM_CCID | |
254 | #define CONFIG_SYS_ID_EEPROM | |
255 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
256 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
257 | ||
258 | /* | |
259 | * General PCI | |
260 | * Addresses are mapped 1-1. | |
261 | */ | |
262 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 | |
263 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 | |
264 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 | |
265 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
266 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 | |
267 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
268 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 | |
269 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
270 | ||
271 | #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 | |
272 | #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 | |
273 | #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 | |
274 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ | |
275 | #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 | |
276 | #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 | |
277 | #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 | |
278 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
279 | ||
280 | #ifdef CONFIG_LEGACY | |
281 | #define BRIDGE_ID 17 | |
282 | #define VIA_ID 2 | |
283 | #else | |
284 | #define BRIDGE_ID 28 | |
285 | #define VIA_ID 4 | |
286 | #endif | |
287 | ||
288 | #if defined(CONFIG_PCI) | |
289 | ||
290 | #define CONFIG_MPC85XX_PCI2 | |
291 | ||
292 | #undef CONFIG_EEPRO100 | |
293 | #undef CONFIG_TULIP | |
294 | ||
295 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
296 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
297 | ||
298 | #endif /* CONFIG_PCI */ | |
299 | ||
300 | #if defined(CONFIG_TSEC_ENET) | |
301 | ||
302 | #define CONFIG_MII 1 /* MII PHY management */ | |
303 | #define CONFIG_TSEC1 1 | |
304 | #define CONFIG_TSEC1_NAME "TSEC0" | |
305 | #define CONFIG_TSEC2 1 | |
306 | #define CONFIG_TSEC2_NAME "TSEC1" | |
307 | #define TSEC1_PHY_ADDR 0 | |
308 | #define TSEC2_PHY_ADDR 1 | |
309 | #define TSEC1_PHYIDX 0 | |
310 | #define TSEC2_PHYIDX 0 | |
311 | #define TSEC1_FLAGS TSEC_GIGABIT | |
312 | #define TSEC2_FLAGS TSEC_GIGABIT | |
313 | ||
314 | /* Options are: TSEC[0-1] */ | |
315 | #define CONFIG_ETHPRIME "TSEC0" | |
316 | ||
317 | #endif /* CONFIG_TSEC_ENET */ | |
318 | ||
319 | /* | |
320 | * Environment | |
321 | */ | |
322 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) | |
323 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ | |
324 | #define CONFIG_ENV_SIZE 0x2000 | |
325 | ||
326 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
327 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
328 | ||
329 | /* | |
330 | * BOOTP options | |
331 | */ | |
332 | #define CONFIG_BOOTP_BOOTFILESIZE | |
333 | ||
334 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
335 | ||
336 | /* | |
337 | * Miscellaneous configurable options | |
338 | */ | |
339 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
340 | ||
341 | /* | |
342 | * For booting Linux, the board info and command line data | |
343 | * have to be in the first 64 MB of memory, since this is | |
344 | * the maximum mapped by the Linux kernel during initialization. | |
345 | */ | |
346 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ | |
347 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
348 | ||
349 | #if defined(CONFIG_CMD_KGDB) | |
350 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
351 | #endif | |
352 | ||
353 | /* | |
354 | * Environment Configuration | |
355 | */ | |
356 | #if defined(CONFIG_TSEC_ENET) | |
357 | #define CONFIG_HAS_ETH0 | |
358 | #define CONFIG_HAS_ETH1 | |
359 | #define CONFIG_HAS_ETH2 | |
360 | #endif | |
361 | ||
362 | #define CONFIG_IPADDR 192.168.1.253 | |
363 | ||
364 | #define CONFIG_HOSTNAME unknown | |
365 | #define CONFIG_ROOTPATH "/nfsroot" | |
366 | #define CONFIG_BOOTFILE "your.uImage" | |
367 | ||
368 | #define CONFIG_SERVERIP 192.168.1.1 | |
369 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
370 | #define CONFIG_NETMASK 255.255.255.0 | |
371 | ||
372 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
373 | ||
374 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
375 | "netdev=eth0\0" \ | |
376 | "consoledev=ttyS1\0" \ | |
377 | "ramdiskaddr=600000\0" \ | |
378 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
379 | "fdtaddr=400000\0" \ | |
380 | "fdtfile=your.fdt.dtb\0" | |
381 | ||
382 | #define CONFIG_NFSBOOTCOMMAND \ | |
383 | "setenv bootargs root=/dev/nfs rw " \ | |
384 | "nfsroot=$serverip:$rootpath " \ | |
385 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
386 | "console=$consoledev,$baudrate $othbootargs;" \ | |
387 | "tftp $loadaddr $bootfile;" \ | |
388 | "tftp $fdtaddr $fdtfile;" \ | |
389 | "bootm $loadaddr - $fdtaddr" | |
390 | ||
391 | #define CONFIG_RAMBOOTCOMMAND \ | |
392 | "setenv bootargs root=/dev/ram rw " \ | |
393 | "console=$consoledev,$baudrate $othbootargs;" \ | |
394 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
395 | "tftp $loadaddr $bootfile;" \ | |
396 | "bootm $loadaddr $ramdiskaddr" | |
397 | ||
398 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
399 | ||
400 | #endif /* __CONFIG_H */ |