| | 1 | /* |
| | 2 | * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. |
| | 3 | * |
| | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| | 5 | */ |
| | 6 | |
| | 7 | /* |
| | 8 | * mpc8572ds board configuration file |
| | 9 | * |
| | 10 | */ |
| | 11 | #ifndef __CONFIG_H |
| | 12 | #define __CONFIG_H |
| | 13 | |
| | 14 | #define CONFIG_DISPLAY_BOARDINFO |
| | 15 | |
| | 16 | #include "../board/freescale/common/ics307_clk.h" |
| | 17 | |
| | 18 | #ifdef CONFIG_36BIT |
| | 19 | #define CONFIG_PHYS_64BIT |
| | 20 | #endif |
| | 21 | |
| | 22 | #ifndef CONFIG_SYS_TEXT_BASE |
| | 23 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
| | 24 | #endif |
| | 25 | |
| | 26 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| | 27 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| | 28 | #endif |
| | 29 | |
| | 30 | #ifndef CONFIG_SYS_MONITOR_BASE |
| | 31 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| | 32 | #endif |
| | 33 | |
| | 34 | /* High Level Configuration Options */ |
| | 35 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| | 36 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| | 37 | #define CONFIG_MPC8572 1 |
| | 38 | #define CONFIG_MPC8572DS 1 |
| | 39 | #define CONFIG_MP 1 /* support multiple processors */ |
| | 40 | |
| | 41 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
| | 42 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| | 43 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ |
| | 44 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ |
| | 45 | #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ |
| | 46 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
| | 47 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
| | 48 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
| | 49 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| | 50 | |
| | 51 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| | 52 | |
| | 53 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| | 54 | #define CONFIG_ENV_OVERWRITE |
| | 55 | |
| | 56 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
| | 57 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ |
| | 58 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
| | 59 | |
| | 60 | /* |
| | 61 | * These can be toggled for performance analysis, otherwise use default. |
| | 62 | */ |
| | 63 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| | 64 | #define CONFIG_BTB /* toggle branch predition */ |
| | 65 | |
| | 66 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| | 67 | |
| | 68 | #ifdef CONFIG_PHYS_64BIT |
| | 69 | #define CONFIG_ADDR_MAP 1 |
| | 70 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
| | 71 | #endif |
| | 72 | |
| | 73 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
| | 74 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff |
| | 75 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| | 76 | |
| | 77 | /* |
| | 78 | * Config the L2 Cache as L2 SRAM |
| | 79 | */ |
| | 80 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| | 81 | #ifdef CONFIG_PHYS_64BIT |
| | 82 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull |
| | 83 | #else |
| | 84 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| | 85 | #endif |
| | 86 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
| | 87 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| | 88 | |
| | 89 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| | 90 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
| | 91 | |
| | 92 | #if defined(CONFIG_NAND_SPL) |
| | 93 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| | 94 | #endif |
| | 95 | |
| | 96 | /* DDR Setup */ |
| | 97 | #define CONFIG_VERY_BIG_RAM |
| | 98 | #define CONFIG_SYS_FSL_DDR2 |
| | 99 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| | 100 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| | 101 | #define CONFIG_DDR_SPD |
| | 102 | |
| | 103 | #define CONFIG_DDR_ECC |
| | 104 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| | 105 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| | 106 | |
| | 107 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| | 108 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| | 109 | |
| | 110 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| | 111 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| | 112 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| | 113 | |
| | 114 | /* I2C addresses of SPD EEPROMs */ |
| | 115 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ |
| | 116 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
| | 117 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ |
| | 118 | |
| | 119 | /* These are used when DDR doesn't use SPD. */ |
| | 120 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
| | 121 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F |
| | 122 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ |
| | 123 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 |
| | 124 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
| | 125 | #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 |
| | 126 | #define CONFIG_SYS_DDR_TIMING_2 0x062874cf |
| | 127 | #define CONFIG_SYS_DDR_MODE_1 0x00440462 |
| | 128 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| | 129 | #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 |
| | 130 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| | 131 | #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 |
| | 132 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
| | 133 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
| | 134 | #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ |
| | 135 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 |
| | 136 | |
| | 137 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
| | 138 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
| | 139 | #define CONFIG_SYS_DDR_SBE 0x00010000 |
| | 140 | |
| | 141 | /* |
| | 142 | * Make sure required options are set |
| | 143 | */ |
| | 144 | #ifndef CONFIG_SPD_EEPROM |
| | 145 | #error ("CONFIG_SPD_EEPROM is required") |
| | 146 | #endif |
| | 147 | |
| | 148 | #undef CONFIG_CLOCKS_IN_MHZ |
| | 149 | |
| | 150 | /* |
| | 151 | * Memory map |
| | 152 | * |
| | 153 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| | 154 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
| | 155 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable |
| | 156 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable |
| | 157 | * |
| | 158 | * Localbus cacheable (TBD) |
| | 159 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
| | 160 | * |
| | 161 | * Localbus non-cacheable |
| | 162 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable |
| | 163 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
| | 164 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
| | 165 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| | 166 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
| | 167 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| | 168 | */ |
| | 169 | |
| | 170 | /* |
| | 171 | * Local Bus Definitions |
| | 172 | */ |
| | 173 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
| | 174 | #ifdef CONFIG_PHYS_64BIT |
| | 175 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull |
| | 176 | #else |
| | 177 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| | 178 | #endif |
| | 179 | |
| | 180 | #define CONFIG_FLASH_BR_PRELIM \ |
| | 181 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
| | 182 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
| | 183 | |
| | 184 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
| | 185 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
| | 186 | |
| | 187 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
| | 188 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| | 189 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| | 190 | |
| | 191 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| | 192 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| | 193 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| | 194 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| | 195 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| | 196 | |
| | 197 | #undef CONFIG_SYS_RAMBOOT |
| | 198 | |
| | 199 | #define CONFIG_FLASH_CFI_DRIVER |
| | 200 | #define CONFIG_SYS_FLASH_CFI |
| | 201 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| | 202 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 |
| | 203 | |
| | 204 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
| | 205 | |
| | 206 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
| | 207 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
| | 208 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
| | 209 | #ifdef CONFIG_PHYS_64BIT |
| | 210 | #define PIXIS_BASE_PHYS 0xfffdf0000ull |
| | 211 | #else |
| | 212 | #define PIXIS_BASE_PHYS PIXIS_BASE |
| | 213 | #endif |
| | 214 | |
| | 215 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
| | 216 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
| | 217 | |
| | 218 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| | 219 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ |
| | 220 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ |
| | 221 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ |
| | 222 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ |
| | 223 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ |
| | 224 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ |
| | 225 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ |
| | 226 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ |
| | 227 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ |
| | 228 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ |
| | 229 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ |
| | 230 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ |
| | 231 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ |
| | 232 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ |
| | 233 | #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ |
| | 234 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ |
| | 235 | #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ |
| | 236 | #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ |
| | 237 | #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ |
| | 238 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| | 239 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ |
| | 240 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ |
| | 241 | #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ |
| | 242 | #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ |
| | 243 | #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ |
| | 244 | #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ |
| | 245 | #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ |
| | 246 | #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ |
| | 247 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ |
| | 248 | #define PIXIS_LED 0x25 /* LED Register */ |
| | 249 | |
| | 250 | #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ |
| | 251 | |
| | 252 | /* old pixis referenced names */ |
| | 253 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ |
| | 254 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ |
| | 255 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
| | 256 | #define PIXIS_VSPEED2_TSEC1SER 0x8 |
| | 257 | #define PIXIS_VSPEED2_TSEC2SER 0x4 |
| | 258 | #define PIXIS_VSPEED2_TSEC3SER 0x2 |
| | 259 | #define PIXIS_VSPEED2_TSEC4SER 0x1 |
| | 260 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 |
| | 261 | #define PIXIS_VCFGEN1_TSEC2SER 0x20 |
| | 262 | #define PIXIS_VCFGEN1_TSEC3SER 0x20 |
| | 263 | #define PIXIS_VCFGEN1_TSEC4SER 0x20 |
| | 264 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ |
| | 265 | | PIXIS_VSPEED2_TSEC2SER \ |
| | 266 | | PIXIS_VSPEED2_TSEC3SER \ |
| | 267 | | PIXIS_VSPEED2_TSEC4SER) |
| | 268 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ |
| | 269 | | PIXIS_VCFGEN1_TSEC2SER \ |
| | 270 | | PIXIS_VCFGEN1_TSEC3SER \ |
| | 271 | | PIXIS_VCFGEN1_TSEC4SER) |
| | 272 | |
| | 273 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| | 274 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ |
| | 275 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
| | 276 | |
| | 277 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| | 278 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| | 279 | |
| | 280 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| | 281 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
| | 282 | |
| | 283 | #ifndef CONFIG_NAND_SPL |
| | 284 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| | 285 | #ifdef CONFIG_PHYS_64BIT |
| | 286 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull |
| | 287 | #else |
| | 288 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| | 289 | #endif |
| | 290 | #else |
| | 291 | #define CONFIG_SYS_NAND_BASE 0xfff00000 |
| | 292 | #ifdef CONFIG_PHYS_64BIT |
| | 293 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull |
| | 294 | #else |
| | 295 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| | 296 | #endif |
| | 297 | #endif |
| | 298 | |
| | 299 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| | 300 | CONFIG_SYS_NAND_BASE + 0x40000, \ |
| | 301 | CONFIG_SYS_NAND_BASE + 0x80000,\ |
| | 302 | CONFIG_SYS_NAND_BASE + 0xC0000} |
| | 303 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 |
| | 304 | #define CONFIG_CMD_NAND 1 |
| | 305 | #define CONFIG_NAND_FSL_ELBC 1 |
| | 306 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| | 307 | #define CONFIG_SYS_NAND_MAX_OOBFREE 5 |
| | 308 | #define CONFIG_SYS_NAND_MAX_ECCPOS 56 |
| | 309 | |
| | 310 | /* NAND boot: 4K NAND loader config */ |
| | 311 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 |
| | 312 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) |
| | 313 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) |
| | 314 | #define CONFIG_SYS_NAND_U_BOOT_START \ |
| | 315 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) |
| | 316 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) |
| | 317 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) |
| | 318 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) |
| | 319 | |
| | 320 | /* NAND flash config */ |
| | 321 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| | 322 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| | 323 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| | 324 | | BR_MS_FCM /* MSEL = FCM */ \ |
| | 325 | | BR_V) /* valid */ |
| | 326 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
| | 327 | | OR_FCM_PGS /* Large Page*/ \ |
| | 328 | | OR_FCM_CSCT \ |
| | 329 | | OR_FCM_CST \ |
| | 330 | | OR_FCM_CHT \ |
| | 331 | | OR_FCM_SCY_1 \ |
| | 332 | | OR_FCM_TRLX \ |
| | 333 | | OR_FCM_EHTR) |
| | 334 | |
| | 335 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| | 336 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
| | 337 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| | 338 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| | 339 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
| | 340 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| | 341 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| | 342 | | BR_MS_FCM /* MSEL = FCM */ \ |
| | 343 | | BR_V) /* valid */ |
| | 344 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| | 345 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ |
| | 346 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| | 347 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| | 348 | | BR_MS_FCM /* MSEL = FCM */ \ |
| | 349 | | BR_V) /* valid */ |
| | 350 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| | 351 | |
| | 352 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ |
| | 353 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| | 354 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| | 355 | | BR_MS_FCM /* MSEL = FCM */ \ |
| | 356 | | BR_V) /* valid */ |
| | 357 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| | 358 | |
| | 359 | /* Serial Port - controlled on board with jumper J8 |
| | 360 | * open - index 2 |
| | 361 | * shorted - index 1 |
| | 362 | */ |
| | 363 | #define CONFIG_CONS_INDEX 1 |
| | 364 | #define CONFIG_SYS_NS16550_SERIAL |
| | 365 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| | 366 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| | 367 | #ifdef CONFIG_NAND_SPL |
| | 368 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| | 369 | #endif |
| | 370 | |
| | 371 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| | 372 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| | 373 | |
| | 374 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| | 375 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| | 376 | |
| | 377 | /* I2C */ |
| | 378 | #define CONFIG_SYS_I2C |
| | 379 | #define CONFIG_SYS_I2C_FSL |
| | 380 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| | 381 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| | 382 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| | 383 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| | 384 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| | 385 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
| | 386 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } |
| | 387 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| | 388 | |
| | 389 | /* |
| | 390 | * I2C2 EEPROM |
| | 391 | */ |
| | 392 | #define CONFIG_ID_EEPROM |
| | 393 | #ifdef CONFIG_ID_EEPROM |
| | 394 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| | 395 | #endif |
| | 396 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| | 397 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| | 398 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 |
| | 399 | |
| | 400 | /* |
| | 401 | * General PCI |
| | 402 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| | 403 | */ |
| | 404 | |
| | 405 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ |
| | 406 | #define CONFIG_SYS_PCIE3_NAME "ULI" |
| | 407 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
| | 408 | #ifdef CONFIG_PHYS_64BIT |
| | 409 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| | 410 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
| | 411 | #else |
| | 412 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
| | 413 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
| | 414 | #endif |
| | 415 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| | 416 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
| | 417 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| | 418 | #ifdef CONFIG_PHYS_64BIT |
| | 419 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull |
| | 420 | #else |
| | 421 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
| | 422 | #endif |
| | 423 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| | 424 | |
| | 425 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ |
| | 426 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
| | 427 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| | 428 | #ifdef CONFIG_PHYS_64BIT |
| | 429 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
| | 430 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| | 431 | #else |
| | 432 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| | 433 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
| | 434 | #endif |
| | 435 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| | 436 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| | 437 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| | 438 | #ifdef CONFIG_PHYS_64BIT |
| | 439 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
| | 440 | #else |
| | 441 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| | 442 | #endif |
| | 443 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| | 444 | |
| | 445 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ |
| | 446 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
| | 447 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
| | 448 | #ifdef CONFIG_PHYS_64BIT |
| | 449 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| | 450 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
| | 451 | #else |
| | 452 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
| | 453 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
| | 454 | #endif |
| | 455 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| | 456 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
| | 457 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| | 458 | #ifdef CONFIG_PHYS_64BIT |
| | 459 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull |
| | 460 | #else |
| | 461 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
| | 462 | #endif |
| | 463 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| | 464 | |
| | 465 | #if defined(CONFIG_PCI) |
| | 466 | |
| | 467 | /*PCIE video card used*/ |
| | 468 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
| | 469 | |
| | 470 | /* video */ |
| | 471 | #define CONFIG_VIDEO |
| | 472 | |
| | 473 | #if defined(CONFIG_VIDEO) |
| | 474 | #define CONFIG_BIOSEMU |
| | 475 | #define CONFIG_CFB_CONSOLE |
| | 476 | #define CONFIG_VIDEO_SW_CURSOR |
| | 477 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| | 478 | #define CONFIG_ATI_RADEON_FB |
| | 479 | #define CONFIG_VIDEO_LOGO |
| | 480 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| | 481 | #endif |
| | 482 | |
| | 483 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| | 484 | |
| | 485 | #undef CONFIG_EEPRO100 |
| | 486 | #undef CONFIG_TULIP |
| | 487 | |
| | 488 | #ifndef CONFIG_PCI_PNP |
| | 489 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS |
| | 490 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS |
| | 491 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| | 492 | #endif |
| | 493 | |
| | 494 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| | 495 | #define CONFIG_DOS_PARTITION |
| | 496 | #define CONFIG_SCSI_AHCI |
| | 497 | |
| | 498 | #ifdef CONFIG_SCSI_AHCI |
| | 499 | #define CONFIG_LIBATA |
| | 500 | #define CONFIG_SATA_ULI5288 |
| | 501 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| | 502 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| | 503 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) |
| | 504 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE |
| | 505 | #endif /* SCSI */ |
| | 506 | |
| | 507 | #endif /* CONFIG_PCI */ |
| | 508 | |
| | 509 | #if defined(CONFIG_TSEC_ENET) |
| | 510 | |
| | 511 | #define CONFIG_MII 1 /* MII PHY management */ |
| | 512 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| | 513 | #define CONFIG_TSEC1 1 |
| | 514 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| | 515 | #define CONFIG_TSEC2 1 |
| | 516 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| | 517 | #define CONFIG_TSEC3 1 |
| | 518 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| | 519 | #define CONFIG_TSEC4 1 |
| | 520 | #define CONFIG_TSEC4_NAME "eTSEC4" |
| | 521 | |
| | 522 | #define CONFIG_PIXIS_SGMII_CMD |
| | 523 | #define CONFIG_FSL_SGMII_RISER 1 |
| | 524 | #define SGMII_RISER_PHY_OFFSET 0x1c |
| | 525 | |
| | 526 | #ifdef CONFIG_FSL_SGMII_RISER |
| | 527 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ |
| | 528 | #endif |
| | 529 | |
| | 530 | #define TSEC1_PHY_ADDR 0 |
| | 531 | #define TSEC2_PHY_ADDR 1 |
| | 532 | #define TSEC3_PHY_ADDR 2 |
| | 533 | #define TSEC4_PHY_ADDR 3 |
| | 534 | |
| | 535 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| | 536 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| | 537 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| | 538 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| | 539 | |
| | 540 | #define TSEC1_PHYIDX 0 |
| | 541 | #define TSEC2_PHYIDX 0 |
| | 542 | #define TSEC3_PHYIDX 0 |
| | 543 | #define TSEC4_PHYIDX 0 |
| | 544 | |
| | 545 | #define CONFIG_ETHPRIME "eTSEC1" |
| | 546 | |
| | 547 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| | 548 | #endif /* CONFIG_TSEC_ENET */ |
| | 549 | |
| | 550 | /* |
| | 551 | * Environment |
| | 552 | */ |
| | 553 | |
| | 554 | #if defined(CONFIG_SYS_RAMBOOT) |
| | 555 | |
| | 556 | #else |
| | 557 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| | 558 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
| | 559 | #define CONFIG_ENV_ADDR 0xfff80000 |
| | 560 | #else |
| | 561 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| | 562 | #endif |
| | 563 | #define CONFIG_ENV_SIZE 0x2000 |
| | 564 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
| | 565 | #endif |
| | 566 | |
| | 567 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| | 568 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| | 569 | |
| | 570 | /* |
| | 571 | * Command line configuration. |
| | 572 | */ |
| | 573 | #define CONFIG_CMD_ERRATA |
| | 574 | #define CONFIG_CMD_IRQ |
| | 575 | #define CONFIG_CMD_REGINFO |
| | 576 | |
| | 577 | #if defined(CONFIG_PCI) |
| | 578 | #define CONFIG_CMD_PCI |
| | 579 | #define CONFIG_SCSI |
| | 580 | #endif |
| | 581 | |
| | 582 | /* |
| | 583 | * USB |
| | 584 | */ |
| | 585 | #define CONFIG_USB_EHCI |
| | 586 | |
| | 587 | #ifdef CONFIG_USB_EHCI |
| | 588 | #define CONFIG_USB_EHCI_PCI |
| | 589 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| | 590 | #define CONFIG_USB_STORAGE |
| | 591 | #define CONFIG_PCI_EHCI_DEVICE 0 |
| | 592 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 |
| | 593 | #endif |
| | 594 | |
| | 595 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| | 596 | |
| | 597 | /* |
| | 598 | * Miscellaneous configurable options |
| | 599 | */ |
| | 600 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| | 601 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| | 602 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| | 603 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| | 604 | #if defined(CONFIG_CMD_KGDB) |
| | 605 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| | 606 | #else |
| | 607 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| | 608 | #endif |
| | 609 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| | 610 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| | 611 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| | 612 | |
| | 613 | /* |
| | 614 | * For booting Linux, the board info and command line data |
| | 615 | * have to be in the first 64 MB of memory, since this is |
| | 616 | * the maximum mapped by the Linux kernel during initialization. |
| | 617 | */ |
| | 618 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| | 619 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| | 620 | |
| | 621 | #if defined(CONFIG_CMD_KGDB) |
| | 622 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| | 623 | #endif |
| | 624 | |
| | 625 | /* |
| | 626 | * Environment Configuration |
| | 627 | */ |
| | 628 | #if defined(CONFIG_TSEC_ENET) |
| | 629 | #define CONFIG_HAS_ETH0 |
| | 630 | #define CONFIG_HAS_ETH1 |
| | 631 | #define CONFIG_HAS_ETH2 |
| | 632 | #define CONFIG_HAS_ETH3 |
| | 633 | #endif |
| | 634 | |
| | 635 | #define CONFIG_IPADDR 192.168.1.254 |
| | 636 | |
| | 637 | #define CONFIG_HOSTNAME unknown |
| | 638 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| | 639 | #define CONFIG_BOOTFILE "uImage" |
| | 640 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| | 641 | |
| | 642 | #define CONFIG_SERVERIP 192.168.1.1 |
| | 643 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| | 644 | #define CONFIG_NETMASK 255.255.255.0 |
| | 645 | |
| | 646 | /* default location for tftp and bootm */ |
| | 647 | #define CONFIG_LOADADDR 1000000 |
| | 648 | |
| | 649 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| | 650 | |
| | 651 | #define CONFIG_BAUDRATE 115200 |
| | 652 | |
| | 653 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| | 654 | "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ |
| | 655 | "netdev=eth0\0" \ |
| | 656 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| | 657 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| | 658 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| | 659 | " +$filesize; " \ |
| | 660 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| | 661 | " +$filesize; " \ |
| | 662 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| | 663 | " $filesize; " \ |
| | 664 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| | 665 | " +$filesize; " \ |
| | 666 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| | 667 | " $filesize\0" \ |
| | 668 | "consoledev=ttyS0\0" \ |
| | 669 | "ramdiskaddr=2000000\0" \ |
| | 670 | "ramdiskfile=8572ds/ramdisk.uboot\0" \ |
| | 671 | "fdtaddr=c00000\0" \ |
| | 672 | "fdtfile=8572ds/mpc8572ds.dtb\0" \ |
| | 673 | "bdev=sda3\0" |
| | 674 | |
| | 675 | #define CONFIG_HDBOOT \ |
| | 676 | "setenv bootargs root=/dev/$bdev rw " \ |
| | 677 | "console=$consoledev,$baudrate $othbootargs;" \ |
| | 678 | "tftp $loadaddr $bootfile;" \ |
| | 679 | "tftp $fdtaddr $fdtfile;" \ |
| | 680 | "bootm $loadaddr - $fdtaddr" |
| | 681 | |
| | 682 | #define CONFIG_NFSBOOTCOMMAND \ |
| | 683 | "setenv bootargs root=/dev/nfs rw " \ |
| | 684 | "nfsroot=$serverip:$rootpath " \ |
| | 685 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| | 686 | "console=$consoledev,$baudrate $othbootargs;" \ |
| | 687 | "tftp $loadaddr $bootfile;" \ |
| | 688 | "tftp $fdtaddr $fdtfile;" \ |
| | 689 | "bootm $loadaddr - $fdtaddr" |
| | 690 | |
| | 691 | #define CONFIG_RAMBOOTCOMMAND \ |
| | 692 | "setenv bootargs root=/dev/ram rw " \ |
| | 693 | "console=$consoledev,$baudrate $othbootargs;" \ |
| | 694 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| | 695 | "tftp $loadaddr $bootfile;" \ |
| | 696 | "tftp $fdtaddr $fdtfile;" \ |
| | 697 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| | 698 | |
| | 699 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT |
| | 700 | |
| | 701 | #endif /* __CONFIG_H */ |
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