[people/ms/u-boot.git] / include / configs / dbau1x00.h

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * This file contains the configuration parameters for the dbau1x00 board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_DBAU1X00		1
#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */

#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
#define CONFIG_SOC_AU1000	1
#else
#ifdef CONFIG_DBAU1100
#define CONFIG_SOC_AU1100	1
#else
#ifdef CONFIG_DBAU1500
#define CONFIG_SOC_AU1500	1
#else
#ifdef CONFIG_DBAU1550
/* Cabernet */
#define CONFIG_SOC_AU1550	1
#else
#error "No valid board set"
#endif
#endif
#endif
#endif

/* valid baudrates */

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"addmisc=setenv bootargs ${bootargs} "				\
		"console=ttyS0,${baudrate} "				\
		"panic=1\0"						\
	"bootfile=/tftpboot/vmlinux.srec\0"				\
	"load=tftp 80500000 ${u-boot}\0"				\
	""

#ifdef CONFIG_DBAU1550
/* Boot from flash by default, revert to bootp */
#define CONFIG_BOOTCOMMAND	"bootm 0xbfc20000; bootp; bootm"
#else /* CONFIG_DBAU1550 */
#define CONFIG_BOOTCOMMAND	"bootp;bootm"
#endif /* CONFIG_DBAU1550 */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_MALLOC_LEN		128*1024

#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024

#define CONFIG_SYS_MHZ			396

#if (CONFIG_SYS_MHZ % 12) != 0
#error "Invalid CPU frequency - must be multiple of 12!"
#endif

#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)

#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */

#define	CONFIG_SYS_LOAD_ADDR		0x81000000     /* default load address	*/

#define CONFIG_SYS_MEMTEST_START	0x80100000
#define CONFIG_SYS_MEMTEST_END		0x80800000

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#ifdef CONFIG_DBAU1550

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	(512)	/* max number of sectors on one chip */

#define PHYS_FLASH_1		0xb8000000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0xbc000000 /* Flash Bank #2 */

#else /* CONFIG_DBAU1550 */

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */

#define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */

#endif /* CONFIG_DBAU1550 */

#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}

#define CONFIG_SYS_FLASH_CFI           1
#define CONFIG_FLASH_CFI_DRIVER    1

#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)

#define CONFIG_SYS_INIT_SP_OFFSET	0x400000

/* We boot from this flash, selected with dip switch */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_2

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */

/* Address and size of Primary Environment Sector	*/
#define CONFIG_ENV_ADDR		0xB0030000
#define CONFIG_ENV_SIZE		0x10000

#define CONFIG_FLASH_16BIT

#define CONFIG_NR_DRAM_BANKS	2

#ifdef CONFIG_DBAU1550
#define MEM_SIZE 192
#else
#define MEM_SIZE 64
#endif

#define CONFIG_MEMSIZE_IN_BYTES

#ifndef CONFIG_DBAU1550
/*---ATA PCMCIA ------------------------------------*/
#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
#define CONFIG_PCMCIA_SLOT_A

#define CONFIG_ATAPI 1

/* We run CF in "true ide" mode or a harddrive via pcmcia */
#define CONFIG_IDE_PCMCIA 1

/* We only support one slot for now */
#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR       CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET     8

/* Offset for normal register accesses  */
#define CONFIG_SYS_ATA_REG_OFFSET      0

/* Offset for alternate registers       */
#define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
#endif /* CONFIG_DBAU1550 */

#endif	/* __CONFIG_H */
Commit	Line	Data
	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	/*
	9	* This file contains the configuration parameters for the dbau1x00 board.
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	#define CONFIG_DBAU1X00 1
	16	#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
	17
	18	#ifdef CONFIG_DBAU1000
	19	/* Also known as Merlot */
	20	#define CONFIG_SOC_AU1000 1
	21	#else
	22	#ifdef CONFIG_DBAU1100
	23	#define CONFIG_SOC_AU1100 1
	24	#else
	25	#ifdef CONFIG_DBAU1500
	26	#define CONFIG_SOC_AU1500 1
	27	#else
	28	#ifdef CONFIG_DBAU1550
	29	/* Cabernet */
	30	#define CONFIG_SOC_AU1550 1
	31	#else
	32	#error "No valid board set"
	33	#endif
	34	#endif
	35	#endif
	36	#endif
	37
	38	/* valid baudrates */
	39
	40	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	41
	42	#define CONFIG_EXTRA_ENV_SETTINGS \
	43	"addmisc=setenv bootargs ${bootargs} " \
	44	"console=ttyS0,${baudrate} " \
	45	"panic=1\0" \
	46	"bootfile=/tftpboot/vmlinux.srec\0" \
	47	"load=tftp 80500000 ${u-boot}\0" \
	48	""
	49
	50	#ifdef CONFIG_DBAU1550
	51	/* Boot from flash by default, revert to bootp */
	52	#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
	53	#else /* CONFIG_DBAU1550 */
	54	#define CONFIG_BOOTCOMMAND "bootp;bootm"
	55	#endif /* CONFIG_DBAU1550 */
	56
	57	/*
	58	* BOOTP options
	59	*/
	60	#define CONFIG_BOOTP_BOOTFILESIZE
	61
	62	/*
	63	* Command line configuration.
	64	*/
	65
	66	/*
	67	* Miscellaneous configurable options
	68	*/
	69
	70	#define CONFIG_SYS_MALLOC_LEN 128*1024
	71
	72	#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
	73
	74	#define CONFIG_SYS_MHZ 396
	75
	76	#if (CONFIG_SYS_MHZ % 12) != 0
	77	#error "Invalid CPU frequency - must be multiple of 12!"
	78	#endif
	79
	80	#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
	81
	82	#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
	83
	84	#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
	85
	86	#define CONFIG_SYS_MEMTEST_START 0x80100000
	87	#define CONFIG_SYS_MEMTEST_END 0x80800000
	88
	89	/*-----------------------------------------------------------------------
	90	* FLASH and environment organization
	91	*/
	92	#ifdef CONFIG_DBAU1550
	93
	94	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	95	#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
	96
	97	#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
	98	#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
	99
	100	#else /* CONFIG_DBAU1550 */
	101
	102	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	103	#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
	104
	105	#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
	106	#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
	107
	108	#endif /* CONFIG_DBAU1550 */
	109
	110	#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
	111
	112	#define CONFIG_SYS_FLASH_CFI 1
	113	#define CONFIG_FLASH_CFI_DRIVER 1
	114
	115	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	116	#define CONFIG_SYS_MONITOR_LEN (192 << 10)
	117
	118	#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
	119
	120	/* We boot from this flash, selected with dip switch */
	121	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
	122
	123	/* timeout values are in ticks */
	124	#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
	125	#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
	126
	127	/* Address and size of Primary Environment Sector */
	128	#define CONFIG_ENV_ADDR 0xB0030000
	129	#define CONFIG_ENV_SIZE 0x10000
	130
	131	#define CONFIG_FLASH_16BIT
	132
	133	#define CONFIG_NR_DRAM_BANKS 2
	134
	135	#ifdef CONFIG_DBAU1550
	136	#define MEM_SIZE 192
	137	#else
	138	#define MEM_SIZE 64
	139	#endif
	140
	141	#define CONFIG_MEMSIZE_IN_BYTES
	142
	143	#ifndef CONFIG_DBAU1550
	144	/---ATA PCMCIA ------------------------------------/
	145	#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
	146	#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
	147	#define CONFIG_PCMCIA_SLOT_A
	148
	149	#define CONFIG_ATAPI 1
	150
	151	/* We run CF in "true ide" mode or a harddrive via pcmcia */
	152	#define CONFIG_IDE_PCMCIA 1
	153
	154	/* We only support one slot for now */
	155	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
	156	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	157
	158	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	159
	160	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	161
	162	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
	163
	164	/* Offset for data I/O */
	165	#define CONFIG_SYS_ATA_DATA_OFFSET 8
	166
	167	/* Offset for normal register accesses */
	168	#define CONFIG_SYS_ATA_REG_OFFSET 0
	169
	170	/* Offset for alternate registers */
	171	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
	172	#endif /* CONFIG_DBAU1550 */
	173
	174	#endif /* __CONFIG_H */