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1 | /* | |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
10 | #define CONFIG_ARMV7_PSCI_1_0 | |
11 | ||
12 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR | |
13 | ||
14 | #define CONFIG_SYS_FSL_CLK | |
15 | ||
16 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
17 | ||
18 | #define CONFIG_DEEP_SLEEP | |
19 | ||
20 | /* | |
21 | * Size of malloc() pool | |
22 | */ | |
23 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
24 | ||
25 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
26 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
27 | ||
28 | #ifndef __ASSEMBLY__ | |
29 | unsigned long get_board_sys_clk(void); | |
30 | unsigned long get_board_ddr_clk(void); | |
31 | #endif | |
32 | ||
33 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
34 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
35 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
36 | #define CONFIG_QIXIS_I2C_ACCESS | |
37 | #else | |
38 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
39 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
40 | #endif | |
41 | ||
42 | #ifdef CONFIG_RAMBOOT_PBL | |
43 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg | |
44 | #endif | |
45 | ||
46 | #ifdef CONFIG_SD_BOOT | |
47 | #ifdef CONFIG_SD_BOOT_QSPI | |
48 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
49 | board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg | |
50 | #else | |
51 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
52 | board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg | |
53 | #endif | |
54 | #define CONFIG_SPL_FRAMEWORK | |
55 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
56 | ||
57 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
58 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
59 | #define CONFIG_SPL_STACK 0x1001d000 | |
60 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
61 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
62 | ||
63 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ | |
64 | CONFIG_SYS_MONITOR_LEN) | |
65 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
66 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
67 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
68 | #define CONFIG_SYS_MONITOR_LEN 0xc0000 | |
69 | #endif | |
70 | ||
71 | #ifdef CONFIG_QSPI_BOOT | |
72 | #define CONFIG_SYS_TEXT_BASE 0x40100000 | |
73 | #endif | |
74 | ||
75 | #ifdef CONFIG_NAND_BOOT | |
76 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | |
77 | #define CONFIG_SPL_FRAMEWORK | |
78 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
79 | ||
80 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
81 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
82 | #define CONFIG_SPL_STACK 0x1001d000 | |
83 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
84 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
85 | ||
86 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) | |
87 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO | |
88 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
89 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
90 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
91 | ||
92 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
93 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
94 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
95 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
96 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
97 | #endif | |
98 | ||
99 | #ifndef CONFIG_SYS_TEXT_BASE | |
100 | #define CONFIG_SYS_TEXT_BASE 0x60100000 | |
101 | #endif | |
102 | ||
103 | #define CONFIG_NR_DRAM_BANKS 1 | |
104 | ||
105 | #define CONFIG_DDR_SPD | |
106 | #define SPD_EEPROM_ADDRESS 0x51 | |
107 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
108 | ||
109 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ | |
110 | #ifndef CONFIG_SYS_FSL_DDR4 | |
111 | #define CONFIG_SYS_DDR_RAW_TIMING | |
112 | #endif | |
113 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
114 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
115 | ||
116 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
117 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
118 | ||
119 | #define CONFIG_DDR_ECC | |
120 | #ifdef CONFIG_DDR_ECC | |
121 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
122 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
123 | #endif | |
124 | ||
125 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ | |
126 | !defined(CONFIG_QSPI_BOOT) | |
127 | #define CONFIG_U_QE | |
128 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
129 | #endif | |
130 | ||
131 | /* | |
132 | * IFC Definitions | |
133 | */ | |
134 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) | |
135 | #define CONFIG_FSL_IFC | |
136 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
137 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
138 | ||
139 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
140 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
141 | CSPR_PORT_SIZE_16 | \ | |
142 | CSPR_MSEL_NOR | \ | |
143 | CSPR_V) | |
144 | #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) | |
145 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
146 | + 0x8000000) | \ | |
147 | CSPR_PORT_SIZE_16 | \ | |
148 | CSPR_MSEL_NOR | \ | |
149 | CSPR_V) | |
150 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
151 | ||
152 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
153 | CSOR_NOR_TRHZ_80) | |
154 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
155 | FTIM0_NOR_TEADC(0x5) | \ | |
156 | FTIM0_NOR_TEAHC(0x5)) | |
157 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
158 | FTIM1_NOR_TRAD_NOR(0x1a) | \ | |
159 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
160 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
161 | FTIM2_NOR_TCH(0x4) | \ | |
162 | FTIM2_NOR_TWPH(0xe) | \ | |
163 | FTIM2_NOR_TWP(0x1c)) | |
164 | #define CONFIG_SYS_NOR_FTIM3 0 | |
165 | ||
166 | #define CONFIG_FLASH_CFI_DRIVER | |
167 | #define CONFIG_SYS_FLASH_CFI | |
168 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
169 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
170 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
171 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
172 | #define CONFIG_SYS_WRITE_SWAPPED_DATA | |
173 | ||
174 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
175 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
176 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
177 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
178 | ||
179 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
180 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ | |
181 | CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} | |
182 | ||
183 | /* | |
184 | * NAND Flash Definitions | |
185 | */ | |
186 | #define CONFIG_NAND_FSL_IFC | |
187 | ||
188 | #define CONFIG_SYS_NAND_BASE 0x7e800000 | |
189 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
190 | ||
191 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
192 | ||
193 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
194 | | CSPR_PORT_SIZE_8 \ | |
195 | | CSPR_MSEL_NAND \ | |
196 | | CSPR_V) | |
197 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
198 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
199 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
200 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
201 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ | |
202 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
203 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | |
204 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ | |
205 | ||
206 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
207 | ||
208 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ | |
209 | FTIM0_NAND_TWP(0x18) | \ | |
210 | FTIM0_NAND_TWCHT(0x7) | \ | |
211 | FTIM0_NAND_TWH(0xa)) | |
212 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
213 | FTIM1_NAND_TWBE(0x39) | \ | |
214 | FTIM1_NAND_TRR(0xe) | \ | |
215 | FTIM1_NAND_TRP(0x18)) | |
216 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ | |
217 | FTIM2_NAND_TREH(0xa) | \ | |
218 | FTIM2_NAND_TWHRE(0x1e)) | |
219 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
220 | ||
221 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
222 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
223 | ||
224 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
225 | #endif | |
226 | ||
227 | /* | |
228 | * QIXIS Definitions | |
229 | */ | |
230 | #define CONFIG_FSL_QIXIS | |
231 | ||
232 | #ifdef CONFIG_FSL_QIXIS | |
233 | #define QIXIS_BASE 0x7fb00000 | |
234 | #define QIXIS_BASE_PHYS QIXIS_BASE | |
235 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
236 | #define QIXIS_LBMAP_SWITCH 6 | |
237 | #define QIXIS_LBMAP_MASK 0x0f | |
238 | #define QIXIS_LBMAP_SHIFT 0 | |
239 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
240 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
241 | #define QIXIS_PWR_CTL 0x21 | |
242 | #define QIXIS_PWR_CTL_POWEROFF 0x80 | |
243 | #define QIXIS_RST_CTL_RESET 0x44 | |
244 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
245 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
246 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
247 | #define QIXIS_CTL_SYS 0x5 | |
248 | #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c | |
249 | #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 | |
250 | #define QIXIS_RST_FORCE_3 0x45 | |
251 | #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 | |
252 | #define QIXIS_PWR_CTL2 0x21 | |
253 | #define QIXIS_PWR_CTL2_PCTL 0x2 | |
254 | ||
255 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
256 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ | |
257 | CSPR_PORT_SIZE_8 | \ | |
258 | CSPR_MSEL_GPCM | \ | |
259 | CSPR_V) | |
260 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
261 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
262 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
263 | CSOR_NOR_TRHZ_80) | |
264 | ||
265 | /* | |
266 | * QIXIS Timing parameters for IFC GPCM | |
267 | */ | |
268 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ | |
269 | FTIM0_GPCM_TEADC(0xe) | \ | |
270 | FTIM0_GPCM_TEAHC(0xe)) | |
271 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ | |
272 | FTIM1_GPCM_TRAD(0x1f)) | |
273 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ | |
274 | FTIM2_GPCM_TCH(0xe) | \ | |
275 | FTIM2_GPCM_TWP(0xf0)) | |
276 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
277 | #endif | |
278 | ||
279 | #if defined(CONFIG_NAND_BOOT) | |
280 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
281 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
282 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
283 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
284 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
285 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
286 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
287 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
288 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
289 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
290 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
291 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
292 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
293 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
294 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
295 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
296 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
297 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
298 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
299 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
300 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
301 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
302 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
303 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
304 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
305 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
306 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
307 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
308 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
309 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
310 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
311 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
312 | #else | |
313 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
314 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
315 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
316 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
317 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
318 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
319 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
320 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
321 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
322 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
323 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
324 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
325 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
326 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
327 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
328 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
329 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
330 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
331 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
332 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
333 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
334 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
335 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
336 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
337 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
338 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
339 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
340 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
341 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
342 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
343 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
344 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
345 | #endif | |
346 | ||
347 | /* | |
348 | * Serial Port | |
349 | */ | |
350 | #ifdef CONFIG_LPUART | |
351 | #define CONFIG_LPUART_32B_REG | |
352 | #else | |
353 | #define CONFIG_CONS_INDEX 1 | |
354 | #define CONFIG_SYS_NS16550_SERIAL | |
355 | #ifndef CONFIG_DM_SERIAL | |
356 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
357 | #endif | |
358 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
359 | #endif | |
360 | ||
361 | /* | |
362 | * I2C | |
363 | */ | |
364 | #define CONFIG_SYS_I2C | |
365 | #define CONFIG_SYS_I2C_MXC | |
366 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ | |
367 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
368 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ | |
369 | ||
370 | /* | |
371 | * I2C bus multiplexer | |
372 | */ | |
373 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
374 | #define I2C_MUX_CH_DEFAULT 0x8 | |
375 | #define I2C_MUX_CH_CH7301 0xC | |
376 | ||
377 | /* | |
378 | * MMC | |
379 | */ | |
380 | #define CONFIG_FSL_ESDHC | |
381 | ||
382 | /* SPI */ | |
383 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
384 | /* QSPI */ | |
385 | #define QSPI0_AMBA_BASE 0x40000000 | |
386 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
387 | #define FSL_QSPI_FLASH_NUM 2 | |
388 | ||
389 | /* DSPI */ | |
390 | ||
391 | /* DM SPI */ | |
392 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) | |
393 | #define CONFIG_DM_SPI_FLASH | |
394 | #define CONFIG_SPI_FLASH_DATAFLASH | |
395 | #endif | |
396 | #endif | |
397 | ||
398 | /* | |
399 | * USB | |
400 | */ | |
401 | /* EHCI Support - disbaled by default */ | |
402 | /*#define CONFIG_HAS_FSL_DR_USB*/ | |
403 | ||
404 | #ifdef CONFIG_HAS_FSL_DR_USB | |
405 | #define CONFIG_USB_EHCI_FSL | |
406 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
407 | #endif | |
408 | ||
409 | /*XHCI Support - enabled by default*/ | |
410 | #define CONFIG_HAS_FSL_XHCI_USB | |
411 | ||
412 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
413 | #define CONFIG_USB_XHCI_FSL | |
414 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 | |
415 | #endif | |
416 | ||
417 | /* | |
418 | * Video | |
419 | */ | |
420 | #ifdef CONFIG_VIDEO_FSL_DCU_FB | |
421 | #define CONFIG_VIDEO_LOGO | |
422 | #define CONFIG_VIDEO_BMP_LOGO | |
423 | ||
424 | #define CONFIG_FSL_DIU_CH7301 | |
425 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 | |
426 | #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 | |
427 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
428 | #endif | |
429 | ||
430 | /* | |
431 | * eTSEC | |
432 | */ | |
433 | #define CONFIG_TSEC_ENET | |
434 | ||
435 | #ifdef CONFIG_TSEC_ENET | |
436 | #define CONFIG_MII | |
437 | #define CONFIG_MII_DEFAULT_TSEC 3 | |
438 | #define CONFIG_TSEC1 1 | |
439 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
440 | #define CONFIG_TSEC2 1 | |
441 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
442 | #define CONFIG_TSEC3 1 | |
443 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
444 | ||
445 | #define TSEC1_PHY_ADDR 1 | |
446 | #define TSEC2_PHY_ADDR 2 | |
447 | #define TSEC3_PHY_ADDR 3 | |
448 | ||
449 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
450 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
451 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
452 | ||
453 | #define TSEC1_PHYIDX 0 | |
454 | #define TSEC2_PHYIDX 0 | |
455 | #define TSEC3_PHYIDX 0 | |
456 | ||
457 | #define CONFIG_ETHPRIME "eTSEC1" | |
458 | ||
459 | #define CONFIG_PHY_REALTEK | |
460 | ||
461 | #define CONFIG_HAS_ETH0 | |
462 | #define CONFIG_HAS_ETH1 | |
463 | #define CONFIG_HAS_ETH2 | |
464 | ||
465 | #define CONFIG_FSL_SGMII_RISER 1 | |
466 | #define SGMII_RISER_PHY_OFFSET 0x1b | |
467 | ||
468 | #ifdef CONFIG_FSL_SGMII_RISER | |
469 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
470 | #endif | |
471 | ||
472 | #endif | |
473 | ||
474 | /* PCIe */ | |
475 | #define CONFIG_PCIE1 /* PCIE controller 1 */ | |
476 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
477 | ||
478 | #ifdef CONFIG_PCI | |
479 | #define CONFIG_PCI_SCAN_SHOW | |
480 | #define CONFIG_CMD_PCI | |
481 | #endif | |
482 | ||
483 | #define CONFIG_CMDLINE_TAG | |
484 | #define CONFIG_CMDLINE_EDITING | |
485 | ||
486 | #define CONFIG_PEN_ADDR_BIG_ENDIAN | |
487 | #define CONFIG_LAYERSCAPE_NS_ACCESS | |
488 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 | |
489 | #define COUNTER_FREQUENCY 12500000 | |
490 | ||
491 | #define CONFIG_HWCONFIG | |
492 | #define HWCONFIG_BUFFER_SIZE 256 | |
493 | ||
494 | #define CONFIG_FSL_DEVICE_DISABLE | |
495 | ||
496 | ||
497 | #define CONFIG_SYS_QE_FW_ADDR 0x60940000 | |
498 | ||
499 | #ifdef CONFIG_LPUART | |
500 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
501 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ | |
502 | "fdt_high=0xffffffff\0" \ | |
503 | "initrd_high=0xffffffff\0" \ | |
504 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" | |
505 | #else | |
506 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
507 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
508 | "fdt_high=0xffffffff\0" \ | |
509 | "initrd_high=0xffffffff\0" \ | |
510 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" | |
511 | #endif | |
512 | ||
513 | /* | |
514 | * Miscellaneous configurable options | |
515 | */ | |
516 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
517 | #define CONFIG_AUTO_COMPLETE | |
518 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
519 | #define CONFIG_SYS_PBSIZE \ | |
520 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
521 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
522 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
523 | ||
524 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
525 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
526 | ||
527 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
528 | ||
529 | #define CONFIG_LS102XA_STREAM_ID | |
530 | ||
531 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
532 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
533 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
534 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
535 | ||
536 | #ifdef CONFIG_SPL_BUILD | |
537 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
538 | #else | |
539 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
540 | #endif | |
541 | ||
542 | /* | |
543 | * Environment | |
544 | */ | |
545 | #define CONFIG_ENV_OVERWRITE | |
546 | ||
547 | #if defined(CONFIG_SD_BOOT) | |
548 | #define CONFIG_ENV_OFFSET 0x300000 | |
549 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
550 | #define CONFIG_ENV_SIZE 0x2000 | |
551 | #elif defined(CONFIG_QSPI_BOOT) | |
552 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
553 | #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ | |
554 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
555 | #elif defined(CONFIG_NAND_BOOT) | |
556 | #define CONFIG_ENV_SIZE 0x2000 | |
557 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
558 | #else | |
559 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) | |
560 | #define CONFIG_ENV_SIZE 0x2000 | |
561 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
562 | #endif | |
563 | ||
564 | #define CONFIG_MISC_INIT_R | |
565 | ||
566 | #include <asm/fsl_secure_boot.h> | |
567 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
568 | ||
569 | #endif |