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1 | /* | |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
10 | #define CONFIG_LS102XA | |
11 | ||
12 | #define CONFIG_ARMV7_PSCI_1_0 | |
13 | ||
14 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR | |
15 | ||
16 | #define CONFIG_SYS_FSL_CLK | |
17 | ||
18 | #define CONFIG_DISPLAY_CPUINFO | |
19 | #define CONFIG_DISPLAY_BOARDINFO | |
20 | ||
21 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
22 | #define CONFIG_BOARD_EARLY_INIT_F | |
23 | #define CONFIG_DEEP_SLEEP | |
24 | #ifdef CONFIG_DEEP_SLEEP | |
25 | #define CONFIG_SILENT_CONSOLE | |
26 | #endif | |
27 | ||
28 | /* | |
29 | * Size of malloc() pool | |
30 | */ | |
31 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
32 | ||
33 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
34 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
35 | ||
36 | /* | |
37 | * USB | |
38 | */ | |
39 | ||
40 | /* | |
41 | * EHCI Support - disbaled by default as | |
42 | * there is no signal coming out of soc on | |
43 | * this board for this controller. However, | |
44 | * the silicon still has this controller, | |
45 | * and anyone can use this controller by | |
46 | * taking signals out on their board. | |
47 | */ | |
48 | ||
49 | /*#define CONFIG_HAS_FSL_DR_USB*/ | |
50 | ||
51 | #ifdef CONFIG_HAS_FSL_DR_USB | |
52 | #define CONFIG_USB_EHCI | |
53 | #define CONFIG_USB_EHCI_FSL | |
54 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
55 | #endif | |
56 | ||
57 | /* XHCI Support - enabled by default */ | |
58 | #define CONFIG_HAS_FSL_XHCI_USB | |
59 | ||
60 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
61 | #define CONFIG_USB_XHCI_FSL | |
62 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 | |
63 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
64 | #endif | |
65 | ||
66 | /* | |
67 | * Generic Timer Definitions | |
68 | */ | |
69 | #define GENERIC_TIMER_CLK 12500000 | |
70 | ||
71 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
72 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
73 | ||
74 | #define DDR_SDRAM_CFG 0x470c0008 | |
75 | #define DDR_CS0_BNDS 0x008000bf | |
76 | #define DDR_CS0_CONFIG 0x80014302 | |
77 | #define DDR_TIMING_CFG_0 0x50550004 | |
78 | #define DDR_TIMING_CFG_1 0xbcb38c56 | |
79 | #define DDR_TIMING_CFG_2 0x0040d120 | |
80 | #define DDR_TIMING_CFG_3 0x010e1000 | |
81 | #define DDR_TIMING_CFG_4 0x00000001 | |
82 | #define DDR_TIMING_CFG_5 0x03401400 | |
83 | #define DDR_SDRAM_CFG_2 0x00401010 | |
84 | #define DDR_SDRAM_MODE 0x00061c60 | |
85 | #define DDR_SDRAM_MODE_2 0x00180000 | |
86 | #define DDR_SDRAM_INTERVAL 0x18600618 | |
87 | #define DDR_DDR_WRLVL_CNTL 0x8655f605 | |
88 | #define DDR_DDR_WRLVL_CNTL_2 0x05060607 | |
89 | #define DDR_DDR_WRLVL_CNTL_3 0x05050505 | |
90 | #define DDR_DDR_CDR1 0x80040000 | |
91 | #define DDR_DDR_CDR2 0x00000001 | |
92 | #define DDR_SDRAM_CLK_CNTL 0x02000000 | |
93 | #define DDR_DDR_ZQ_CNTL 0x89080600 | |
94 | #define DDR_CS0_CONFIG_2 0 | |
95 | #define DDR_SDRAM_CFG_MEM_EN 0x80000000 | |
96 | #define SDRAM_CFG2_D_INIT 0x00000010 | |
97 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 | |
98 | #define SDRAM_CFG2_FRC_SR 0x80000000 | |
99 | #define SDRAM_CFG_BI 0x00000001 | |
100 | ||
101 | #ifdef CONFIG_RAMBOOT_PBL | |
102 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg | |
103 | #endif | |
104 | ||
105 | #ifdef CONFIG_SD_BOOT | |
106 | #ifdef CONFIG_SD_BOOT_QSPI | |
107 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
108 | board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg | |
109 | #else | |
110 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
111 | board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg | |
112 | #endif | |
113 | #define CONFIG_SPL_FRAMEWORK | |
114 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
115 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
116 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
117 | #define CONFIG_SPL_SERIAL_SUPPORT | |
118 | #define CONFIG_SPL_MMC_SUPPORT | |
119 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 | |
120 | ||
121 | #ifdef CONFIG_SECURE_BOOT | |
122 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) | |
123 | /* | |
124 | * HDR would be appended at end of image and copied to DDR along | |
125 | * with U-Boot image. | |
126 | */ | |
127 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ | |
128 | (CONFIG_U_BOOT_HDR_SIZE / 512) | |
129 | #else | |
130 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 | |
131 | #endif /* ifdef CONFIG_SECURE_BOOT */ | |
132 | ||
133 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
134 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
135 | #define CONFIG_SPL_STACK 0x1001d000 | |
136 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
137 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
138 | ||
139 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ | |
140 | CONFIG_SYS_MONITOR_LEN) | |
141 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
142 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
143 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
144 | ||
145 | #ifdef CONFIG_U_BOOT_HDR_SIZE | |
146 | /* | |
147 | * HDR would be appended at end of image and copied to DDR along | |
148 | * with U-Boot image. Here u-boot max. size is 512K. So if binary | |
149 | * size increases then increase this size in case of secure boot as | |
150 | * it uses raw u-boot image instead of fit image. | |
151 | */ | |
152 | #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) | |
153 | #else | |
154 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
155 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ | |
156 | #endif | |
157 | ||
158 | #ifdef CONFIG_QSPI_BOOT | |
159 | #define CONFIG_SYS_TEXT_BASE 0x40010000 | |
160 | #endif | |
161 | ||
162 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
163 | #define CONFIG_SYS_NO_FLASH | |
164 | #endif | |
165 | ||
166 | #ifndef CONFIG_SYS_TEXT_BASE | |
167 | #define CONFIG_SYS_TEXT_BASE 0x60100000 | |
168 | #endif | |
169 | ||
170 | #define CONFIG_NR_DRAM_BANKS 1 | |
171 | #define PHYS_SDRAM 0x80000000 | |
172 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | |
173 | ||
174 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
175 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
176 | ||
177 | #define CONFIG_SYS_HAS_SERDES | |
178 | ||
179 | #define CONFIG_FSL_CAAM /* Enable CAAM */ | |
180 | ||
181 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ | |
182 | !defined(CONFIG_QSPI_BOOT) | |
183 | #define CONFIG_U_QE | |
184 | #endif | |
185 | ||
186 | /* | |
187 | * IFC Definitions | |
188 | */ | |
189 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) | |
190 | #define CONFIG_FSL_IFC | |
191 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
192 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
193 | ||
194 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
195 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
196 | CSPR_PORT_SIZE_16 | \ | |
197 | CSPR_MSEL_NOR | \ | |
198 | CSPR_V) | |
199 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
200 | ||
201 | /* NOR Flash Timing Params */ | |
202 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
203 | CSOR_NOR_TRHZ_80) | |
204 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
205 | FTIM0_NOR_TEADC(0x5) | \ | |
206 | FTIM0_NOR_TAVDS(0x0) | \ | |
207 | FTIM0_NOR_TEAHC(0x5)) | |
208 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
209 | FTIM1_NOR_TRAD_NOR(0x1A) | \ | |
210 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
211 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
212 | FTIM2_NOR_TCH(0x4) | \ | |
213 | FTIM2_NOR_TWP(0x1c) | \ | |
214 | FTIM2_NOR_TWPH(0x0e)) | |
215 | #define CONFIG_SYS_NOR_FTIM3 0 | |
216 | ||
217 | #define CONFIG_FLASH_CFI_DRIVER | |
218 | #define CONFIG_SYS_FLASH_CFI | |
219 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
220 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
221 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
222 | ||
223 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
224 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
225 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
226 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
227 | ||
228 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
229 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } | |
230 | ||
231 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
232 | #define CONFIG_SYS_WRITE_SWAPPED_DATA | |
233 | #endif | |
234 | ||
235 | /* CPLD */ | |
236 | ||
237 | #define CONFIG_SYS_CPLD_BASE 0x7fb00000 | |
238 | #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
239 | ||
240 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
241 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ | |
242 | CSPR_PORT_SIZE_8 | \ | |
243 | CSPR_MSEL_GPCM | \ | |
244 | CSPR_V) | |
245 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
246 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
247 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
248 | CSOR_NOR_TRHZ_80) | |
249 | ||
250 | /* CPLD Timing parameters for IFC GPCM */ | |
251 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ | |
252 | FTIM0_GPCM_TEADC(0xf) | \ | |
253 | FTIM0_GPCM_TEAHC(0xf)) | |
254 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
255 | FTIM1_GPCM_TRAD(0x3f)) | |
256 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
257 | FTIM2_GPCM_TCH(0xf) | \ | |
258 | FTIM2_GPCM_TWP(0xff)) | |
259 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
260 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
261 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
262 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
263 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
264 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
265 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
266 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
267 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
268 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
269 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR | |
270 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK | |
271 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR | |
272 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
273 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
274 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
275 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
276 | ||
277 | /* | |
278 | * Serial Port | |
279 | */ | |
280 | #ifdef CONFIG_LPUART | |
281 | #define CONFIG_LPUART_32B_REG | |
282 | #else | |
283 | #define CONFIG_CONS_INDEX 1 | |
284 | #define CONFIG_SYS_NS16550_SERIAL | |
285 | #ifndef CONFIG_DM_SERIAL | |
286 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
287 | #endif | |
288 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
289 | #endif | |
290 | ||
291 | #define CONFIG_BAUDRATE 115200 | |
292 | ||
293 | /* | |
294 | * I2C | |
295 | */ | |
296 | #define CONFIG_SYS_I2C | |
297 | #define CONFIG_SYS_I2C_MXC | |
298 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ | |
299 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
300 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ | |
301 | ||
302 | /* EEPROM */ | |
303 | #define CONFIG_ID_EEPROM | |
304 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
305 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
306 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 | |
307 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
308 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
309 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
310 | ||
311 | /* | |
312 | * MMC | |
313 | */ | |
314 | #define CONFIG_MMC | |
315 | #define CONFIG_FSL_ESDHC | |
316 | #define CONFIG_GENERIC_MMC | |
317 | ||
318 | #define CONFIG_DOS_PARTITION | |
319 | ||
320 | /* SPI */ | |
321 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
322 | /* QSPI */ | |
323 | #define QSPI0_AMBA_BASE 0x40000000 | |
324 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
325 | #define FSL_QSPI_FLASH_NUM 2 | |
326 | ||
327 | /* DSPI */ | |
328 | #endif | |
329 | ||
330 | /* DM SPI */ | |
331 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) | |
332 | #define CONFIG_DM_SPI_FLASH | |
333 | #endif | |
334 | ||
335 | /* | |
336 | * Video | |
337 | */ | |
338 | #define CONFIG_FSL_DCU_FB | |
339 | ||
340 | #ifdef CONFIG_FSL_DCU_FB | |
341 | #define CONFIG_VIDEO | |
342 | #define CONFIG_CMD_BMP | |
343 | #define CONFIG_CFB_CONSOLE | |
344 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
345 | #define CONFIG_VIDEO_LOGO | |
346 | #define CONFIG_VIDEO_BMP_LOGO | |
347 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
348 | ||
349 | #define CONFIG_FSL_DCU_SII9022A | |
350 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 | |
351 | #define CONFIG_SYS_I2C_DVI_ADDR 0x39 | |
352 | #endif | |
353 | ||
354 | /* | |
355 | * eTSEC | |
356 | */ | |
357 | #define CONFIG_TSEC_ENET | |
358 | ||
359 | #ifdef CONFIG_TSEC_ENET | |
360 | #define CONFIG_MII | |
361 | #define CONFIG_MII_DEFAULT_TSEC 1 | |
362 | #define CONFIG_TSEC1 1 | |
363 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
364 | #define CONFIG_TSEC2 1 | |
365 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
366 | #define CONFIG_TSEC3 1 | |
367 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
368 | ||
369 | #define TSEC1_PHY_ADDR 2 | |
370 | #define TSEC2_PHY_ADDR 0 | |
371 | #define TSEC3_PHY_ADDR 1 | |
372 | ||
373 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
374 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
375 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
376 | ||
377 | #define TSEC1_PHYIDX 0 | |
378 | #define TSEC2_PHYIDX 0 | |
379 | #define TSEC3_PHYIDX 0 | |
380 | ||
381 | #define CONFIG_ETHPRIME "eTSEC1" | |
382 | ||
383 | #define CONFIG_PHY_GIGE | |
384 | #define CONFIG_PHYLIB | |
385 | #define CONFIG_PHY_ATHEROS | |
386 | ||
387 | #define CONFIG_HAS_ETH0 | |
388 | #define CONFIG_HAS_ETH1 | |
389 | #define CONFIG_HAS_ETH2 | |
390 | #endif | |
391 | ||
392 | /* PCIe */ | |
393 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
394 | #define CONFIG_PCIE1 /* PCIE controller 1 */ | |
395 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
396 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ | |
397 | #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" | |
398 | ||
399 | #define CONFIG_SYS_PCI_64BIT | |
400 | ||
401 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
402 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
403 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
404 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
405 | ||
406 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
407 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
408 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
409 | ||
410 | #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 | |
411 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 | |
412 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ | |
413 | ||
414 | #ifdef CONFIG_PCI | |
415 | #define CONFIG_PCI_PNP | |
416 | #define CONFIG_PCI_SCAN_SHOW | |
417 | #define CONFIG_CMD_PCI | |
418 | #endif | |
419 | ||
420 | #define CONFIG_CMDLINE_TAG | |
421 | #define CONFIG_CMDLINE_EDITING | |
422 | ||
423 | #define CONFIG_ARMV7_NONSEC | |
424 | #define CONFIG_ARMV7_VIRT | |
425 | #define CONFIG_PEN_ADDR_BIG_ENDIAN | |
426 | #define CONFIG_LAYERSCAPE_NS_ACCESS | |
427 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 | |
428 | #define CONFIG_TIMER_CLK_FREQ 12500000 | |
429 | ||
430 | #define CONFIG_HWCONFIG | |
431 | #define HWCONFIG_BUFFER_SIZE 256 | |
432 | ||
433 | #define CONFIG_FSL_DEVICE_DISABLE | |
434 | ||
435 | ||
436 | #ifdef CONFIG_LPUART | |
437 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
438 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ | |
439 | "initrd_high=0xffffffff\0" \ | |
440 | "fdt_high=0xffffffff\0" | |
441 | #else | |
442 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
443 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
444 | "initrd_high=0xffffffff\0" \ | |
445 | "fdt_high=0xffffffff\0" | |
446 | #endif | |
447 | ||
448 | /* | |
449 | * Miscellaneous configurable options | |
450 | */ | |
451 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
452 | #define CONFIG_AUTO_COMPLETE | |
453 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
454 | #define CONFIG_SYS_PBSIZE \ | |
455 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
456 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
457 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
458 | ||
459 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
460 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
461 | ||
462 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
463 | ||
464 | #define CONFIG_LS102XA_STREAM_ID | |
465 | ||
466 | /* | |
467 | * Stack sizes | |
468 | * The stack sizes are set up in start.S using the settings below | |
469 | */ | |
470 | #define CONFIG_STACKSIZE (30 * 1024) | |
471 | ||
472 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
473 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
474 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
475 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
476 | ||
477 | #ifdef CONFIG_SPL_BUILD | |
478 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
479 | #else | |
480 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
481 | #endif | |
482 | ||
483 | #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 | |
484 | ||
485 | /* | |
486 | * Environment | |
487 | */ | |
488 | #define CONFIG_ENV_OVERWRITE | |
489 | ||
490 | #if defined(CONFIG_SD_BOOT) | |
491 | #define CONFIG_ENV_OFFSET 0x100000 | |
492 | #define CONFIG_ENV_IS_IN_MMC | |
493 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
494 | #define CONFIG_ENV_SIZE 0x20000 | |
495 | #elif defined(CONFIG_QSPI_BOOT) | |
496 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
497 | #define CONFIG_ENV_SIZE 0x2000 | |
498 | #define CONFIG_ENV_OFFSET 0x100000 | |
499 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
500 | #else | |
501 | #define CONFIG_ENV_IS_IN_FLASH | |
502 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
503 | #define CONFIG_ENV_SIZE 0x20000 | |
504 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
505 | #endif | |
506 | ||
507 | #define CONFIG_MISC_INIT_R | |
508 | ||
509 | /* Hash command with SHA acceleration supported in hardware */ | |
510 | #ifdef CONFIG_FSL_CAAM | |
511 | #define CONFIG_CMD_HASH | |
512 | #define CONFIG_SHA_HW_ACCEL | |
513 | #endif | |
514 | ||
515 | #include <asm/fsl_secure_boot.h> | |
516 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
517 | ||
518 | #endif |