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1 | /* | |
2 | * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> | |
3 | * | |
4 | * (C) Copyright 2004 | |
5 | * Texas Instruments. | |
6 | * Richard Woodruff <r-woodruff2@ti.com> | |
7 | * Kshitij Gupta <kshitij@ti.com> | |
8 | * | |
9 | * Configuration settings for the Freescale i.MX31 PDK board. | |
10 | * | |
11 | * SPDX-License-Identifier: GPL-2.0+ | |
12 | */ | |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
16 | ||
17 | #include <asm/arch/imx-regs.h> | |
18 | ||
19 | /* High Level Configuration Options */ | |
20 | #define CONFIG_MX31 /* This is a mx31 */ | |
21 | ||
22 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
23 | #define CONFIG_SETUP_MEMORY_TAGS | |
24 | #define CONFIG_INITRD_TAG | |
25 | ||
26 | #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS | |
27 | ||
28 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
29 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
30 | #define CONFIG_SPL_MAX_SIZE 2048 | |
31 | ||
32 | #define CONFIG_SPL_TEXT_BASE 0x87dc0000 | |
33 | #define CONFIG_SYS_TEXT_BASE 0x87e00000 | |
34 | ||
35 | #ifndef CONFIG_SPL_BUILD | |
36 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
37 | #endif | |
38 | ||
39 | /* | |
40 | * Size of malloc() pool | |
41 | */ | |
42 | #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) | |
43 | ||
44 | /* | |
45 | * Hardware drivers | |
46 | */ | |
47 | ||
48 | #define CONFIG_MXC_UART | |
49 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
50 | #define CONFIG_MXC_GPIO | |
51 | ||
52 | #define CONFIG_HARD_SPI | |
53 | #define CONFIG_MXC_SPI | |
54 | #define CONFIG_DEFAULT_SPI_BUS 1 | |
55 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) | |
56 | ||
57 | /* PMIC Controller */ | |
58 | #define CONFIG_POWER | |
59 | #define CONFIG_POWER_SPI | |
60 | #define CONFIG_POWER_FSL | |
61 | #define CONFIG_FSL_PMIC_BUS 1 | |
62 | #define CONFIG_FSL_PMIC_CS 2 | |
63 | #define CONFIG_FSL_PMIC_CLK 1000000 | |
64 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) | |
65 | #define CONFIG_FSL_PMIC_BITLEN 32 | |
66 | #define CONFIG_RTC_MC13XXX | |
67 | ||
68 | /* allow to overwrite serial and ethaddr */ | |
69 | #define CONFIG_ENV_OVERWRITE | |
70 | #define CONFIG_CONS_INDEX 1 | |
71 | #define CONFIG_BAUDRATE 115200 | |
72 | ||
73 | /*********************************************************** | |
74 | * Command definition | |
75 | ***********************************************************/ | |
76 | #define CONFIG_CMD_DATE | |
77 | #define CONFIG_CMD_NAND | |
78 | ||
79 | ||
80 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
81 | "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ | |
82 | "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ | |
83 | "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ | |
84 | "bootcmd=run bootcmd_net\0" \ | |
85 | "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ | |
86 | "tftpboot 0x81000000 uImage-mx31; bootm\0" \ | |
87 | "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ | |
88 | "nand erase 0x0 0x40000; " \ | |
89 | "nand write 0x81000000 0x0 0x40000\0" | |
90 | ||
91 | #define CONFIG_SMC911X | |
92 | #define CONFIG_SMC911X_BASE 0xB6000000 | |
93 | #define CONFIG_SMC911X_32_BIT | |
94 | ||
95 | /* | |
96 | * Miscellaneous configurable options | |
97 | */ | |
98 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
99 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
100 | /* max number of command args */ | |
101 | #define CONFIG_SYS_MAXARGS 16 | |
102 | /* Boot Argument Buffer Size */ | |
103 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
104 | ||
105 | /* memtest works on */ | |
106 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
107 | #define CONFIG_SYS_MEMTEST_END 0x80010000 | |
108 | ||
109 | /* default load address */ | |
110 | #define CONFIG_SYS_LOAD_ADDR 0x81000000 | |
111 | ||
112 | #define CONFIG_CMDLINE_EDITING | |
113 | ||
114 | /*----------------------------------------------------------------------- | |
115 | * Physical Memory Map | |
116 | */ | |
117 | #define CONFIG_NR_DRAM_BANKS 1 | |
118 | #define PHYS_SDRAM_1 CSD0_BASE | |
119 | #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) | |
120 | ||
121 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
122 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
123 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
124 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
125 | GENERATED_GBL_DATA_SIZE) | |
126 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
127 | CONFIG_SYS_INIT_RAM_SIZE) | |
128 | ||
129 | /* | |
130 | * environment organization | |
131 | */ | |
132 | #define CONFIG_ENV_IS_IN_NAND | |
133 | #define CONFIG_ENV_OFFSET 0x40000 | |
134 | #define CONFIG_ENV_OFFSET_REDUND 0x60000 | |
135 | #define CONFIG_ENV_SIZE (128 * 1024) | |
136 | ||
137 | /* | |
138 | * NAND driver | |
139 | */ | |
140 | #define CONFIG_NAND_MXC | |
141 | #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR | |
142 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
143 | #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR | |
144 | #define CONFIG_MXC_NAND_HWECC | |
145 | #define CONFIG_SYS_NAND_LARGEPAGE | |
146 | ||
147 | /* NAND configuration for the NAND_SPL */ | |
148 | ||
149 | /* Start copying real U-Boot from the second page */ | |
150 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO | |
151 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 | |
152 | /* Load U-Boot to this address */ | |
153 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
154 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST | |
155 | ||
156 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 | |
157 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
158 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
159 | #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) | |
160 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
161 | ||
162 | /* Configuration of lowlevel_init.S (clocks and SDRAM) */ | |
163 | #define CCM_CCMR_SETUP 0x074B0BF5 | |
164 | #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ | |
165 | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ | |
166 | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ | |
167 | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) | |
168 | #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ | |
169 | PLL_MFN(12)) | |
170 | ||
171 | #define ESDMISC_MDDR_SETUP 0x00000004 | |
172 | #define ESDMISC_MDDR_RESET_DL 0x0000000c | |
173 | #define ESDCFG0_MDDR_SETUP 0x006ac73a | |
174 | ||
175 | #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) | |
176 | #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ | |
177 | ESDCTL_DSIZ(2) | ESDCTL_BL(1)) | |
178 | #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) | |
179 | #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) | |
180 | #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) | |
181 | #define ESDCTL_RW ESDCTL_SETTINGS | |
182 | ||
183 | #endif /* __CONFIG_H */ |