[people/ms/u-boot.git] / include / fpga.h

/*
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <linux/types.h>	       /* for ulong typedef */

#ifndef _FPGA_H_
#define _FPGA_H_

#ifndef CONFIG_MAX_FPGA_DEVICES
#define CONFIG_MAX_FPGA_DEVICES		5
#endif

/* fpga_xxxx function return value definitions */
#define FPGA_SUCCESS		0
#define FPGA_FAIL		-1

/* device numbers must be non-negative */
#define FPGA_INVALID_DEVICE	-1

/* root data type defintions */
typedef enum {			/* typedef fpga_type */
	fpga_min_type,		/* range check value */
	fpga_xilinx,		/* Xilinx Family) */
	fpga_altera,		/* unimplemented */
	fpga_lattice,		/* Lattice family */
	fpga_undefined		/* invalid range check value */
} fpga_type;			/* end, typedef fpga_type */

typedef struct {		/* typedef fpga_desc */
	fpga_type devtype;	/* switch value to select sub-functions */
	void *devdesc;		/* real device descriptor */
} fpga_desc;			/* end, typedef fpga_desc */

typedef struct {                /* typedef fpga_desc */
	unsigned int blocksize;
	char *interface;
	char *dev_part;
	char *filename;
	int fstype;
} fpga_fs_info;

typedef enum {
	BIT_FULL = 0,
	BIT_PARTIAL,
	BIT_NONE = 0xFF,
} bitstream_type;

/* root function definitions */
void fpga_init(void);
int fpga_add(fpga_type devtype, void *desc);
int fpga_count(void);
const fpga_desc *const fpga_get_desc(int devnum);
int fpga_is_partial_data(int devnum, size_t img_len);
int fpga_load(int devnum, const void *buf, size_t bsize,
	      bitstream_type bstype);
int fpga_fsload(int devnum, const void *buf, size_t size,
		fpga_fs_info *fpga_fsinfo);
int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
		       bitstream_type bstype);
int fpga_dump(int devnum, const void *buf, size_t bsize);
int fpga_info(int devnum);
const fpga_desc *const fpga_validate(int devnum, const void *buf,
				     size_t bsize, char *fn);

#endif	/* _FPGA_H_ */
Commit	Line	Data
	1	/*
	2	* (C) Copyright 2002
	3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <linux/types.h> /* for ulong typedef */
	9
	10	#ifndef _FPGA_H_
	11	#define _FPGA_H_
	12
	13	#ifndef CONFIG_MAX_FPGA_DEVICES
	14	#define CONFIG_MAX_FPGA_DEVICES 5
	15	#endif
	16
	17	/* fpga_xxxx function return value definitions */
	18	#define FPGA_SUCCESS 0
	19	#define FPGA_FAIL -1
	20
	21	/* device numbers must be non-negative */
	22	#define FPGA_INVALID_DEVICE -1
	23
	24	/* root data type defintions */
	25	typedef enum { /* typedef fpga_type */
	26	fpga_min_type, /* range check value */
	27	fpga_xilinx, /* Xilinx Family) */
	28	fpga_altera, /* unimplemented */
	29	fpga_lattice, /* Lattice family */
	30	fpga_undefined /* invalid range check value */
	31	} fpga_type; /* end, typedef fpga_type */
	32
	33	typedef struct { /* typedef fpga_desc */
	34	fpga_type devtype; /* switch value to select sub-functions */
	35	void devdesc; / real device descriptor */
	36	} fpga_desc; /* end, typedef fpga_desc */
	37
	38	typedef struct { /* typedef fpga_desc */
	39	unsigned int blocksize;
	40	char *interface;
	41	char *dev_part;
	42	char *filename;
	43	int fstype;
	44	} fpga_fs_info;
	45
	46	typedef enum {
	47	BIT_FULL = 0,
	48	BIT_PARTIAL,
	49	BIT_NONE = 0xFF,
	50	} bitstream_type;
	51
	52	/* root function definitions */
	53	void fpga_init(void);
	54	int fpga_add(fpga_type devtype, void *desc);
	55	int fpga_count(void);
	56	const fpga_desc *const fpga_get_desc(int devnum);
	57	int fpga_is_partial_data(int devnum, size_t img_len);
	58	int fpga_load(int devnum, const void *buf, size_t bsize,
	59	bitstream_type bstype);
	60	int fpga_fsload(int devnum, const void *buf, size_t size,
	61	fpga_fs_info *fpga_fsinfo);
	62	int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
	63	bitstream_type bstype);
	64	int fpga_dump(int devnum, const void *buf, size_t bsize);
	65	int fpga_info(int devnum);
	66	const fpga_desc const fpga_validate(int devnum, const void buf,
	67	size_t bsize, char *fn);
	68
	69	#endif /* _FPGA_H_ */