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2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/compiler.h>
10 #include <linux/kernel.h>
11 #include <linux/log2.h>
12 #include <asm/arcregs.h>
13 #include <asm/cache.h>
15 /* Bit values in IC_CTRL */
16 #define IC_CTRL_CACHE_DISABLE (1 << 0)
18 /* Bit values in DC_CTRL */
19 #define DC_CTRL_CACHE_DISABLE (1 << 0)
20 #define DC_CTRL_INV_MODE_FLUSH (1 << 6)
21 #define DC_CTRL_FLUSH_STATUS (1 << 8)
22 #define CACHE_VER_NUM_MASK 0xF
23 #define SLC_CTRL_SB (1 << 2)
30 * By default that variable will fall into .bss section.
31 * But .bss section is not relocated and so it will be initilized before
32 * relocation but will be used after being zeroed.
34 int l1_line_sz
__section(".data");
35 int dcache_exists
__section(".data");
36 int icache_exists
__section(".data");
38 #define CACHE_LINE_MASK (~(l1_line_sz - 1))
40 #ifdef CONFIG_ISA_ARCV2
41 int slc_line_sz
__section(".data");
42 int slc_exists
__section(".data");
43 int ioc_exists
__section(".data");
45 static unsigned int __before_slc_op(const int op
)
47 unsigned int reg
= reg
;
51 * IM is set by default and implies Flush-n-inv
52 * Clear it here for vanilla inv
54 reg
= read_aux_reg(ARC_AUX_SLC_CTRL
);
55 write_aux_reg(ARC_AUX_SLC_CTRL
, reg
& ~DC_CTRL_INV_MODE_FLUSH
);
61 static void __after_slc_op(const int op
, unsigned int reg
)
63 if (op
& OP_FLUSH
) { /* flush / flush-n-inv both wait */
65 * Make sure "busy" bit reports correct status,
68 read_aux_reg(ARC_AUX_SLC_CTRL
);
69 while (read_aux_reg(ARC_AUX_SLC_CTRL
) &
74 /* Switch back to default Invalidate mode */
76 write_aux_reg(ARC_AUX_SLC_CTRL
, reg
| DC_CTRL_INV_MODE_FLUSH
);
79 static inline void __slc_line_loop(unsigned long paddr
, unsigned long sz
,
85 #define SLC_LINE_MASK (~(slc_line_sz - 1))
87 aux_cmd
= op
& OP_INV
? ARC_AUX_SLC_IVDL
: ARC_AUX_SLC_FLDL
;
89 sz
+= paddr
& ~SLC_LINE_MASK
;
90 paddr
&= SLC_LINE_MASK
;
92 num_lines
= DIV_ROUND_UP(sz
, slc_line_sz
);
94 while (num_lines
-- > 0) {
95 write_aux_reg(aux_cmd
, paddr
);
100 static inline void __slc_entire_op(const int cacheop
)
103 unsigned int ctrl_reg
= __before_slc_op(cacheop
);
105 if (cacheop
& OP_INV
) /* Inv or flush-n-inv use same cmd reg */
106 aux
= ARC_AUX_SLC_INVALIDATE
;
108 aux
= ARC_AUX_SLC_FLUSH
;
110 write_aux_reg(aux
, 0x1);
112 __after_slc_op(cacheop
, ctrl_reg
);
115 static inline void __slc_line_op(unsigned long paddr
, unsigned long sz
,
118 unsigned int ctrl_reg
= __before_slc_op(cacheop
);
119 __slc_line_loop(paddr
, sz
, cacheop
);
120 __after_slc_op(cacheop
, ctrl_reg
);
123 #define __slc_entire_op(cacheop)
124 #define __slc_line_op(paddr, sz, cacheop)
127 #ifdef CONFIG_ISA_ARCV2
128 static void read_decode_cache_bcr_arcv2(void)
132 #ifdef CONFIG_CPU_BIG_ENDIAN
133 unsigned int pad
:24, way
:2, lsz
:2, sz
:4;
135 unsigned int sz
:4, lsz
:2, way
:2, pad
:24;
143 #ifdef CONFIG_CPU_BIG_ENDIAN
144 unsigned int pad
:24, ver
:8;
146 unsigned int ver
:8, pad
:24;
152 sbcr
.word
= read_aux_reg(ARC_BCR_SLC
);
153 if (sbcr
.fields
.ver
) {
154 slc_cfg
.word
= read_aux_reg(ARC_AUX_SLC_CONFIG
);
156 slc_line_sz
= (slc_cfg
.fields
.lsz
== 0) ? 128 : 64;
160 struct bcr_clust_cfg
{
161 #ifdef CONFIG_CPU_BIG_ENDIAN
162 unsigned int pad
:7, c
:1, num_entries
:8, num_cores
:8, ver
:8;
164 unsigned int ver
:8, num_cores
:8, num_entries
:8, c
:1, pad
:7;
170 cbcr
.word
= read_aux_reg(ARC_BCR_CLUSTER
);
176 void read_decode_cache_bcr(void)
178 int dc_line_sz
= 0, ic_line_sz
= 0;
182 #ifdef CONFIG_CPU_BIG_ENDIAN
183 unsigned int pad
:12, line_len
:4, sz
:4, config
:4, ver
:8;
185 unsigned int ver
:8, config
:4, sz
:4, line_len
:4, pad
:12;
191 ibcr
.word
= read_aux_reg(ARC_BCR_IC_BUILD
);
192 if (ibcr
.fields
.ver
) {
194 l1_line_sz
= ic_line_sz
= 8 << ibcr
.fields
.line_len
;
196 panic("Instruction exists but line length is 0\n");
199 dbcr
.word
= read_aux_reg(ARC_BCR_DC_BUILD
);
200 if (dbcr
.fields
.ver
){
202 l1_line_sz
= dc_line_sz
= 16 << dbcr
.fields
.line_len
;
204 panic("Data cache exists but line length is 0\n");
207 if (ic_line_sz
&& dc_line_sz
&& (ic_line_sz
!= dc_line_sz
))
208 panic("Instruction and data cache line lengths differ\n");
211 void cache_init(void)
213 read_decode_cache_bcr();
215 #ifdef CONFIG_ISA_ARCV2
216 read_decode_cache_bcr_arcv2();
219 /* IOC Aperture start is equal to DDR start */
220 unsigned int ap_base
= CONFIG_SYS_SDRAM_BASE
;
221 /* IOC Aperture size is equal to DDR size */
222 long ap_size
= CONFIG_SYS_SDRAM_SIZE
;
225 invalidate_dcache_all();
227 if (!is_power_of_2(ap_size
) || ap_size
< 4096)
228 panic("IOC Aperture size must be power of 2 and bigger 4Kib");
231 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
232 * so setting 0x11 implies 512M, 0x12 implies 1G...
234 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE
,
235 order_base_2(ap_size
/1024) - 2);
238 /* IOC Aperture start must be aligned to the size of the aperture */
239 if (ap_base
% ap_size
!= 0)
240 panic("IOC Aperture start must be aligned to the size of the aperture");
242 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE
, ap_base
>> 12);
243 write_aux_reg(ARC_AUX_IO_COH_PARTIAL
, 1);
244 write_aux_reg(ARC_AUX_IO_COH_ENABLE
, 1);
250 int icache_status(void)
255 if (read_aux_reg(ARC_AUX_IC_CTRL
) & IC_CTRL_CACHE_DISABLE
)
261 void icache_enable(void)
264 write_aux_reg(ARC_AUX_IC_CTRL
, read_aux_reg(ARC_AUX_IC_CTRL
) &
265 ~IC_CTRL_CACHE_DISABLE
);
268 void icache_disable(void)
271 write_aux_reg(ARC_AUX_IC_CTRL
, read_aux_reg(ARC_AUX_IC_CTRL
) |
272 IC_CTRL_CACHE_DISABLE
);
275 #ifndef CONFIG_SYS_DCACHE_OFF
276 void invalidate_icache_all(void)
278 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
279 if (icache_status()) {
280 write_aux_reg(ARC_AUX_IC_IVIC
, 1);
281 read_aux_reg(ARC_AUX_IC_CTRL
); /* blocks */
285 void invalidate_icache_all(void)
290 int dcache_status(void)
295 if (read_aux_reg(ARC_AUX_DC_CTRL
) & DC_CTRL_CACHE_DISABLE
)
301 void dcache_enable(void)
306 write_aux_reg(ARC_AUX_DC_CTRL
, read_aux_reg(ARC_AUX_DC_CTRL
) &
307 ~(DC_CTRL_INV_MODE_FLUSH
| DC_CTRL_CACHE_DISABLE
));
310 void dcache_disable(void)
315 write_aux_reg(ARC_AUX_DC_CTRL
, read_aux_reg(ARC_AUX_DC_CTRL
) |
316 DC_CTRL_CACHE_DISABLE
);
319 #ifndef CONFIG_SYS_DCACHE_OFF
321 * Common Helper for Line Operations on {I,D}-Cache
323 static inline void __cache_line_loop(unsigned long paddr
, unsigned long sz
,
326 unsigned int aux_cmd
;
327 #if (CONFIG_ARC_MMU_VER == 3)
328 unsigned int aux_tag
;
332 if (cacheop
== OP_INV_IC
) {
333 aux_cmd
= ARC_AUX_IC_IVIL
;
334 #if (CONFIG_ARC_MMU_VER == 3)
335 aux_tag
= ARC_AUX_IC_PTAG
;
338 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
339 aux_cmd
= cacheop
& OP_INV
? ARC_AUX_DC_IVDL
: ARC_AUX_DC_FLDL
;
340 #if (CONFIG_ARC_MMU_VER == 3)
341 aux_tag
= ARC_AUX_DC_PTAG
;
345 sz
+= paddr
& ~CACHE_LINE_MASK
;
346 paddr
&= CACHE_LINE_MASK
;
348 num_lines
= DIV_ROUND_UP(sz
, l1_line_sz
);
350 while (num_lines
-- > 0) {
351 #if (CONFIG_ARC_MMU_VER == 3)
352 write_aux_reg(aux_tag
, paddr
);
354 write_aux_reg(aux_cmd
, paddr
);
359 static unsigned int __before_dc_op(const int op
)
365 * IM is set by default and implies Flush-n-inv
366 * Clear it here for vanilla inv
368 reg
= read_aux_reg(ARC_AUX_DC_CTRL
);
369 write_aux_reg(ARC_AUX_DC_CTRL
, reg
& ~DC_CTRL_INV_MODE_FLUSH
);
375 static void __after_dc_op(const int op
, unsigned int reg
)
377 if (op
& OP_FLUSH
) /* flush / flush-n-inv both wait */
378 while (read_aux_reg(ARC_AUX_DC_CTRL
) & DC_CTRL_FLUSH_STATUS
)
381 /* Switch back to default Invalidate mode */
383 write_aux_reg(ARC_AUX_DC_CTRL
, reg
| DC_CTRL_INV_MODE_FLUSH
);
386 static inline void __dc_entire_op(const int cacheop
)
389 unsigned int ctrl_reg
= __before_dc_op(cacheop
);
391 if (cacheop
& OP_INV
) /* Inv or flush-n-inv use same cmd reg */
392 aux
= ARC_AUX_DC_IVDC
;
394 aux
= ARC_AUX_DC_FLSH
;
396 write_aux_reg(aux
, 0x1);
398 __after_dc_op(cacheop
, ctrl_reg
);
401 static inline void __dc_line_op(unsigned long paddr
, unsigned long sz
,
404 unsigned int ctrl_reg
= __before_dc_op(cacheop
);
405 __cache_line_loop(paddr
, sz
, cacheop
);
406 __after_dc_op(cacheop
, ctrl_reg
);
409 #define __dc_entire_op(cacheop)
410 #define __dc_line_op(paddr, sz, cacheop)
411 #endif /* !CONFIG_SYS_DCACHE_OFF */
413 void invalidate_dcache_range(unsigned long start
, unsigned long end
)
415 #ifdef CONFIG_ISA_ARCV2
418 __dc_line_op(start
, end
- start
, OP_INV
);
420 #ifdef CONFIG_ISA_ARCV2
421 if (slc_exists
&& !ioc_exists
)
422 __slc_line_op(start
, end
- start
, OP_INV
);
426 void flush_dcache_range(unsigned long start
, unsigned long end
)
428 #ifdef CONFIG_ISA_ARCV2
431 __dc_line_op(start
, end
- start
, OP_FLUSH
);
433 #ifdef CONFIG_ISA_ARCV2
434 if (slc_exists
&& !ioc_exists
)
435 __slc_line_op(start
, end
- start
, OP_FLUSH
);
439 void flush_cache(unsigned long start
, unsigned long size
)
441 flush_dcache_range(start
, start
+ size
);
444 void invalidate_dcache_all(void)
446 __dc_entire_op(OP_INV
);
448 #ifdef CONFIG_ISA_ARCV2
450 __slc_entire_op(OP_INV
);
454 void flush_dcache_all(void)
456 __dc_entire_op(OP_FLUSH
);
458 #ifdef CONFIG_ISA_ARCV2
460 __slc_entire_op(OP_FLUSH
);