2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arcregs.h>
11 /* Bit values in IC_CTRL */
12 #define IC_CTRL_CACHE_DISABLE (1 << 0)
14 /* Bit values in DC_CTRL */
15 #define DC_CTRL_CACHE_DISABLE (1 << 0)
16 #define DC_CTRL_INV_MODE_FLUSH (1 << 6)
17 #define DC_CTRL_FLUSH_STATUS (1 << 8)
18 #define CACHE_VER_NUM_MASK 0xF
19 #define SLC_CTRL_SB (1 << 2)
21 int icache_status(void)
23 /* If no cache in CPU exit immediately */
24 if (!(read_aux_reg(ARC_BCR_IC_BUILD
) & CACHE_VER_NUM_MASK
))
27 return (read_aux_reg(ARC_AUX_IC_CTRL
) & IC_CTRL_CACHE_DISABLE
) !=
28 IC_CTRL_CACHE_DISABLE
;
31 void icache_enable(void)
33 /* If no cache in CPU exit immediately */
34 if (!(read_aux_reg(ARC_BCR_IC_BUILD
) & CACHE_VER_NUM_MASK
))
37 write_aux_reg(ARC_AUX_IC_CTRL
, read_aux_reg(ARC_AUX_IC_CTRL
) &
38 ~IC_CTRL_CACHE_DISABLE
);
41 void icache_disable(void)
43 /* If no cache in CPU exit immediately */
44 if (!(read_aux_reg(ARC_BCR_IC_BUILD
) & CACHE_VER_NUM_MASK
))
47 write_aux_reg(ARC_AUX_IC_CTRL
, read_aux_reg(ARC_AUX_IC_CTRL
) |
48 IC_CTRL_CACHE_DISABLE
);
51 void invalidate_icache_all(void)
53 /* If no cache in CPU exit immediately */
54 if (!(read_aux_reg(ARC_BCR_IC_BUILD
) & CACHE_VER_NUM_MASK
))
57 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
58 write_aux_reg(ARC_AUX_IC_IVIC
, 1);
61 int dcache_status(void)
63 /* If no cache in CPU exit immediately */
64 if (!(read_aux_reg(ARC_BCR_DC_BUILD
) & CACHE_VER_NUM_MASK
))
67 return (read_aux_reg(ARC_AUX_DC_CTRL
) & DC_CTRL_CACHE_DISABLE
) !=
68 DC_CTRL_CACHE_DISABLE
;
71 void dcache_enable(void)
73 /* If no cache in CPU exit immediately */
74 if (!(read_aux_reg(ARC_BCR_DC_BUILD
) & CACHE_VER_NUM_MASK
))
77 write_aux_reg(ARC_AUX_DC_CTRL
, read_aux_reg(ARC_AUX_DC_CTRL
) &
78 ~(DC_CTRL_INV_MODE_FLUSH
| DC_CTRL_CACHE_DISABLE
));
81 void dcache_disable(void)
83 /* If no cache in CPU exit immediately */
84 if (!(read_aux_reg(ARC_BCR_DC_BUILD
) & CACHE_VER_NUM_MASK
))
87 write_aux_reg(ARC_AUX_DC_CTRL
, read_aux_reg(ARC_AUX_DC_CTRL
) |
88 DC_CTRL_CACHE_DISABLE
);
91 void flush_dcache_all(void)
93 /* If no cache in CPU exit immediately */
94 if (!(read_aux_reg(ARC_BCR_DC_BUILD
) & CACHE_VER_NUM_MASK
))
97 /* Do flush of entire cache */
98 write_aux_reg(ARC_AUX_DC_FLSH
, 1);
101 while (read_aux_reg(ARC_AUX_DC_CTRL
) & DC_CTRL_FLUSH_STATUS
)
105 #ifndef CONFIG_SYS_DCACHE_OFF
106 static void dcache_flush_line(unsigned addr
)
108 #if (CONFIG_ARC_MMU_VER == 3)
109 write_aux_reg(ARC_AUX_DC_PTAG
, addr
);
111 write_aux_reg(ARC_AUX_DC_FLDL
, addr
);
114 while (read_aux_reg(ARC_AUX_DC_CTRL
) & DC_CTRL_FLUSH_STATUS
)
117 #ifndef CONFIG_SYS_ICACHE_OFF
119 * Invalidate I$ for addresses range just flushed from D$.
120 * If we try to execute data flushed above it will be valid/correct
122 #if (CONFIG_ARC_MMU_VER == 3)
123 write_aux_reg(ARC_AUX_IC_PTAG
, addr
);
125 write_aux_reg(ARC_AUX_IC_IVIL
, addr
);
126 #endif /* CONFIG_SYS_ICACHE_OFF */
128 #endif /* CONFIG_SYS_DCACHE_OFF */
130 void flush_dcache_range(unsigned long start
, unsigned long end
)
132 #ifndef CONFIG_SYS_DCACHE_OFF
135 start
= start
& (~(CONFIG_SYS_CACHELINE_SIZE
- 1));
136 end
= end
& (~(CONFIG_SYS_CACHELINE_SIZE
- 1));
138 for (addr
= start
; addr
<= end
; addr
+= CONFIG_SYS_CACHELINE_SIZE
)
139 dcache_flush_line(addr
);
140 #endif /* CONFIG_SYS_DCACHE_OFF */
143 void invalidate_dcache_range(unsigned long start
, unsigned long end
)
145 #ifndef CONFIG_SYS_DCACHE_OFF
148 start
= start
& (~(CONFIG_SYS_CACHELINE_SIZE
- 1));
149 end
= end
& (~(CONFIG_SYS_CACHELINE_SIZE
- 1));
151 for (addr
= start
; addr
<= end
; addr
+= CONFIG_SYS_CACHELINE_SIZE
) {
152 #if (CONFIG_ARC_MMU_VER == 3)
153 write_aux_reg(ARC_AUX_DC_PTAG
, addr
);
155 write_aux_reg(ARC_AUX_DC_IVDL
, addr
);
157 #endif /* CONFIG_SYS_DCACHE_OFF */
160 void invalidate_dcache_all(void)
162 /* If no cache in CPU exit immediately */
163 if (!(read_aux_reg(ARC_BCR_DC_BUILD
) & CACHE_VER_NUM_MASK
))
166 /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
167 write_aux_reg(ARC_AUX_DC_IVDC
, 1);
170 void flush_cache(unsigned long start
, unsigned long size
)
172 flush_dcache_range(start
, start
+ size
);
175 #ifdef CONFIG_ISA_ARCV2
176 void slc_enable(void)
178 /* If SLC ver = 0, no SLC present in CPU */
179 if (!(read_aux_reg(ARC_BCR_SLC
) & 0xff))
182 write_aux_reg(ARC_AUX_SLC_CONTROL
,
183 read_aux_reg(ARC_AUX_SLC_CONTROL
) & ~1);
186 void slc_disable(void)
188 /* If SLC ver = 0, no SLC present in CPU */
189 if (!(read_aux_reg(ARC_BCR_SLC
) & 0xff))
192 write_aux_reg(ARC_AUX_SLC_CONTROL
,
193 read_aux_reg(ARC_AUX_SLC_CONTROL
) | 1);
198 /* If SLC ver = 0, no SLC present in CPU */
199 if (!(read_aux_reg(ARC_BCR_SLC
) & 0xff))
202 write_aux_reg(ARC_AUX_SLC_FLUSH
, 1);
205 while (read_aux_reg(ARC_AUX_SLC_CONTROL
) & SLC_CTRL_SB
)
209 void slc_invalidate(void)
211 /* If SLC ver = 0, no SLC present in CPU */
212 if (!(read_aux_reg(ARC_BCR_SLC
) & 0xff))
215 write_aux_reg(ARC_AUX_SLC_INVALIDATE
, 1);
218 #endif /* CONFIG_ISA_ARCV2 */