arch/arm/include/asm/arch-omap5/clock.h

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  *      Aneesh V <aneesh@ti.com>
   6  *      Sricharan R <r.sricharan@ti.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10 #ifndef _CLOCKS_OMAP5_H_
  11 #define _CLOCKS_OMAP5_H_
  12 #include <common.h>
  13 #include <asm/omap_common.h>
  14
  15 /*
  16  * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
  17  * loop, allow for a minimum of 2 ms wait (in reality the wait will be
  18  * much more than that)
  19  */
  20 #define LDELAY          1000000
  21
  22 /* CM_DLL_CTRL */
  23 #define CM_DLL_CTRL_OVERRIDE_SHIFT              0
  24 #define CM_DLL_CTRL_OVERRIDE_MASK               (1 << 0)
  25 #define CM_DLL_CTRL_NO_OVERRIDE                 0
  26
  27 /* CM_CLKMODE_DPLL */
  28 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT          11
  29 #define CM_CLKMODE_DPLL_REGM4XEN_MASK           (1 << 11)
  30 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT         10
  31 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK          (1 << 10)
  32 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT    9
  33 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK     (1 << 9)
  34 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT     8
  35 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK      (1 << 8)
  36 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT         5
  37 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK          (0x7 << 5)
  38 #define CM_CLKMODE_DPLL_EN_SHIFT                0
  39 #define CM_CLKMODE_DPLL_EN_MASK                 (0x7 << 0)
  40
  41 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT           0
  42 #define CM_CLKMODE_DPLL_DPLL_EN_MASK            7
  43
  44 #define DPLL_EN_STOP                    1
  45 #define DPLL_EN_MN_BYPASS               4
  46 #define DPLL_EN_LOW_POWER_BYPASS        5
  47 #define DPLL_EN_FAST_RELOCK_BYPASS      6
  48 #define DPLL_EN_LOCK                    7
  49
  50 /* CM_IDLEST_DPLL fields */
  51 #define ST_DPLL_CLK_MASK                1
  52
  53 /* SGX */
  54 #define CLKSEL_GPU_HYD_GCLK_MASK                (1 << 25)
  55 #define CLKSEL_GPU_CORE_GCLK_MASK               (1 << 24)
  56
  57 /* CM_CLKSEL_DPLL */
  58 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT        24
  59 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK         (0xFF << 24)
  60 #define CM_CLKSEL_DPLL_M_SHIFT                  8
  61 #define CM_CLKSEL_DPLL_M_MASK                   (0x7FF << 8)
  62 #define CM_CLKSEL_DPLL_N_SHIFT                  0
  63 #define CM_CLKSEL_DPLL_N_MASK                   0x7F
  64 #define CM_CLKSEL_DCC_EN_SHIFT                  22
  65 #define CM_CLKSEL_DCC_EN_MASK                   (1 << 22)
  66
  67 /* CM_SYS_CLKSEL */
  68 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
  69
  70 /* CM_CLKSEL_CORE */
  71 #define CLKSEL_CORE_SHIFT       0
  72 #define CLKSEL_L3_SHIFT         4
  73 #define CLKSEL_L4_SHIFT         8
  74
  75 #define CLKSEL_CORE_X2_DIV_1    0
  76 #define CLKSEL_L3_CORE_DIV_2    1
  77 #define CLKSEL_L4_L3_DIV_2      1
  78
  79 /* CM_ABE_PLL_REF_CLKSEL */
  80 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT      0
  81 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK       1
  82 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK     0
  83 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK     1
  84
  85 /* CM_CLKSEL_ABE_PLL_SYS */
  86 #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT      0
  87 #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK       1
  88 #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1           0
  89 #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2           1
  90
  91 /* CM_BYPCLK_DPLL_IVA */
  92 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT         0
  93 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK          3
  94
  95 #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2           1
  96
  97 /* CM_SHADOW_FREQ_CONFIG1 */
  98 #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK    1
  99 #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK   4
 100 #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK      8
 101
 102 #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT       8
 103 #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK        (7 << 8)
 104
 105 #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT        11
 106 #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK         (0x1F << 11)
 107
 108 /*CM_<clock_domain>__CLKCTRL */
 109 #define CD_CLKCTRL_CLKTRCTRL_SHIFT              0
 110 #define CD_CLKCTRL_CLKTRCTRL_MASK               3
 111
 112 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP           0
 113 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP           1
 114 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP            2
 115 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO            3
 116
 117
 118 /* CM_<clock_domain>_<module>_CLKCTRL */
 119 #define MODULE_CLKCTRL_MODULEMODE_SHIFT         0
 120 #define MODULE_CLKCTRL_MODULEMODE_MASK          3
 121 #define MODULE_CLKCTRL_IDLEST_SHIFT             16
 122 #define MODULE_CLKCTRL_IDLEST_MASK              (3 << 16)
 123
 124 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE            0
 125 #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO               1
 126 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN        2
 127
 128 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL  0
 129 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING     1
 130 #define MODULE_CLKCTRL_IDLEST_IDLE              2
 131 #define MODULE_CLKCTRL_IDLEST_DISABLED          3
 132
 133 /* CM_L4PER_GPIO4_CLKCTRL */
 134 #define GPIO4_CLKCTRL_OPTFCLKEN_MASK            (1 << 8)
 135
 136 /* CM_L3INIT_HSMMCn_CLKCTRL */
 137 #define HSMMC_CLKCTRL_CLKSEL_MASK               (1 << 24)
 138 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK           (3 << 25)
 139
 140 /* CM_L3INIT_SATA_CLKCTRL */
 141 #define SATA_CLKCTRL_OPTFCLKEN_MASK             (1 << 8)
 142
 143 /* CM_WKUP_GPTIMER1_CLKCTRL */
 144 #define GPTIMER1_CLKCTRL_CLKSEL_MASK            (1 << 24)
 145
 146 /* CM_CAM_ISS_CLKCTRL */
 147 #define ISS_CLKCTRL_OPTFCLKEN_MASK              (1 << 8)
 148
 149 /* CM_DSS_DSS_CLKCTRL */
 150 #define DSS_CLKCTRL_OPTFCLKEN_MASK              0xF00
 151
 152 /* CM_L3INIT_USBPHY_CLKCTRL */
 153 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK   8
 154
 155 /* CM_L3INIT_USB_HOST_HS_CLKCTRL */
 156 #define OPTFCLKEN_FUNC48M_CLK                   (1 << 15)
 157 #define OPTFCLKEN_HSIC480M_P2_CLK               (1 << 14)
 158 #define OPTFCLKEN_HSIC480M_P1_CLK               (1 << 13)
 159 #define OPTFCLKEN_HSIC60M_P2_CLK                (1 << 12)
 160 #define OPTFCLKEN_HSIC60M_P1_CLK                (1 << 11)
 161 #define OPTFCLKEN_UTMI_P3_CLK                   (1 << 10)
 162 #define OPTFCLKEN_UTMI_P2_CLK                   (1 << 9)
 163 #define OPTFCLKEN_UTMI_P1_CLK                   (1 << 8)
 164 #define OPTFCLKEN_HSIC480M_P3_CLK               (1 << 7)
 165 #define OPTFCLKEN_HSIC60M_P3_CLK                (1 << 6)
 166
 167 /* CM_L3INIT_USB_TLL_HS_CLKCTRL */
 168 #define OPTFCLKEN_USB_CH0_CLK_ENABLE    (1 << 8)
 169 #define OPTFCLKEN_USB_CH1_CLK_ENABLE    (1 << 9)
 170 #define OPTFCLKEN_USB_CH2_CLK_ENABLE    (1 << 10)
 171
 172 /* CM_COREAON_USB_PHY_CORE_CLKCTRL */
 173 #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K    (1 << 8)
 174
 175 /* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */
 176 #define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK      (1 << 8)
 177
 178 /* CM_L3INIT_USB_OTG_SS_CLKCTRL */
 179 #define OTG_SS_CLKCTRL_MODULEMODE_HW    (1 << 0)
 180 #define OPTFCLKEN_REFCLK960M                    (1 << 8)
 181
 182 /* CM_L3INIT_OCP2SCP1_CLKCTRL */
 183 #define OCP2SCP1_CLKCTRL_MODULEMODE_HW  (1 << 0)
 184
 185 /* CM_MPU_MPU_CLKCTRL */
 186 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT  24
 187 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK   (3 << 24)
 188 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT   26
 189 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK    (1 << 26)
 190
 191 /* CM_WKUPAON_SCRM_CLKCTRL */
 192 #define OPTFCLKEN_SCRM_PER_SHIFT                9
 193 #define OPTFCLKEN_SCRM_PER_MASK                 (1 << 9)
 194 #define OPTFCLKEN_SCRM_CORE_SHIFT               8
 195 #define OPTFCLKEN_SCRM_CORE_MASK                (1 << 8)
 196
 197 /* CM_COREAON_IO_SRCOMP_CLKCTRL */
 198 #define OPTFCLKEN_SRCOMP_FCLK_SHIFT             8
 199 #define OPTFCLKEN_SRCOMP_FCLK_MASK              (1 << 8)
 200
 201 /* PRM_RSTTIME */
 202 #define RSTTIME1_SHIFT                          0
 203 #define RSTTIME1_MASK                           (0x3ff << 0)
 204
 205 /* Clock frequencies */
 206 #define OMAP_SYS_CLK_IND_38_4_MHZ       6
 207
 208 /* PRM_VC_VAL_BYPASS */
 209 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ     400
 210
 211 /* CTRL_CORE_SRCOMP_NORTH_SIDE */
 212 #define USB2PHY_DISCHGDET       (1 << 29)
 213 #define USB2PHY_AUTORESUME_EN (1 << 30)
 214
 215 /* SMPS */
 216 #define SMPS_I2C_SLAVE_ADDR     0x12
 217 #define SMPS_REG_ADDR_12_MPU    0x23
 218 #define SMPS_REG_ADDR_45_IVA    0x2B
 219 #define SMPS_REG_ADDR_8_CORE    0x37
 220
 221 /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
 222 /* ES1.0 settings */
 223 #define VDD_MPU         1040
 224 #define VDD_MM          1040
 225 #define VDD_CORE        1040
 226
 227 #define VDD_MPU_LOW     890
 228 #define VDD_MM_LOW      890
 229 #define VDD_CORE_LOW    890
 230
 231 /* ES2.0 settings */
 232 #define VDD_MPU_ES2     1060
 233 #define VDD_MM_ES2      1025
 234 #define VDD_CORE_ES2    1040
 235
 236 #define VDD_MPU_ES2_HIGH 1250
 237 #define VDD_MM_ES2_OD  1120
 238
 239 /* Efuse register offsets for OMAP5 platform */
 240 #define OMAP5_ES2_EFUSE_BASE    0x4A002000
 241 #define OMAP5_ES2_PROD_REGBITS  16
 242
 243 /* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */
 244 #define OMAP5_ES2_PROD_CORE_OPNO_VMIN   (OMAP5_ES2_EFUSE_BASE + 0x1D8)
 245
 246 /* CONTROL_STD_FUSE_OPP_VDD_MM_4 */
 247 #define OMAP5_ES2_PROD_MM_OPNO_VMIN     (OMAP5_ES2_EFUSE_BASE + 0x1A4)
 248 /* CONTROL_STD_FUSE_OPP_VDD_MM_5 */
 249 #define OMAP5_ES2_PROD_MM_OPOD_VMIN     (OMAP5_ES2_EFUSE_BASE + 0x1A8)
 250 /* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */
 251 #define OMAP5_ES2_PROD_MPU_OPNO_VMIN    (OMAP5_ES2_EFUSE_BASE + 0x1C4)
 252 /* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */
 253 #define OMAP5_ES2_PROD_MPU_OPHI_VMIN    (OMAP5_ES2_EFUSE_BASE + 0x1C8)
 254
 255 /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
 256 #define VDD_MPU_DRA7_NOM        1150
 257 #define VDD_CORE_DRA7_NOM       1150
 258 #define VDD_EVE_DRA7_NOM        1060
 259 #define VDD_GPU_DRA7_NOM        1060
 260 #define VDD_IVA_DRA7_NOM        1060
 261
 262 /* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
 263 #define VDD_EVE_DRA7_OD         1150
 264 #define VDD_GPU_DRA7_OD         1150
 265 #define VDD_IVA_DRA7_OD         1150
 266
 267 /* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
 268 #define VDD_EVE_DRA7_HIGH       1250
 269 #define VDD_GPU_DRA7_HIGH       1250
 270 #define VDD_IVA_DRA7_HIGH       1250
 271
 272 /* Efuse register offsets for DRA7xx platform */
 273 #define DRA752_EFUSE_BASE       0x4A002000
 274 #define DRA752_EFUSE_REGBITS    16
 275 /* STD_FUSE_OPP_VMIN_IVA_2 */
 276 #define STD_FUSE_OPP_VMIN_IVA_NOM       (DRA752_EFUSE_BASE + 0x05CC)
 277 /* STD_FUSE_OPP_VMIN_IVA_3 */
 278 #define STD_FUSE_OPP_VMIN_IVA_OD        (DRA752_EFUSE_BASE + 0x05D0)
 279 /* STD_FUSE_OPP_VMIN_IVA_4 */
 280 #define STD_FUSE_OPP_VMIN_IVA_HIGH      (DRA752_EFUSE_BASE + 0x05D4)
 281 /* STD_FUSE_OPP_VMIN_DSPEVE_2 */
 282 #define STD_FUSE_OPP_VMIN_DSPEVE_NOM    (DRA752_EFUSE_BASE + 0x05E0)
 283 /* STD_FUSE_OPP_VMIN_DSPEVE_3 */
 284 #define STD_FUSE_OPP_VMIN_DSPEVE_OD     (DRA752_EFUSE_BASE + 0x05E4)
 285 /* STD_FUSE_OPP_VMIN_DSPEVE_4 */
 286 #define STD_FUSE_OPP_VMIN_DSPEVE_HIGH   (DRA752_EFUSE_BASE + 0x05E8)
 287 /* STD_FUSE_OPP_VMIN_CORE_2 */
 288 #define STD_FUSE_OPP_VMIN_CORE_NOM      (DRA752_EFUSE_BASE + 0x05F4)
 289 /* STD_FUSE_OPP_VMIN_GPU_2 */
 290 #define STD_FUSE_OPP_VMIN_GPU_NOM       (DRA752_EFUSE_BASE + 0x1B08)
 291 /* STD_FUSE_OPP_VMIN_GPU_3 */
 292 #define STD_FUSE_OPP_VMIN_GPU_OD        (DRA752_EFUSE_BASE + 0x1B0C)
 293 /* STD_FUSE_OPP_VMIN_GPU_4 */
 294 #define STD_FUSE_OPP_VMIN_GPU_HIGH      (DRA752_EFUSE_BASE + 0x1B10)
 295 /* STD_FUSE_OPP_VMIN_MPU_2 */
 296 #define STD_FUSE_OPP_VMIN_MPU_NOM       (DRA752_EFUSE_BASE + 0x1B20)
 297 /* STD_FUSE_OPP_VMIN_MPU_3 */
 298 #define STD_FUSE_OPP_VMIN_MPU_OD        (DRA752_EFUSE_BASE + 0x1B24)
 299 /* STD_FUSE_OPP_VMIN_MPU_4 */
 300 #define STD_FUSE_OPP_VMIN_MPU_HIGH      (DRA752_EFUSE_BASE + 0x1B28)
 301
 302 #if defined(CONFIG_DRA7_MPU_OPP_HIGH)
 303 #define DRA7_MPU_OPP    OPP_HIGH
 304 #elif defined(CONFIG_DRA7_MPU_OPP_OD)
 305 #define DRA7_MPU_OPP    OPP_OD
 306 #else /* OPP_NOM default */
 307 #define DRA7_MPU_OPP    OPP_NOM
 308 #endif
 309
 310 /* OPP_NOM only available option for CORE */
 311 #define DRA7_CORE_OPP   OPP_NOM
 312
 313 #if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH)
 314 #define DRA7_DSPEVE_OPP OPP_HIGH
 315 #elif defined(CONFIG_DRA7_DSPEVE_OPP_OD)
 316 #define DRA7_DSPEVE_OPP OPP_OD
 317 #else /* OPP_NOM default */
 318 #define DRA7_DSPEVE_OPP OPP_NOM
 319 #endif
 320
 321 #if defined(CONFIG_DRA7_IVA_OPP_HIGH)
 322 #define DRA7_IVA_OPP    OPP_HIGH
 323 #elif defined(CONFIG_DRA7_IVA_OPP_OD)
 324 #define DRA7_IVA_OPP    OPP_OD
 325 #else /* OPP_NOM default */
 326 #define DRA7_IVA_OPP    OPP_NOM
 327 #endif
 328
 329 #if defined(CONFIG_DRA7_GPU_OPP_HIGH)
 330 #define DRA7_GPU_OPP    OPP_HIGH
 331 #elif defined(CONFIG_DRA7_GPU_OPP_OD)
 332 #define DRA7_GPU_OPP    OPP_OD
 333 #else /* OPP_NOM default */
 334 #define DRA7_GPU_OPP    OPP_NOM
 335 #endif
 336
 337 /* Standard offset is 0.5v expressed in uv */
 338 #define PALMAS_SMPS_BASE_VOLT_UV 500000
 339
 340 /* Offset is 0.73V for LP873x */
 341 #define LP873X_BUCK_BASE_VOLT_UV                730000
 342
 343 /* Offset is 0.73V for LP87565 */
 344 #define LP87565_BUCK_BASE_VOLT_UV               730000
 345
 346 /* TPS659038 */
 347 #define TPS659038_I2C_SLAVE_ADDR                0x58
 348 #define TPS659038_REG_ADDR_SMPS12               0x23
 349 #define TPS659038_REG_ADDR_SMPS45               0x2B
 350 #define TPS659038_REG_ADDR_SMPS6                0x2F
 351 #define TPS659038_REG_ADDR_SMPS7                0x33
 352 #define TPS659038_REG_ADDR_SMPS8                0x37
 353
 354 /* TPS65917 */
 355 #define TPS65917_I2C_SLAVE_ADDR         0x58
 356 #define TPS65917_REG_ADDR_SMPS1         0x23
 357 #define TPS65917_REG_ADDR_SMPS2         0x27
 358 #define TPS65917_REG_ADDR_SMPS3         0x2F
 359 #define TPS65917_REG_ADDR_SMPS4         0x33
 360
 361 /* LP873X */
 362 #define LP873X_I2C_SLAVE_ADDR           0x60
 363 #define LP873X_REG_ADDR_BUCK0           0x6
 364 #define LP873X_REG_ADDR_BUCK1           0x7
 365 #define LP873X_REG_ADDR_LDO1            0xA
 366
 367 /* LP87565 */
 368 #define LP87565_I2C_SLAVE_ADDR          0x61
 369 #define LP87565_REG_ADDR_BUCK01         0xA
 370 #define LP87565_REG_ADDR_BUCK23         0xE
 371
 372 /* TPS */
 373 #define TPS62361_I2C_SLAVE_ADDR         0x60
 374 #define TPS62361_REG_ADDR_SET0          0x0
 375 #define TPS62361_REG_ADDR_SET1          0x1
 376 #define TPS62361_REG_ADDR_SET2          0x2
 377 #define TPS62361_REG_ADDR_SET3          0x3
 378 #define TPS62361_REG_ADDR_CTRL          0x4
 379 #define TPS62361_REG_ADDR_TEMP          0x5
 380 #define TPS62361_REG_ADDR_RMP_CTRL      0x6
 381 #define TPS62361_REG_ADDR_CHIP_ID       0x8
 382 #define TPS62361_REG_ADDR_CHIP_ID_2     0x9
 383
 384 #define TPS62361_BASE_VOLT_MV   500
 385 #define TPS62361_VSEL0_GPIO     7
 386
 387 /* Defines for DPLL setup */
 388 #define DPLL_LOCKED_FREQ_TOLERANCE_0            0
 389 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ      500
 390 #define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ        1000
 391
 392 #define DPLL_NO_LOCK    0
 393 #define DPLL_LOCK       1
 394
 395 #if defined(CONFIG_DRA7XX)
 396 #define V_OSCK                  20000000        /* Clock output from T2 */
 397 #else
 398 #define V_OSCK                  19200000        /* Clock output from T2 */
 399 #endif
 400
 401 #define V_SCLK  V_OSCK
 402
 403 /* CKO buffer control */
 404 #define CKOBUFFER_CLK_ENABLE_MASK       (1 << 28)
 405
 406 /* AUXCLKx reg fields */
 407 #define AUXCLK_ENABLE_MASK              (1 << 8)
 408 #define AUXCLK_SRCSELECT_SHIFT          1
 409 #define AUXCLK_SRCSELECT_MASK           (3 << 1)
 410 #define AUXCLK_CLKDIV_SHIFT             16
 411 #define AUXCLK_CLKDIV_MASK              (0xF << 16)
 412
 413 #define AUXCLK_SRCSELECT_SYS_CLK        0
 414 #define AUXCLK_SRCSELECT_CORE_DPLL      1
 415 #define AUXCLK_SRCSELECT_PER_DPLL       2
 416 #define AUXCLK_SRCSELECT_ALTERNATE      3
 417
 418 #endif /* _CLOCKS_OMAP5_H_ */