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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/include/asm/arch-omap5/sys_proto.h
3 * Texas Instruments, <www.ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/omap.h>
13 #include <asm/arch/clock.h>
14 #include <asm/omap_common.h>
15 #include <linux/mtd/omap_gpmc.h>
16 #include <asm/arch/clock.h>
17 #include <asm/ti-common/sys_proto.h>
19 DECLARE_GLOBAL_DATA_PTR
;
22 * Structure for Iodelay configuration registers.
23 * Theoretical max for g_delay is 21560 ps.
24 * Theoretical max for a_delay is 1/3rd of g_delay max.
25 * So using u16 for both a/g_delay.
27 struct iodelay_cfg_entry
{
33 struct pad_conf_entry
{
38 struct mmc_platform_fixups
{
47 extern const struct omap_sysinfo sysinfo
;
50 void watchdog_init(void);
51 u32
get_device_type(void);
52 void do_set_mux(u32 base
, struct pad_conf_entry
const *array
, int size
);
53 void do_set_mux32(u32 base
, struct pad_conf_entry
const *array
, int size
);
54 void set_muxconf_regs(void);
55 u32
wait_on_value(u32
, u32
, void *, u32
);
56 void sdelay(unsigned long);
57 void setup_early_clocks(void);
59 void do_board_detect(void);
60 void vcores_init(void);
61 void bypass_dpll(u32
const base
);
62 void freq_update_core(void);
63 u32
get_sys_clk_freq(void);
64 u32
omap5_ddr_clk(void);
65 void cancel_out(u32
*num
, u32
*den
, u32 den_limit
);
66 void sdram_init(void);
67 u32
omap_sdram_size(void);
69 void save_omap_boot_params(void);
70 void init_omap_revision(void);
71 void init_package_revision(void);
72 void do_io_settings(void);
73 void sri2c_init(void);
74 int omap_vc_bypass_send_value(u8 sa
, u8 reg_addr
, u8 reg_data
);
76 void force_emif_self_refresh(void);
77 void get_ioregs(const struct ctrl_ioregs
**regs
);
78 void srcomp_enable(void);
79 void setup_warmreset_time(void);
80 const struct mmc_platform_fixups
*platform_fixups_mmc(uint32_t addr
);
82 static inline u32
div_round_up(u32 num
, u32 den
)
84 return (num
+ den
- 1)/den
;
87 static inline u32
usec_to_32k(u32 usec
)
89 return div_round_up(32768 * usec
, 1000000);
92 #define OMAP5_SERVICE_L2ACTLR_SET 0x104
93 #define OMAP5_SERVICE_ACR_SET 0x107