arch/powerpc/cpu/ppc4xx/4xx_uart.c

   1 /*
   2  * (C) Copyright 2000-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2010
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0 IBM-pibs
   9  */
  10
  11 #include <common.h>
  12 #include <asm/processor.h>
  13 #include <asm/io.h>
  14 #include <watchdog.h>
  15 #include <asm/ppc4xx.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #if defined(CONFIG_405GP) || \
  20     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
  21     defined(CONFIG_405EX) || defined(CONFIG_440)
  22
  23 #if defined(CONFIG_440)
  24
  25 #if defined(CONFIG_440GP)
  26 #define CR0_MASK        0x3fff0000
  27 #define CR0_EXTCLK_ENA  0x00600000
  28 #define CR0_UDIV_POS    16
  29 #define UDIV_SUBTRACT   1
  30 #define UART0_SDR       CPC0_CR0
  31 #define MFREG(a, d)     d = mfdcr(a)
  32 #define MTREG(a, d)     mtdcr(a, d)
  33 #else /* #if defined(CONFIG_440GP) */
  34 /* all other 440 PPC's access clock divider via sdr register */
  35 #define CR0_MASK        0xdfffffff
  36 #define CR0_EXTCLK_ENA  0x00800000
  37 #define CR0_UDIV_POS    0
  38 #define UDIV_SUBTRACT   0
  39 #define UART0_SDR       SDR0_UART0
  40 #define UART1_SDR       SDR0_UART1
  41 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  42     defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  43     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  44     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  45 #define UART2_SDR       SDR0_UART2
  46 #endif
  47 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  48     defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  49     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  50 #define UART3_SDR       SDR0_UART3
  51 #endif
  52 #define MFREG(a, d)     mfsdr(a, d)
  53 #define MTREG(a, d)     mtsdr(a, d)
  54 #endif /* #if defined(CONFIG_440GP) */
  55 #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
  56 #define UCR0_MASK       0x0000007f
  57 #define UCR1_MASK       0x00007f00
  58 #define UCR0_UDIV_POS   0
  59 #define UCR1_UDIV_POS   8
  60 #define UDIV_MAX        127
  61 #elif defined(CONFIG_405EX)
  62 #define MFREG(a, d)     mfsdr(a, d)
  63 #define MTREG(a, d)     mtsdr(a, d)
  64 #define CR0_MASK        0x000000ff
  65 #define CR0_EXTCLK_ENA  0x00800000
  66 #define CR0_UDIV_POS    0
  67 #define UDIV_SUBTRACT   0
  68 #define UART0_SDR       SDR0_UART0
  69 #define UART1_SDR       SDR0_UART1
  70 #else /* CONFIG_405GP */
  71 #define CR0_MASK        0x00001fff
  72 #define CR0_EXTCLK_ENA  0x000000c0
  73 #define CR0_UDIV_POS    1
  74 #define UDIV_MAX        32
  75 #endif
  76
  77 #if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
  78 #error "External serial clock not supported on AMCC PPC405EP!"
  79 #endif
  80
  81 #if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) ||  \
  82      defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
  83 /*
  84  * For some SoC's, the cpu clock is on divider chain A, UART on
  85  * divider chain B ... so cpu clock is irrelevant. Get the
  86  * "optimized" values that are subject to the 1/2 opb clock
  87  * constraint.
  88  */
  89 static u16 serial_bdiv(int baudrate, u32 *udiv)
  90 {
  91         sys_info_t sysinfo;
  92         u32 div;                /* total divisor udiv * bdiv */
  93         u32 umin;               /* minimum udiv */
  94         u16 diff;               /* smallest diff */
  95         u16 idiff;              /* current diff */
  96         u16 ibdiv;              /* current bdiv */
  97         u32 i;
  98         u32 est;                /* current estimate */
  99         u32 max;
 100 #if defined(CONFIG_405EZ)
 101         u32 cpr_pllc;
 102         u32 plloutb;
 103         u32 reg;
 104 #endif
 105
 106         get_sys_info(&sysinfo);
 107
 108 #if defined(CONFIG_405EZ)
 109         /* check the pll feedback source */
 110         mfcpr(CPR0_PLLC, cpr_pllc);
 111         plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
 112                                            sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
 113                     sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
 114         div = plloutb / (16 * baudrate); /* total divisor */
 115         umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
 116         max = 256;                      /* highest possible */
 117 #else /* 405EZ */
 118         div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
 119         umin = sysinfo.pllOpbDiv << 1;  /* 2 x OPB divisor */
 120         max = 32;                       /* highest possible */
 121 #endif /* 405EZ */
 122
 123         *udiv = diff = max;
 124
 125         /*
 126          * i is the test udiv value -- start with the largest
 127          * possible (max) to minimize serial clock and constrain
 128          * search to umin.
 129          */
 130         for (i = max; i > umin; i--) {
 131                 ibdiv = div / i;
 132                 est = i * ibdiv;
 133                 idiff = (est > div) ? (est - div) : (div - est);
 134                 if (idiff == 0) {
 135                         *udiv = i;
 136                         break;          /* can't do better */
 137                 } else if (idiff < diff) {
 138                         *udiv = i;      /* best so far */
 139                         diff = idiff;   /* update lowest diff*/
 140                 }
 141         }
 142
 143 #if defined(CONFIG_405EZ)
 144         mfcpr(CPR0_PERD0, reg);
 145         reg &= ~0x0000ffff;
 146         reg |= ((*udiv - 0) << 8) | (*udiv - 0);
 147         mtcpr(CPR0_PERD0, reg);
 148 #endif
 149
 150         return div / *udiv;
 151 }
 152 #endif /* #if (defined(CONFIG_405EP) ... */
 153
 154 /*
 155  * This function returns the UART clock used by the common
 156  * NS16550 driver. Additionally the SoC internal divisors for
 157  * optimal UART baudrate are configured.
 158  */
 159 int get_serial_clock(void)
 160 {
 161         u32 clk;
 162         u32 udiv;
 163 #if !defined(CONFIG_405EZ)
 164         u32 reg;
 165 #endif
 166 #if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
 167         PPC4xx_SYS_INFO sys_info;
 168 #endif
 169
 170         /*
 171          * Programming of the internal divisors is SoC specific.
 172          * Let's handle this in some #ifdef's for the SoC's.
 173          */
 174
 175 #if defined(CONFIG_405GP)
 176         reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
 177 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 178         clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 179         udiv = 1;
 180         reg |= CR0_EXTCLK_ENA;
 181 #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 182         clk = gd->cpu_clk;
 183 #ifdef CONFIG_SYS_405_UART_ERRATA_59
 184         udiv = 31;                      /* Errata 59: stuck at 31 */
 185 #else /* CONFIG_SYS_405_UART_ERRATA_59 */
 186         {
 187                 u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
 188
 189                 udiv = (clk + tmp / 2) / tmp;
 190         }
 191         if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 192                 udiv = UDIV_MAX;
 193 #endif /* CONFIG_SYS_405_UART_ERRATA_59 */
 194 #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 195         reg |= (udiv - 1) << CR0_UDIV_POS;      /* set the UART divisor */
 196         mtdcr (CPC0_CR0, reg);
 197 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 198         clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 199 #else
 200         clk = CONFIG_SYS_BASE_BAUD * 16;
 201 #endif
 202 #endif
 203
 204 #if defined(CONFIG_405EP)
 205         {
 206                 u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
 207
 208                 reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
 209                 clk = gd->cpu_clk;
 210                 udiv = (clk + tmp / 2) / tmp;
 211                 if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 212                         udiv = UDIV_MAX;
 213         }
 214         reg |= udiv << UCR0_UDIV_POS;           /* set the UART divisor */
 215         reg |= udiv << UCR1_UDIV_POS;           /* set the UART divisor */
 216         mtdcr(CPC0_UCR, reg);
 217         clk = CONFIG_SYS_BASE_BAUD * 16;
 218 #endif /* CONFIG_405EP */
 219
 220 #if defined(CONFIG_405EX) || defined(CONFIG_440)
 221         MFREG(UART0_SDR, reg);
 222         reg &= ~CR0_MASK;
 223
 224 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 225         reg |= CR0_EXTCLK_ENA;
 226         udiv = 1;
 227         clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 228 #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 229         clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
 230 #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 231
 232         reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;  /* set the UART divisor */
 233
 234         /*
 235          * Configure input clock to baudrate generator for all
 236          * available serial ports here
 237          */
 238         MTREG(UART0_SDR, reg);
 239 #if defined(UART1_SDR)
 240         MTREG(UART1_SDR, reg);
 241 #endif
 242 #if defined(UART2_SDR)
 243         MTREG(UART2_SDR, reg);
 244 #endif
 245 #if defined(UART3_SDR)
 246         MTREG(UART3_SDR, reg);
 247 #endif
 248 #endif /* CONFIG_405EX ... */
 249
 250 #if defined(CONFIG_405EZ)
 251         clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
 252 #endif /* CONFIG_405EZ */
 253
 254         /*
 255          * Correct UART frequency in bd-info struct now that
 256          * the UART divisor is available
 257          */
 258 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 259         gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 260 #else
 261         get_sys_info(&sys_info);
 262         gd->arch.uart_clk = sys_info.freqUART / udiv;
 263 #endif
 264
 265         return clk;
 266 }
 267 #endif  /* CONFIG_405GP */