board/amcc/canyonlands/canyonlands.c

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/ppc440.h>
  10 #include <libfdt.h>
  11 #include <fdt_support.h>
  12 #include <i2c.h>
  13 #include <asm/processor.h>
  14 #include <asm/io.h>
  15 #include <asm/mmu.h>
  16 #include <asm/4xx_pcie.h>
  17 #include <asm/ppc4xx-gpio.h>
  18 #include <linux/errno.h>
  19 #include <usb.h>
  20
  21 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 struct board_bcsr {
  26         u8      board_id;
  27         u8      cpld_rev;
  28         u8      led_user;
  29         u8      board_status;
  30         u8      reset_ctrl;
  31         u8      flash_ctrl;
  32         u8      eth_ctrl;
  33         u8      usb_ctrl;
  34         u8      irq_ctrl;
  35 };
  36
  37 #define BOARD_CANYONLANDS_PCIE  1
  38 #define BOARD_CANYONLANDS_SATA  2
  39 #define BOARD_GLACIER           3
  40 #define BOARD_ARCHES            4
  41
  42 /*
  43  * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
  44  * board specific values.
  45  */
  46 #if defined(CONFIG_ARCHES)
  47 u32 ddr_wrdtr(u32 default_val) {
  48         return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
  49 }
  50 #else
  51 u32 ddr_wrdtr(u32 default_val) {
  52         return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
  53 }
  54
  55 u32 ddr_clktr(u32 default_val) {
  56         return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
  57 }
  58 #endif
  59
  60 #if defined(CONFIG_ARCHES)
  61 /*
  62  * FPGA read/write helper macros
  63  */
  64 static inline int board_fpga_read(int offset)
  65 {
  66         return in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
  67 }
  68
  69 static inline void board_fpga_write(int offset, int data)
  70 {
  71         out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
  72 }
  73
  74 /*
  75  * CPLD read/write helper macros
  76  */
  77 static inline int board_cpld_read(int offset)
  78 {
  79         int data;
  80
  81         out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  82         data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
  83
  84         return data;
  85 }
  86
  87 static inline void board_cpld_write(int offset, int data)
  88 {
  89         out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  90         out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
  91 }
  92 #else
  93 static int pvr_460ex(void)
  94 {
  95         u32 pvr = get_pvr();
  96
  97         if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
  98             (pvr == PVR_460EX_RB))
  99                 return 1;
 100
 101         return 0;
 102 }
 103 #endif  /* defined(CONFIG_ARCHES) */
 104
 105 int board_early_init_f(void)
 106 {
 107 #if !defined(CONFIG_ARCHES)
 108         u32 sdr0_cust0;
 109         struct board_bcsr *bcsr_data =
 110                 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
 111
 112 #endif
 113
 114         /*
 115          * Setup the interrupt controller polarities, triggers, etc.
 116          */
 117         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 118         mtdcr(UIC0ER, 0x00000000);      /* disable all */
 119         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
 120         mtdcr(UIC0PR, 0xffffffff);      /* per ref-board manual */
 121         mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
 122         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
 123         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 124
 125         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 126         mtdcr(UIC1ER, 0x00000000);      /* disable all */
 127         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
 128         mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
 129         mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
 130         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
 131         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 132
 133         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 134         mtdcr(UIC2ER, 0x00000000);      /* disable all */
 135         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
 136         mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
 137         mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
 138         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
 139         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 140
 141         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
 142         mtdcr(UIC3ER, 0x00000000);      /* disable all */
 143         mtdcr(UIC3CR, 0x00000000);      /* all non-critical */
 144         mtdcr(UIC3PR, 0xffffffff);      /* per ref-board manual */
 145         mtdcr(UIC3TR, 0x00000000);      /* per ref-board manual */
 146         mtdcr(UIC3VR, 0x00000000);      /* int31 highest, base=0x000 */
 147         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
 148
 149 #if !defined(CONFIG_ARCHES)
 150         /* SDR Setting - enable NDFC */
 151         mfsdr(SDR0_CUST0, sdr0_cust0);
 152         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 153                 SDR0_CUST0_NDFC_ENABLE          |
 154                 SDR0_CUST0_NDFC_BW_8_BIT        |
 155                 SDR0_CUST0_NDFC_ARE_MASK        |
 156                 SDR0_CUST0_NDFC_BAC_ENCODE(3)   |
 157                 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 158         mtsdr(SDR0_CUST0, sdr0_cust0);
 159 #endif
 160
 161         /*
 162          * Configure PFC (Pin Function Control) registers
 163          * UART0: 4 pins
 164          */
 165         mtsdr(SDR0_PFC1, 0x00040000);
 166
 167         /* Enable PCI host functionality in SDR0_PCI0 */
 168         mtsdr(SDR0_PCI0, 0xe0000000);
 169
 170 #if !defined(CONFIG_ARCHES)
 171         /* Enable ethernet and take out of reset */
 172         out_8(&bcsr_data->eth_ctrl, 0) ;
 173
 174         /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
 175         out_8(&bcsr_data->flash_ctrl, 0) ;
 176         mtsdr(SDR0_SRST1, 0);   /* Pull AHB out of reset default=1 */
 177
 178         /* Setup PLB4-AHB bridge based on the system address map */
 179         mtdcr(AHB_TOP, 0x8000004B);
 180         mtdcr(AHB_BOT, 0x8000004B);
 181
 182 #endif
 183
 184         return 0;
 185 }
 186
 187 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 188 int board_usb_init(int index, enum usb_init_type init)
 189 {
 190         struct board_bcsr *bcsr_data =
 191                 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
 192         u8 val;
 193
 194         /* Enable USB host & USB-OTG */
 195         val = in_8(&bcsr_data->usb_ctrl);
 196         val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
 197         out_8(&bcsr_data->usb_ctrl, val);
 198
 199         /*
 200          * Configure USB-STP pins as alternate and not GPIO
 201          * It seems to be neccessary to configure the STP pins as GPIO
 202          * input at powerup (perhaps while USB reset is asserted). So
 203          * we configure those pins to their "real" function now.
 204          */
 205         gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 206         gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 207
 208         return 0;
 209 }
 210
 211 int usb_board_stop(void)
 212 {
 213         struct board_bcsr *bcsr_data =
 214                 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
 215         u8 val;
 216
 217         /* Disable USB host & USB-OTG */
 218         val = in_8(&bcsr_data->usb_ctrl);
 219         val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
 220         out_8(&bcsr_data->usb_ctrl, val);
 221
 222         /* Reconfigure USB-STP pins as input */
 223         gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
 224         gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
 225
 226         return 0;
 227 }
 228
 229 int board_usb_cleanup(int index, enum usb_init_type init)
 230 {
 231         return usb_board_stop();
 232 }
 233 #endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
 234
 235 #if !defined(CONFIG_ARCHES)
 236 static void canyonlands_sata_init(int board_type)
 237 {
 238         u32 reg;
 239
 240         if (board_type == BOARD_CANYONLANDS_SATA) {
 241                 /* Put SATA in reset */
 242                 SDR_WRITE(SDR0_SRST1, 0x00020001);
 243
 244                 /* Set the phy for SATA, not PCI-E port 0 */
 245                 reg = SDR_READ(PESDR0_PHY_CTL_RST);
 246                 SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
 247                 reg = SDR_READ(PESDR0_L0CLK);
 248                 SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
 249                 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
 250                 SDR_WRITE(PESDR0_L0DRV, 0x00000104);
 251
 252                 /* Bring SATA out of reset */
 253                 SDR_WRITE(SDR0_SRST1, 0x00000000);
 254         }
 255 }
 256 #endif  /* !defined(CONFIG_ARCHES) */
 257
 258 int get_cpu_num(void)
 259 {
 260         int cpu = NA_OR_UNKNOWN_CPU;
 261
 262 #if defined(CONFIG_ARCHES)
 263         int cpu_num;
 264
 265         cpu_num = board_fpga_read(0x3);
 266
 267         /* sanity check; assume cpu numbering starts and increments from 0 */
 268         if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
 269                 cpu = cpu_num;
 270 #endif
 271
 272         return cpu;
 273 }
 274
 275 #if !defined(CONFIG_ARCHES)
 276 int checkboard(void)
 277 {
 278         struct board_bcsr *bcsr_data =
 279                 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
 280         char buf[64];
 281         int i = getenv_f("serial#", buf, sizeof(buf));
 282
 283         if (pvr_460ex()) {
 284                 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
 285                 if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
 286                         gd->board_type = BOARD_CANYONLANDS_PCIE;
 287                 else
 288                         gd->board_type = BOARD_CANYONLANDS_SATA;
 289         } else {
 290                 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
 291                 gd->board_type = BOARD_GLACIER;
 292         }
 293
 294         switch (gd->board_type) {
 295         case BOARD_CANYONLANDS_PCIE:
 296         case BOARD_GLACIER:
 297                 puts(", 2*PCIe");
 298                 break;
 299
 300         case BOARD_CANYONLANDS_SATA:
 301                 puts(", 1*PCIe/1*SATA");
 302                 break;
 303         }
 304
 305         printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
 306
 307         if (i > 0) {
 308                 puts(", serial# ");
 309                 puts(buf);
 310         }
 311         putc('\n');
 312
 313         canyonlands_sata_init(gd->board_type);
 314
 315         return (0);
 316 }
 317
 318 #else   /* defined(CONFIG_ARCHES) */
 319
 320 int checkboard(void)
 321 {
 322         char *s = getenv("serial#");
 323
 324         printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
 325         printf("       Revision %02x.%02x ",
 326                                 board_fpga_read(0x0), board_fpga_read(0x1));
 327
 328         gd->board_type = BOARD_ARCHES;
 329
 330         /* Only CPU0 has access to CPLD registers */
 331         if (get_cpu_num() == 0) {
 332                 u8 cfg_sw = board_cpld_read(0x1);
 333                 printf("(FPGA=%02x, CPLD=%02x)\n",
 334                                 board_fpga_read(0x2), board_cpld_read(0x0));
 335                 printf("       Configuration Switch %d%d%d%d\n",
 336                                 ((cfg_sw >> 3) & 0x01),
 337                                 ((cfg_sw >> 2) & 0x01),
 338                                 ((cfg_sw >> 1) & 0x01),
 339                                 ((cfg_sw >> 0) & 0x01));
 340         } else
 341                 printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
 342
 343
 344         if (s != NULL)
 345                 printf("       Serial# %s\n", s);
 346
 347         return 0;
 348 }
 349 #endif  /* !defined(CONFIG_ARCHES) */
 350
 351 #if defined(CONFIG_PCI)
 352 int board_pcie_first(void)
 353 {
 354         /*
 355          * Canyonlands with SATA enabled has only one PCIe slot
 356          * (2nd one).
 357          */
 358         if (gd->board_type == BOARD_CANYONLANDS_SATA)
 359                 return 1;
 360
 361         return 0;
 362 }
 363 #endif /* CONFIG_PCI */
 364
 365 int board_early_init_r (void)
 366 {
 367         /*
 368          * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 369          * boot EBC mapping only supports a maximum of 16MBytes
 370          * (4.ff00.0000 - 4.ffff.ffff).
 371          * To solve this problem, the FLASH has to get remapped to another
 372          * EBC address which accepts bigger regions:
 373          *
 374          * 0xfc00.0000 -> 4.cc00.0000
 375          */
 376
 377         /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
 378         mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 379
 380         /* Remove TLB entry of boot EBC mapping */
 381         remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
 382
 383         /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
 384         program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
 385                     TLB_WORD2_I_ENABLE);
 386
 387         /*
 388          * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
 389          * 0xfc00.0000 is possible
 390          */
 391
 392         /*
 393          * Clear potential errors resulting from auto-calibration.
 394          * If not done, then we could get an interrupt later on when
 395          * exceptions are enabled.
 396          */
 397         set_mcsr(get_mcsr());
 398
 399         return 0;
 400 }
 401
 402 #if !defined(CONFIG_ARCHES)
 403 int misc_init_r(void)
 404 {
 405         u32 sdr0_srst1 = 0;
 406         u32 eth_cfg;
 407         u8 val;
 408
 409         /*
 410          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 411          * This is board specific, so let's do it here.
 412          */
 413         mfsdr(SDR0_ETH_CFG, eth_cfg);
 414         /* disable SGMII mode */
 415         eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
 416                      SDR0_ETH_CFG_SGMII1_ENABLE |
 417                      SDR0_ETH_CFG_SGMII0_ENABLE);
 418         /* Set the for 2 RGMII mode */
 419         /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 420         eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
 421         if (pvr_460ex())
 422                 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 423         else
 424                 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 425         mtsdr(SDR0_ETH_CFG, eth_cfg);
 426
 427         /*
 428          * The AHB Bridge core is held in reset after power-on or reset
 429          * so enable it now
 430          */
 431         mfsdr(SDR0_SRST1, sdr0_srst1);
 432         sdr0_srst1 &= ~SDR0_SRST1_AHB;
 433         mtsdr(SDR0_SRST1, sdr0_srst1);
 434
 435         /*
 436          * RTC/M41T62:
 437          * Disable square wave output: Batterie will be drained
 438          * quickly, when this output is not disabled
 439          */
 440         val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
 441         val &= ~0x40;
 442         i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
 443
 444         return 0;
 445 }
 446
 447 #else   /* defined(CONFIG_ARCHES) */
 448
 449 int misc_init_r(void)
 450 {
 451         u32 eth_cfg = 0;
 452         u32 eth_pll;
 453         u32 reg;
 454
 455         /*
 456          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 457          * This is board specific, so let's do it here.
 458          */
 459
 460         /* enable SGMII mode */
 461         eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
 462                         SDR0_ETH_CFG_SGMII1_ENABLE |
 463                         SDR0_ETH_CFG_SGMII2_ENABLE);
 464
 465         /* Set EMAC for MDIO */
 466         eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
 467
 468         /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
 469         eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
 470
 471         mtsdr(SDR0_ETH_CFG, eth_cfg);
 472
 473         /* reset all SGMII interfaces */
 474         mfsdr(SDR0_SRST1,   reg);
 475         reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
 476         mtsdr(SDR0_SRST1, reg);
 477         mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
 478         mtsdr(SDR0_SRST1,   0x00000000);
 479
 480         do {
 481                 mfsdr(SDR0_ETH_PLL, eth_pll);
 482         } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
 483
 484         return 0;
 485 }
 486 #endif  /* !defined(CONFIG_ARCHES) */
 487
 488 #ifdef CONFIG_OF_BOARD_SETUP
 489 extern int __ft_board_setup(void *blob, bd_t *bd);
 490
 491 int ft_board_setup(void *blob, bd_t *bd)
 492 {
 493         __ft_board_setup(blob, bd);
 494
 495         if (gd->board_type == BOARD_CANYONLANDS_SATA) {
 496                 /*
 497                  * When SATA is selected we need to disable the first PCIe
 498                  * node in the device tree, so that Linux doesn't initialize
 499                  * it.
 500                  */
 501                 fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
 502                                      "disabled", sizeof("disabled"), 1);
 503         }
 504
 505         if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
 506                 /*
 507                  * When PCIe is selected we need to disable the SATA
 508                  * node in the device tree, so that Linux doesn't initialize
 509                  * it.
 510                  */
 511                 fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
 512                                      "disabled", sizeof("disabled"), 1);
 513         }
 514
 515         return 0;
 516 }
 517 #endif /* CONFIG_OF_BOARD_SETUP */