board/amcc/yosemite/yosemite.c

   1 /*
   2  * (C) Copyright 2006-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/ppc4xx.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <spd_sdram.h>
  13 #include <libfdt.h>
  14 #include <fdt_support.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips     */
  19
  20 static inline u32 get_async_pci_freq(void)
  21 {
  22         if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
  23                 CONFIG_SYS_BCSR5_PCI66EN)
  24                 return 66666666;
  25         else
  26                 return 33333333;
  27 }
  28
  29 int board_early_init_f(void)
  30 {
  31         register uint reg;
  32
  33         /*--------------------------------------------------------------------
  34          * Setup the external bus controller/chip selects
  35          *-------------------------------------------------------------------*/
  36         mtdcr(EBC0_CFGADDR, EBC0_CFG);
  37         reg = mfdcr(EBC0_CFGDATA);
  38         mtdcr(EBC0_CFGDATA, reg | 0x04000000);  /* Set ATC */
  39
  40         /*--------------------------------------------------------------------
  41          * Setup the GPIO pins
  42          *-------------------------------------------------------------------*/
  43         /*CPLD cs */
  44         /*setup Address lines for flash size 64Meg. */
  45         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
  46         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
  47         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
  48
  49         /*setup emac */
  50         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  51         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  52         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  53         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  54         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  55
  56         /*UART1 */
  57         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  58         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  59         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  60
  61         /* external interrupts IRQ0...3 */
  62         out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
  63         out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
  64         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  65
  66 #ifdef CONFIG_440EP
  67         /*setup USB 2.0 */
  68         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  69         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  70         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  71         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  72         out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  73 #endif
  74
  75         /*--------------------------------------------------------------------
  76          * Setup the interrupt controller polarities, triggers, etc.
  77          *-------------------------------------------------------------------*/
  78         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  79         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  80         mtdcr(UIC0CR, 0x00000009);      /* ATI & UIC1 crit are critical */
  81         mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
  82         mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
  83         mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
  84         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  85
  86         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  87         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  88         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  89         mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
  90         mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
  91         mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
  92         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  93
  94         /*--------------------------------------------------------------------
  95          * Setup other serial configuration
  96          *-------------------------------------------------------------------*/
  97         mfsdr(SDR0_PCI0, reg);
  98         mtsdr(SDR0_PCI0, 0x80000000 | reg);     /* PCI arbiter enabled */
  99         mtsdr(SDR0_PFC0, 0x00003e00);   /* Pin function */
 100         mtsdr(SDR0_PFC1, 0x00048000);   /* Pin function: UART0 has 4 pins */
 101
 102         /* Check and reconfigure the PCI sync clock if necessary */
 103         ppc4xx_pci_sync_clock_config(get_async_pci_freq());
 104
 105         /*clear tmrclk divisor */
 106         *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
 107
 108         /*enable ethernet */
 109         *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
 110
 111 #ifdef CONFIG_440EP
 112         /*enable usb 1.1 fs device and remove usb 2.0 reset */
 113         *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
 114 #endif
 115
 116         /*get rid of flash write protect */
 117         *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
 118
 119         return 0;
 120 }
 121
 122 int misc_init_r (void)
 123 {
 124         uint pbcr;
 125         int size_val = 0;
 126
 127         /* Re-do sizing to get full correct info */
 128         mtdcr(EBC0_CFGADDR, PB0CR);
 129         pbcr = mfdcr(EBC0_CFGDATA);
 130         switch (gd->bd->bi_flashsize) {
 131         case 1 << 20:
 132                 size_val = 0;
 133                 break;
 134         case 2 << 20:
 135                 size_val = 1;
 136                 break;
 137         case 4 << 20:
 138                 size_val = 2;
 139                 break;
 140         case 8 << 20:
 141                 size_val = 3;
 142                 break;
 143         case 16 << 20:
 144                 size_val = 4;
 145                 break;
 146         case 32 << 20:
 147                 size_val = 5;
 148                 break;
 149         case 64 << 20:
 150                 size_val = 6;
 151                 break;
 152         case 128 << 20:
 153                 size_val = 7;
 154                 break;
 155         }
 156         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 157         mtdcr(EBC0_CFGADDR, PB0CR);
 158         mtdcr(EBC0_CFGDATA, pbcr);
 159
 160         /* adjust flash start and offset */
 161         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 162         gd->bd->bi_flashoffset = 0;
 163
 164         /* Monitor protection ON by default */
 165         (void)flash_protect(FLAG_PROTECT_SET,
 166                             -CONFIG_SYS_MONITOR_LEN,
 167                             0xffffffff,
 168                             &flash_info[0]);
 169
 170         return 0;
 171 }
 172
 173 int checkboard(void)
 174 {
 175         char buf[64];
 176         int i = getenv_f("serial#", buf, sizeof(buf));
 177         u8 rev;
 178         u32 clock = get_async_pci_freq();
 179
 180 #ifdef CONFIG_440EP
 181         printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
 182 #else
 183         printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 184 #endif
 185
 186         rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
 187         printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
 188
 189         if (i > 0) {
 190                 puts(", serial# ");
 191                 puts(buf);
 192         }
 193         putc('\n');
 194
 195         /*
 196          * Reconfiguration of the PCI sync clock is already done,
 197          * now check again if everything is in range:
 198          */
 199         if (ppc4xx_pci_sync_clock_config(clock)) {
 200                 printf("ERROR: PCI clocking incorrect (async=%d "
 201                        "sync=%ld)!\n", clock, get_PCI_freq());
 202         }
 203
 204         return (0);
 205 }
 206
 207 /*************************************************************************
 208  *  dram_init -- doesn't use serial presence detect.
 209  *
 210  *  Assumes:    256 MB, ECC, non-registered
 211  *              PLB @ 133 MHz
 212  *
 213  ************************************************************************/
 214 #define NUM_TRIES 64
 215 #define NUM_READS 10
 216
 217 void sdram_tr1_set(int ram_address, int* tr1_value)
 218 {
 219         int i;
 220         int j, k;
 221         volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
 222         int first_good = -1, last_bad = 0x1ff;
 223
 224         unsigned long test[NUM_TRIES] = {
 225                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 226                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 227                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 228                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 229                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 230                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 231                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 232                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 233                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 234                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 235                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 236                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 237                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 238                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 239                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 240                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
 241
 242         /* go through all possible SDRAM0_TR1[RDCT] values */
 243         for (i=0; i<=0x1ff; i++) {
 244                 /* set the current value for TR1 */
 245                 mtsdram(SDRAM0_TR1, (0x80800800 | i));
 246
 247                 /* write values */
 248                 for (j=0; j<NUM_TRIES; j++) {
 249                         ram_pointer[j] = test[j];
 250
 251                         /* clear any cache at ram location */
 252                         __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 253                 }
 254
 255                 /* read values back */
 256                 for (j=0; j<NUM_TRIES; j++) {
 257                         for (k=0; k<NUM_READS; k++) {
 258                                 /* clear any cache at ram location */
 259                                 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 260
 261                                 if (ram_pointer[j] != test[j])
 262                                         break;
 263                         }
 264
 265                         /* read error */
 266                         if (k != NUM_READS) {
 267                                 break;
 268                         }
 269                 }
 270
 271                 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
 272                 if (j == NUM_TRIES) {
 273                         if (first_good == -1)
 274                                 first_good = i;         /* found beginning of window */
 275                 } else { /* bad read */
 276                         /* if we have not had a good read then don't care */
 277                         if(first_good != -1) {
 278                                 /* first failure after a good read */
 279                                 last_bad = i-1;
 280                                 break;
 281                         }
 282                 }
 283         }
 284
 285         /* return the current value for TR1 */
 286         *tr1_value = (first_good + last_bad) / 2;
 287 }
 288
 289 int dram_init(void)
 290 {
 291         register uint reg;
 292         int tr1_bank1, tr1_bank2;
 293
 294         /*--------------------------------------------------------------------
 295          * Setup some default
 296          *------------------------------------------------------------------*/
 297         mtsdram(SDRAM0_UABBA, 0x00000000);      /* ubba=0 (default)             */
 298         mtsdram(SDRAM0_SLIO, 0x00000000);       /* rdre=0 wrre=0 rarw=0         */
 299         mtsdram(SDRAM0_DEVOPT, 0x00000000);     /* dll=0 ds=0 (normal)          */
 300         mtsdram(SDRAM0_CLKTR, 0x40000000);      /* ?? */
 301         mtsdram(SDRAM0_WDDCTR, 0x40000000);     /* ?? */
 302
 303         /*clear this first, if the DDR is enabled by a debugger
 304           then you can not make changes. */
 305         mtsdram(SDRAM0_CFG0, 0x00000000);       /* Disable EEC */
 306
 307         /*--------------------------------------------------------------------
 308          * Setup for board-specific specific mem
 309          *------------------------------------------------------------------*/
 310         /*
 311          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 312          */
 313         mtsdram(SDRAM0_B0CR, 0x000a4001);       /* SDBA=0x000 128MB, Mode 3, enabled */
 314         mtsdram(SDRAM0_B1CR, 0x080a4001);       /* SDBA=0x080 128MB, Mode 3, enabled */
 315
 316         mtsdram(SDRAM0_TR0, 0x410a4012);        /* ?? */
 317         mtsdram(SDRAM0_RTR, 0x04080000);        /* ?? */
 318         mtsdram(SDRAM0_CFG1, 0x00000000);       /* Self-refresh exit, disable PM    */
 319         mtsdram(SDRAM0_CFG0, 0x30000000);       /* Disable EEC */
 320         udelay(400);            /* Delay 200 usecs (min)            */
 321
 322         /*--------------------------------------------------------------------
 323          * Enable the controller, then wait for DCEN to complete
 324          *------------------------------------------------------------------*/
 325         mtsdram(SDRAM0_CFG0, 0x80000000);       /* Enable */
 326
 327         for (;;) {
 328                 mfsdram(SDRAM0_MCSTS, reg);
 329                 if (reg & 0x80000000)
 330                         break;
 331         }
 332
 333         sdram_tr1_set(0x00000000, &tr1_bank1);
 334         sdram_tr1_set(0x08000000, &tr1_bank2);
 335         mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
 336
 337         gd->ram_size = CONFIG_SYS_SDRAM_BANKS *
 338                 (CONFIG_SYS_KBYTES_SDRAM * 1024);       /* set bytes */
 339
 340         return 0;
 341 }
 342
 343 /*************************************************************************
 344  *  hw_watchdog_reset
 345  *
 346  *      This routine is called to reset (keep alive) the watchdog timer
 347  *
 348  ************************************************************************/
 349 #if defined(CONFIG_HW_WATCHDOG)
 350 void hw_watchdog_reset(void)
 351 {
 352
 353 }
 354 #endif
 355
 356 void board_reset(void)
 357 {
 358         /* give reset to BCSR */
 359         *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
 360 }