board/engicam/geam6ul/geam6ul.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10
  11 #include <asm/io.h>
  12 #include <asm/gpio.h>
  13 #include <linux/sizes.h>
  14
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/mach-imx/iomux-v3.h>
  21
  22 #include "../common/board.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #ifdef CONFIG_NAND_MXS
  27
  28 #define GPMI_PAD_CTRL0          (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  29 #define GPMI_PAD_CTRL1          (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  30                                 PAD_CTL_SRE_FAST)
  31 #define GPMI_PAD_CTRL2          (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  32
  33 static iomux_v3_cfg_t const nand_pads[] = {
  34         IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  35         IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  36         IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  37         IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  38         IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  39         IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  40         IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  41         IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  42         IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  43         IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  44         IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  45         IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  46         IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  47         IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  48         IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  49 };
  50
  51 void setup_gpmi_nand(void)
  52 {
  53         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  54
  55         /* config gpmi nand iomux */
  56         SETUP_IOMUX_PADS(nand_pads);
  57
  58         clrbits_le32(&mxc_ccm->CCGR4,
  59                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  60                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  61                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  62                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  63                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  64
  65         /*
  66          * config gpmi and bch clock to 100 MHz
  67          * bch/gpmi select PLL2 PFD2 400M
  68          * 100M = 400M / 4
  69          */
  70         clrbits_le32(&mxc_ccm->cscmr1,
  71                      MXC_CCM_CSCMR1_BCH_CLK_SEL |
  72                      MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  73         clrsetbits_le32(&mxc_ccm->cscdr1,
  74                         MXC_CCM_CSCDR1_BCH_PODF_MASK |
  75                         MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  76                         (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  77                         (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  78
  79         /* enable gpmi and bch clock gating */
  80         setbits_le32(&mxc_ccm->CCGR4,
  81                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  82                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  83                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  84                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  85                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  86
  87         /* enable apbh clock gating */
  88         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  89 }
  90 #endif /* CONFIG_NAND_MXS */