board/engicam/icorem6_rqs/icorem6_rqs.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <mmc.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <linux/sizes.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/imx-common/iomux-v3.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  26         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  27         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  28
  29 static iomux_v3_cfg_t const uart4_pads[] = {
  30         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  31         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  32 };
  33
  34 int board_early_init_f(void)
  35 {
  36         SETUP_IOMUX_PADS(uart4_pads);
  37
  38         return 0;
  39 }
  40
  41 int board_init(void)
  42 {
  43         /* Address of boot parameters */
  44         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  45
  46         return 0;
  47 }
  48
  49 #ifdef CONFIG_ENV_IS_IN_MMC
  50 int board_mmc_get_env_dev(int devno)
  51 {
  52         /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
  53         return (devno == 3) ? 1 : 0;
  54 }
  55
  56 static void mmc_late_init(void)
  57 {
  58         char cmd[32];
  59         char mmcblk[32];
  60         u32 dev_no = mmc_get_env_dev();
  61
  62         setenv_ulong("mmcdev", dev_no);
  63
  64         /* Set mmcblk env */
  65         sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
  66         setenv("mmcroot", mmcblk);
  67
  68         sprintf(cmd, "mmc dev %d", dev_no);
  69         run_command(cmd, 0);
  70 }
  71 #endif
  72
  73 int board_late_init(void)
  74 {
  75         switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
  76                         IMX6_BMODE_SHIFT) {
  77         case IMX6_BMODE_SD:
  78         case IMX6_BMODE_ESD:
  79         case IMX6_BMODE_MMC:
  80         case IMX6_BMODE_EMMC:
  81 #ifdef CONFIG_ENV_IS_IN_MMC
  82                 mmc_late_init();
  83 #endif
  84                 setenv("modeboot", "mmcboot");
  85                 break;
  86         default:
  87                 setenv("modeboot", "");
  88                 break;
  89         }
  90
  91         if (is_mx6dq())
  92                 setenv("fdt_file", "imx6q-icore-rqs.dtb");
  93         else if(is_mx6dl() || is_mx6solo())
  94                 setenv("fdt_file", "imx6dl-icore-rqs.dtb");
  95
  96         return 0;
  97 }
  98
  99 int dram_init(void)
 100 {
 101         gd->ram_size = imx_ddr_size();
 102
 103         return 0;
 104 }
 105
 106 #ifdef CONFIG_SPL_BUILD
 107 #include <libfdt.h>
 108 #include <spl.h>
 109
 110 #include <asm/arch/crm_regs.h>
 111 #include <asm/arch/mx6-ddr.h>
 112
 113 /* MMC board initialization is needed till adding DM support in SPL */
 114 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 115 #include <mmc.h>
 116 #include <fsl_esdhc.h>
 117
 118 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 119         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_HIGH |               \
 120         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 121
 122 static iomux_v3_cfg_t const usdhc3_pads[] = {
 123         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 124         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 125         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 126         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 127         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 128         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 129 };
 130
 131 static iomux_v3_cfg_t const usdhc4_pads[] = {
 132         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 133         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 134         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 135         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 136         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 137         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 142 };
 143
 144 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 145         {USDHC3_BASE_ADDR, 1, 4},
 146         {USDHC4_BASE_ADDR, 1, 8},
 147 };
 148
 149 int board_mmc_getcd(struct mmc *mmc)
 150 {
 151         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 152         int ret = 0;
 153
 154         switch (cfg->esdhc_base) {
 155         case USDHC3_BASE_ADDR:
 156         case USDHC4_BASE_ADDR:
 157                 ret = 1;
 158                 break;
 159         }
 160
 161         return ret;
 162 }
 163
 164 int board_mmc_init(bd_t *bis)
 165 {
 166         int i, ret;
 167
 168         /*
 169         * According to the board_mmc_init() the following map is done:
 170         * (U-boot device node)    (Physical Port)
 171         * mmc0                  USDHC3
 172         * mmc1                  USDHC4
 173         */
 174         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 175                 switch (i) {
 176                 case 0:
 177                         SETUP_IOMUX_PADS(usdhc3_pads);
 178                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 179                         break;
 180                 case 1:
 181                         SETUP_IOMUX_PADS(usdhc4_pads);
 182                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 183                         break;
 184                 default:
 185                         printf("Warning - USDHC%d controller not supporting\n",
 186                                i + 1);
 187                         return 0;
 188                 }
 189
 190                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 191                 if (ret) {
 192                         printf("Warning: failed to initialize mmc dev %d\n", i);
 193                         return ret;
 194                 }
 195         }
 196
 197         return 0;
 198 }
 199
 200 #ifdef CONFIG_ENV_IS_IN_MMC
 201 void board_boot_order(u32 *spl_boot_list)
 202 {
 203         u32 bmode = imx6_src_get_boot_mode();
 204         u8 boot_dev = BOOT_DEVICE_MMC1;
 205
 206         switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
 207         case IMX6_BMODE_SD:
 208         case IMX6_BMODE_ESD:
 209                 /* SD/eSD - BOOT_DEVICE_MMC1 */
 210                 break;
 211         case IMX6_BMODE_MMC:
 212         case IMX6_BMODE_EMMC:
 213                 /* MMC/eMMC */
 214                 boot_dev = BOOT_DEVICE_MMC2;
 215                 break;
 216         default:
 217                 /* Default - BOOT_DEVICE_MMC1 */
 218                 printf("Wrong board boot order\n");
 219                 break;
 220         }
 221
 222         spl_boot_list[0] = boot_dev;
 223 }
 224 #endif
 225 #endif
 226
 227 #ifdef CONFIG_SPL_LOAD_FIT
 228 int board_fit_config_name_match(const char *name)
 229 {
 230         if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
 231                 return 0;
 232         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
 233                 return 0;
 234         else
 235                 return -1;
 236 }
 237 #endif
 238
 239 /*
 240  * Driving strength:
 241  *   0x30 == 40 Ohm
 242  *   0x28 == 48 Ohm
 243  */
 244
 245 #define IMX6DQ_DRIVE_STRENGTH           0x30
 246 #define IMX6SDL_DRIVE_STRENGTH          0x28
 247
 248 /* configure MX6Q/DUAL mmdc DDR io registers */
 249 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 250         .dram_sdqs0 = 0x28,
 251         .dram_sdqs1 = 0x28,
 252         .dram_sdqs2 = 0x28,
 253         .dram_sdqs3 = 0x28,
 254         .dram_sdqs4 = 0x28,
 255         .dram_sdqs5 = 0x28,
 256         .dram_sdqs6 = 0x28,
 257         .dram_sdqs7 = 0x28,
 258         .dram_dqm0 = 0x28,
 259         .dram_dqm1 = 0x28,
 260         .dram_dqm2 = 0x28,
 261         .dram_dqm3 = 0x28,
 262         .dram_dqm4 = 0x28,
 263         .dram_dqm5 = 0x28,
 264         .dram_dqm6 = 0x28,
 265         .dram_dqm7 = 0x28,
 266         .dram_cas = 0x30,
 267         .dram_ras = 0x30,
 268         .dram_sdclk_0 = 0x30,
 269         .dram_sdclk_1 = 0x30,
 270         .dram_reset = 0x30,
 271         .dram_sdcke0 = 0x3000,
 272         .dram_sdcke1 = 0x3000,
 273         .dram_sdba2 = 0x00000000,
 274         .dram_sdodt0 = 0x30,
 275         .dram_sdodt1 = 0x30,
 276 };
 277
 278 /* configure MX6Q/DUAL mmdc GRP io registers */
 279 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 280         .grp_b0ds = 0x30,
 281         .grp_b1ds = 0x30,
 282         .grp_b2ds = 0x30,
 283         .grp_b3ds = 0x30,
 284         .grp_b4ds = 0x30,
 285         .grp_b5ds = 0x30,
 286         .grp_b6ds = 0x30,
 287         .grp_b7ds = 0x30,
 288         .grp_addds = 0x30,
 289         .grp_ddrmode_ctl = 0x00020000,
 290         .grp_ddrpke = 0x00000000,
 291         .grp_ddrmode = 0x00020000,
 292         .grp_ctlds = 0x30,
 293         .grp_ddr_type = 0x000c0000,
 294 };
 295
 296 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 297 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 298         .dram_sdclk_0 = 0x30,
 299         .dram_sdclk_1 = 0x30,
 300         .dram_cas = 0x30,
 301         .dram_ras = 0x30,
 302         .dram_reset = 0x30,
 303         .dram_sdcke0 = 0x30,
 304         .dram_sdcke1 = 0x30,
 305         .dram_sdba2 = 0x00000000,
 306         .dram_sdodt0 = 0x30,
 307         .dram_sdodt1 = 0x30,
 308         .dram_sdqs0 = 0x28,
 309         .dram_sdqs1 = 0x28,
 310         .dram_sdqs2 = 0x28,
 311         .dram_sdqs3 = 0x28,
 312         .dram_sdqs4 = 0x28,
 313         .dram_sdqs5 = 0x28,
 314         .dram_sdqs6 = 0x28,
 315         .dram_sdqs7 = 0x28,
 316         .dram_dqm0 = 0x28,
 317         .dram_dqm1 = 0x28,
 318         .dram_dqm2 = 0x28,
 319         .dram_dqm3 = 0x28,
 320         .dram_dqm4 = 0x28,
 321         .dram_dqm5 = 0x28,
 322         .dram_dqm6 = 0x28,
 323         .dram_dqm7 = 0x28,
 324 };
 325
 326 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 327 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 328         .grp_ddr_type = 0x000c0000,
 329         .grp_ddrmode_ctl = 0x00020000,
 330         .grp_ddrpke = 0x00000000,
 331         .grp_addds = 0x30,
 332         .grp_ctlds = 0x30,
 333         .grp_ddrmode = 0x00020000,
 334         .grp_b0ds = 0x28,
 335         .grp_b1ds = 0x28,
 336         .grp_b2ds = 0x28,
 337         .grp_b3ds = 0x28,
 338         .grp_b4ds = 0x28,
 339         .grp_b5ds = 0x28,
 340         .grp_b6ds = 0x28,
 341         .grp_b7ds = 0x28,
 342 };
 343
 344 /* mt41j256 */
 345 static struct mx6_ddr3_cfg mt41j256 = {
 346         .mem_speed = 1066,
 347         .density = 2,
 348         .width = 16,
 349         .banks = 8,
 350         .rowaddr = 13,
 351         .coladdr = 10,
 352         .pagesz = 2,
 353         .trcd = 1375,
 354         .trcmin = 4875,
 355         .trasmin = 3500,
 356         .SRT = 0,
 357 };
 358
 359 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 360         .p0_mpwldectrl0 = 0x000E0009,
 361         .p0_mpwldectrl1 = 0x0018000E,
 362         .p1_mpwldectrl0 = 0x00000007,
 363         .p1_mpwldectrl1 = 0x00000000,
 364         .p0_mpdgctrl0 = 0x43280334,
 365         .p0_mpdgctrl1 = 0x031C0314,
 366         .p1_mpdgctrl0 = 0x4318031C,
 367         .p1_mpdgctrl1 = 0x030C0258,
 368         .p0_mprddlctl = 0x3E343A40,
 369         .p1_mprddlctl = 0x383C3844,
 370         .p0_mpwrdlctl = 0x40404440,
 371         .p1_mpwrdlctl = 0x4C3E4446,
 372 };
 373
 374 /* DDR 64bit */
 375 static struct mx6_ddr_sysinfo mem_q = {
 376         .ddr_type       = DDR_TYPE_DDR3,
 377         .dsize          = 2,
 378         .cs1_mirror     = 0,
 379         /* config for full 4GB range so that get_mem_size() works */
 380         .cs_density     = 32,
 381         .ncs            = 1,
 382         .bi_on          = 1,
 383         .rtt_nom        = 2,
 384         .rtt_wr         = 2,
 385         .ralat          = 5,
 386         .walat          = 0,
 387         .mif3_mode      = 3,
 388         .rst_to_cke     = 0x23,
 389         .sde_to_rst     = 0x10,
 390 };
 391
 392 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 393         .p0_mpwldectrl0 = 0x001F0024,
 394         .p0_mpwldectrl1 = 0x00110018,
 395         .p1_mpwldectrl0 = 0x001F0024,
 396         .p1_mpwldectrl1 = 0x00110018,
 397         .p0_mpdgctrl0 = 0x4230022C,
 398         .p0_mpdgctrl1 = 0x02180220,
 399         .p1_mpdgctrl0 = 0x42440248,
 400         .p1_mpdgctrl1 = 0x02300238,
 401         .p0_mprddlctl = 0x44444A48,
 402         .p1_mprddlctl = 0x46484A42,
 403         .p0_mpwrdlctl = 0x38383234,
 404         .p1_mpwrdlctl = 0x3C34362E,
 405 };
 406
 407 /* DDR 64bit 1GB */
 408 static struct mx6_ddr_sysinfo mem_dl = {
 409         .dsize          = 2,
 410         .cs1_mirror     = 0,
 411         /* config for full 4GB range so that get_mem_size() works */
 412         .cs_density     = 32,
 413         .ncs            = 1,
 414         .bi_on          = 1,
 415         .rtt_nom        = 1,
 416         .rtt_wr         = 1,
 417         .ralat          = 5,
 418         .walat          = 0,
 419         .mif3_mode      = 3,
 420         .rst_to_cke     = 0x23,
 421         .sde_to_rst     = 0x10,
 422 };
 423
 424 /* DDR 32bit 512MB */
 425 static struct mx6_ddr_sysinfo mem_s = {
 426         .dsize          = 1,
 427         .cs1_mirror     = 0,
 428         /* config for full 4GB range so that get_mem_size() works */
 429         .cs_density     = 32,
 430         .ncs            = 1,
 431         .bi_on          = 1,
 432         .rtt_nom        = 1,
 433         .rtt_wr         = 1,
 434         .ralat          = 5,
 435         .walat          = 0,
 436         .mif3_mode      = 3,
 437         .rst_to_cke     = 0x23,
 438         .sde_to_rst     = 0x10,
 439 };
 440
 441 static void ccgr_init(void)
 442 {
 443         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 444
 445         writel(0x00003F3F, &ccm->CCGR0);
 446         writel(0x0030FC00, &ccm->CCGR1);
 447         writel(0x000FC000, &ccm->CCGR2);
 448         writel(0x3F300000, &ccm->CCGR3);
 449         writel(0xFF00F300, &ccm->CCGR4);
 450         writel(0x0F0000C3, &ccm->CCGR5);
 451         writel(0x000003CC, &ccm->CCGR6);
 452 }
 453
 454 static void gpr_init(void)
 455 {
 456         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 457
 458         /* enable AXI cache for VDOA/VPU/IPU */
 459         writel(0xF00000CF, &iomux->gpr[4]);
 460         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 461         writel(0x007F007F, &iomux->gpr[6]);
 462         writel(0x007F007F, &iomux->gpr[7]);
 463 }
 464
 465 static void spl_dram_init(void)
 466 {
 467         if (is_mx6solo()) {
 468                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 469                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 470         } else if (is_mx6dl()) {
 471                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 472                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 473         } else if (is_mx6dq()) {
 474                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 475                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 476         }
 477
 478         udelay(100);
 479 }
 480
 481 void board_init_f(ulong dummy)
 482 {
 483         ccgr_init();
 484
 485         /* setup AIPS and disable watchdog */
 486         arch_cpu_init();
 487
 488         gpr_init();
 489
 490         /* iomux */
 491         board_early_init_f();
 492
 493         /* setup GP timer */
 494         timer_init();
 495
 496         /* UART clocks enabled and gd valid - init serial console */
 497         preloader_console_init();
 498
 499         /* DDR initialization */
 500         spl_dram_init();
 501
 502         /* Clear the BSS. */
 503         memset(__bss_start, 0, __bss_end - __bss_start);
 504
 505         /* load/boot image from boot device */
 506         board_init_r(NULL, 0);
 507 }
 508 #endif