board/engicam/isiotmx6ul/isiotmx6ul.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <mmc.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <linux/sizes.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/imx-common/iomux-v3.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE | \
  26                         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  27                         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  28
  29 static iomux_v3_cfg_t const uart1_pads[] = {
  30         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  31         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  32 };
  33
  34 int board_early_init_f(void)
  35 {
  36         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  37
  38         return 0;
  39 }
  40
  41 #ifdef CONFIG_NAND_MXS
  42
  43 #define GPMI_PAD_CTRL0          (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  44 #define GPMI_PAD_CTRL1          (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  45                                 PAD_CTL_SRE_FAST)
  46 #define GPMI_PAD_CTRL2          (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  47
  48 static iomux_v3_cfg_t const nand_pads[] = {
  49         MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  50         MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  51         MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  52         MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  53         MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  54         MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  55         MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  56         MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  57         MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  58         MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  59         MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  60         MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  61         MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  62         MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  63         MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  64 };
  65
  66 static void setup_gpmi_nand(void)
  67 {
  68         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  69
  70         /* config gpmi nand iomux */
  71         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  72
  73         clrbits_le32(&mxc_ccm->CCGR4,
  74                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  75                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  76                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  77                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  78                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  79
  80         /*
  81          * config gpmi and bch clock to 100 MHz
  82          * bch/gpmi select PLL2 PFD2 400M
  83          * 100M = 400M / 4
  84          */
  85         clrbits_le32(&mxc_ccm->cscmr1,
  86                      MXC_CCM_CSCMR1_BCH_CLK_SEL |
  87                      MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  88         clrsetbits_le32(&mxc_ccm->cscdr1,
  89                         MXC_CCM_CSCDR1_BCH_PODF_MASK |
  90                         MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  91                         (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  92                         (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  93
  94         /* enable gpmi and bch clock gating */
  95         setbits_le32(&mxc_ccm->CCGR4,
  96                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  97                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  98                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  99                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 100                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 101
 102         /* enable apbh clock gating */
 103         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 104 }
 105 #endif /* CONFIG_NAND_MXS */
 106
 107 #ifdef CONFIG_ENV_IS_IN_MMC
 108 int board_mmc_get_env_dev(int devno)
 109 {
 110         /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
 111         return (devno == 0) ? 0 : 1;
 112 }
 113
 114 static void mmc_late_init(void)
 115 {
 116         char cmd[32];
 117         char mmcblk[32];
 118         u32 dev_no = mmc_get_env_dev();
 119
 120         setenv_ulong("mmcdev", dev_no);
 121
 122         /* Set mmcblk env */
 123         sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
 124         setenv("mmcroot", mmcblk);
 125
 126         sprintf(cmd, "mmc dev %d", dev_no);
 127         run_command(cmd, 0);
 128 }
 129 #endif
 130
 131 int board_late_init(void)
 132 {
 133         switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
 134                         IMX6_BMODE_SHIFT) {
 135         case IMX6_BMODE_SD:
 136         case IMX6_BMODE_ESD:
 137         case IMX6_BMODE_MMC:
 138         case IMX6_BMODE_EMMC:
 139 #ifdef CONFIG_ENV_IS_IN_MMC
 140                 mmc_late_init();
 141 #endif
 142                 setenv("modeboot", "mmcboot");
 143                 break;
 144         case IMX6_BMODE_NAND:
 145                 setenv("modeboot", "nandboot");
 146                 break;
 147         default:
 148                 setenv("modeboot", "");
 149                 break;
 150         }
 151
 152         return 0;
 153 }
 154
 155 int board_init(void)
 156 {
 157         /* Address of boot parameters */
 158         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 159
 160 #ifdef CONFIG_NAND_MXS
 161         setup_gpmi_nand();
 162 #endif
 163         return 0;
 164 }
 165
 166 int dram_init(void)
 167 {
 168         gd->ram_size = imx_ddr_size();
 169
 170         return 0;
 171 }
 172
 173 #ifdef CONFIG_SPL_BUILD
 174 #include <libfdt.h>
 175 #include <spl.h>
 176
 177 #include <asm/arch/crm_regs.h>
 178 #include <asm/arch/mx6-ddr.h>
 179
 180 /* MMC board initialization is needed till adding DM support in SPL */
 181 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 182 #include <mmc.h>
 183 #include <fsl_esdhc.h>
 184
 185 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 186         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 187         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 188
 189 static iomux_v3_cfg_t const usdhc1_pads[] = {
 190         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 191         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 192         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 193         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 194         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 195         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 196
 197         /* VSELECT */
 198         MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 199         /* CD */
 200         MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 201         /* RST_B */
 202         MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 203 };
 204
 205 static iomux_v3_cfg_t const usdhc2_pads[] = {
 206         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 207         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 208         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 209         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 210         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 211         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 212         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 213         MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 214         MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 215 };
 216
 217 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 19)
 218 #define USDHC2_CD_GPIO  IMX_GPIO_NR(4, 5)
 219
 220 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 221         {USDHC1_BASE_ADDR, 0, 4},
 222         {USDHC2_BASE_ADDR, 0, 8},
 223 };
 224
 225 int board_mmc_getcd(struct mmc *mmc)
 226 {
 227         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 228         int ret = 0;
 229
 230         switch (cfg->esdhc_base) {
 231         case USDHC1_BASE_ADDR:
 232                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 233                 break;
 234         case USDHC2_BASE_ADDR:
 235                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 236                 break;
 237         }
 238
 239         return ret;
 240 }
 241
 242 int board_mmc_init(bd_t *bis)
 243 {
 244         int i, ret;
 245
 246         /*
 247         * According to the board_mmc_init() the following map is done:
 248         * (U-boot device node)    (Physical Port)
 249         * mmc0                          USDHC1
 250         * mmc1                          USDHC2
 251         */
 252         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 253                 switch (i) {
 254                 case 0:
 255                         imx_iomux_v3_setup_multiple_pads(
 256                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 257                         gpio_direction_input(USDHC1_CD_GPIO);
 258                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 259                         break;
 260                 case 1:
 261                         imx_iomux_v3_setup_multiple_pads(
 262                                 usdhc1_pads, ARRAY_SIZE(usdhc2_pads));
 263                         gpio_direction_input(USDHC2_CD_GPIO);
 264                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 265                         break;
 266                 default:
 267                         printf("Warning - USDHC%d controller not supporting\n",
 268                                i + 1);
 269                         return 0;
 270                 }
 271
 272                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 273                 if (ret) {
 274                         printf("Warning: failed to initialize mmc dev %d\n", i);
 275                         return ret;
 276                 }
 277         }
 278
 279         return 0;
 280 }
 281
 282 #ifdef CONFIG_ENV_IS_IN_MMC
 283 void board_boot_order(u32 *spl_boot_list)
 284 {
 285         u32 bmode = imx6_src_get_boot_mode();
 286         u8 boot_dev = BOOT_DEVICE_MMC1;
 287
 288         switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
 289         case IMX6_BMODE_SD:
 290         case IMX6_BMODE_ESD:
 291                 /* SD/eSD - BOOT_DEVICE_MMC1 */
 292                 break;
 293         case IMX6_BMODE_MMC:
 294         case IMX6_BMODE_EMMC:
 295                 /* MMC/eMMC */
 296                 boot_dev = BOOT_DEVICE_MMC2;
 297                 break;
 298         default:
 299                 /* Default - BOOT_DEVICE_MMC1 */
 300                 printf("Wrong board boot order\n");
 301                 break;
 302         }
 303
 304         spl_boot_list[0] = boot_dev;
 305 }
 306 #endif
 307 #endif /* CONFIG_FSL_ESDHC */
 308
 309 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 310         .grp_addds = 0x00000030,
 311         .grp_ddrmode_ctl = 0x00020000,
 312         .grp_b0ds = 0x00000030,
 313         .grp_ctlds = 0x00000030,
 314         .grp_b1ds = 0x00000030,
 315         .grp_ddrpke = 0x00000000,
 316         .grp_ddrmode = 0x00020000,
 317         .grp_ddr_type = 0x000c0000,
 318 };
 319
 320 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 321         .dram_dqm0 = 0x00000030,
 322         .dram_dqm1 = 0x00000030,
 323         .dram_ras = 0x00000030,
 324         .dram_cas = 0x00000030,
 325         .dram_odt0 = 0x00000030,
 326         .dram_odt1 = 0x00000030,
 327         .dram_sdba2 = 0x00000000,
 328         .dram_sdclk_0 = 0x00000008,
 329         .dram_sdqs0 = 0x00000038,
 330         .dram_sdqs1 = 0x00000030,
 331         .dram_reset = 0x00000030,
 332 };
 333
 334 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 335         .p0_mpwldectrl0 = 0x00070007,
 336         .p0_mpdgctrl0 = 0x41490145,
 337         .p0_mprddlctl = 0x40404546,
 338         .p0_mpwrdlctl = 0x4040524D,
 339 };
 340
 341 struct mx6_ddr_sysinfo ddr_sysinfo = {
 342         .dsize = 0,
 343         .cs_density = 20,
 344         .ncs = 1,
 345         .cs1_mirror = 0,
 346         .rtt_wr = 2,
 347         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 348         .walat = 1,             /* Write additional latency */
 349         .ralat = 5,             /* Read additional latency */
 350         .mif3_mode = 3,         /* Command prediction working mode */
 351         .bi_on = 1,             /* Bank interleaving enabled */
 352         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 353         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 354         .ddr_type = DDR_TYPE_DDR3,
 355 };
 356
 357 static struct mx6_ddr3_cfg mem_ddr = {
 358         .mem_speed = 800,
 359         .density = 4,
 360         .width = 16,
 361         .banks = 8,
 362         .rowaddr = 15,
 363         .coladdr = 10,
 364         .pagesz = 2,
 365         .trcd = 1375,
 366         .trcmin = 4875,
 367         .trasmin = 3500,
 368 };
 369
 370 static void ccgr_init(void)
 371 {
 372         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 373
 374         writel(0x00c03f3f, &ccm->CCGR0);
 375         writel(0xfcffff00, &ccm->CCGR1);
 376         writel(0x0cffffcc, &ccm->CCGR2);
 377         writel(0x3f3c3030, &ccm->CCGR3);
 378         writel(0xff00fffc, &ccm->CCGR4);
 379         writel(0x033f30ff, &ccm->CCGR5);
 380         writel(0x00c00fff, &ccm->CCGR6);
 381 }
 382
 383 static void spl_dram_init(void)
 384 {
 385         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 386         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 387 }
 388
 389 void board_init_f(ulong dummy)
 390 {
 391         /* setup AIPS and disable watchdog */
 392         arch_cpu_init();
 393
 394         ccgr_init();
 395
 396         /* iomux and setup of i2c */
 397         board_early_init_f();
 398
 399         /* setup GP timer */
 400         timer_init();
 401
 402         /* UART clocks enabled and gd valid - init serial console */
 403         preloader_console_init();
 404
 405         /* DDR initialization */
 406         spl_dram_init();
 407
 408         /* Clear the BSS. */
 409         memset(__bss_start, 0, __bss_end - __bss_start);
 410
 411         /* load/boot image from boot device */
 412         board_init_r(NULL, 0);
 413 }
 414 #endif /* CONFIG_SPL_BUILD */