board/esd/cpci2dp/cpci2dp.c

   1 /*
   2  * (C) Copyright 2005
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/processor.h>
  10 #include <asm/io.h>
  11 #include <command.h>
  12 #include <malloc.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 int board_early_init_f (void)
  17 {
  18         unsigned long CPC0_CR0Reg;
  19
  20         /*
  21          * Setup GPIO pins
  22          */
  23         CPC0_CR0Reg = mfdcr(CPC0_CR0);
  24         mtdcr(CPC0_CR0, CPC0_CR0Reg |
  25               ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
  26                 CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
  27
  28         /* set output pins to high */
  29         out_be32((void *)GPIO0_OR,  CONFIG_SYS_EEPROM_WP);
  30         /* setup for output (LED=off) */
  31         out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
  32
  33         /*
  34          * IRQ 0-15  405GP internally generated; active high; level sensitive
  35          * IRQ 16    405GP internally generated; active low; level sensitive
  36          * IRQ 17-24 RESERVED
  37          * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
  38          * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
  39          * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
  40          * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
  41          * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  42          * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
  43          * IRQ 31 (EXT IRQ 6) unused
  44          */
  45         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  46         mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
  47         mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical*/
  48         mtdcr(UIC0PR, 0xFFFFFF81);      /* set int polarities */
  49
  50         mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
  51         mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest priority*/
  52         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  53
  54         return 0;
  55 }
  56
  57 int misc_init_r (void)
  58 {
  59         unsigned long CPC0_CR0Reg;
  60
  61         /* adjust flash start and offset */
  62         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  63         gd->bd->bi_flashoffset = 0;
  64
  65         /*
  66          * Select cts (and not dsr) on uart1
  67          */
  68         CPC0_CR0Reg = mfdcr(CPC0_CR0);
  69         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
  70
  71         return (0);
  72 }
  73
  74
  75 /*
  76  * Check Board Identity:
  77  */
  78 int checkboard (void)
  79 {
  80         char str[64];
  81         int i = getenv_f("serial#", str, sizeof(str));
  82
  83         puts ("Board: ");
  84
  85         if (i == -1) {
  86                 puts ("### No HW ID - assuming CPCI2DP");
  87         } else {
  88                 puts(str);
  89         }
  90
  91         printf(" (Ver 1.0)");
  92
  93         putc ('\n');
  94
  95         return 0;
  96 }
  97
  98 #if defined(CONFIG_SYS_EEPROM_WREN)
  99 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 100  *         <state>     -1: deliver current state
 101  *                     0: disable write
 102  *                     1: enable write
 103  *  Returns:           -1: wrong device address
 104  *                      0: dis-/en- able done
 105  *                   0/1: current state if <state> was -1.
 106  */
 107 int eeprom_write_enable (unsigned dev_addr, int state) {
 108         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 109                 return -1;
 110         } else {
 111                 switch (state) {
 112                 case 1:
 113                         /* Enable write access, clear bit GPIO_SINT2. */
 114                         out_be32((void *)GPIO0_OR,
 115                                  in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 116                         state = 0;
 117                         break;
 118                 case 0:
 119                         /* Disable write access, set bit GPIO_SINT2. */
 120                         out_be32((void *)GPIO0_OR,
 121                                  in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 122                         state = 0;
 123                         break;
 124                 default:
 125                         /* Read current status back. */
 126                         state = (0 == (in_be32((void *)GPIO0_OR) &
 127                                        CONFIG_SYS_EEPROM_WP));
 128                         break;
 129                 }
 130         }
 131         return state;
 132 }
 133 #endif
 134
 135 #if defined(CONFIG_SYS_EEPROM_WREN)
 136 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 137 {
 138         int query = argc == 1;
 139         int state = 0;
 140
 141         if (query) {
 142                 /* Query write access state. */
 143                 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 144                 if (state < 0) {
 145                         puts ("Query of write access state failed.\n");
 146                 } else {
 147                         printf ("Write access for device 0x%0x is %sabled.\n",
 148                                 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 149                         state = 0;
 150                 }
 151         } else {
 152                 if ('0' == argv[1][0]) {
 153                         /* Disable write access. */
 154                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 155                 } else {
 156                         /* Enable write access. */
 157                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 158                 }
 159                 if (state < 0) {
 160                         puts ("Setup of write access state failed.\n");
 161                 }
 162         }
 163
 164         return state;
 165 }
 166
 167 U_BOOT_CMD(
 168         eepwren,        2,      0,      do_eep_wren,
 169         "Enable / disable / query EEPROM write access",
 170         ""
 171 );
 172 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */