board/esd/pmc440/init.S

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0+
   3  */
   4
   5 #include <asm-offsets.h>
   6 #include <ppc_asm.tmpl>
   7 #include <asm/mmu.h>
   8 #include <config.h>
   9
  10 /*
  11  * TLB TABLE
  12  *
  13  * This table is used by the cpu boot code to setup the initial tlb
  14  * entries. Rather than make broad assumptions in the cpu source tree,
  15  * this table lets each board set things up however they like.
  16  *
  17  *  Pointer to the table is returned in r1
  18  *
  19  */
  20     .section .bootpg,"ax"
  21     .globl tlbtab
  22
  23 tlbtab:
  24         tlbtab_start
  25
  26         /*
  27          * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  28          * speed up boot process. It is patched after relocation to enable SA_I
  29          */
  30         tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
  31
  32         /* TLB entries for DDR2 SDRAM are generated dynamically */
  33
  34 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
  35         /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  36         tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
  37 #endif
  38
  39         /* TLB-entry for PCI Memory */
  40         tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
  41         tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
  42         tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
  43         tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
  44
  45         /* TLB-entries for EBC */
  46         /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
  47          * tlb entry.
  48          * This dummy entry is only for convinience in order not to modify the
  49          * amount of entries. Currently OS/9 relies on this :-)
  50          */
  51         tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
  52
  53         /* TLB-entry for NAND */
  54         tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
  55
  56         /* TLB-entry for Internal Registers & OCM */
  57         tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
  58
  59         /*TLB-entry PCI registers*/
  60         tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
  61
  62         /* TLB-entry for peripherals */
  63         tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
  64
  65         /* TLB-entry PCI IO space */
  66         tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
  67
  68         /* TODO:  what about high IO space */
  69         tlbtab_end