2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
13 #include <fdt_support.h>
20 #include <fsl_esdhc.h>
22 #include <environment.h>
30 DECLARE_GLOBAL_DATA_PTR
;
34 static const char *freq
[3] = {"100.00MHZ", "156.25MHZ"};
35 #ifndef CONFIG_SD_BOOT
36 u8 cfg_rcw_src1
, cfg_rcw_src2
;
41 printf("Board: LS1043ARDB, boot from ");
46 cfg_rcw_src1
= CPLD_READ(cfg_rcw_src1
);
47 cfg_rcw_src2
= CPLD_READ(cfg_rcw_src2
);
48 cpld_rev_bit(&cfg_rcw_src1
);
49 cfg_rcw_src
= cfg_rcw_src1
;
50 cfg_rcw_src
= (cfg_rcw_src
<< 1) | cfg_rcw_src2
;
52 if (cfg_rcw_src
== 0x25)
53 printf("vBank %d\n", CPLD_READ(vbank
));
54 else if (cfg_rcw_src
== 0x106)
57 printf("Invalid setting of SW4\n");
60 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver
),
61 CPLD_READ(cpld_ver_sub
), CPLD_READ(pcba_ver
));
63 puts("SERDES Reference Clocks:\n");
64 sd1refclk_sel
= CPLD_READ(sd1refclk_sel
);
65 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq
[sd1refclk_sel
], freq
[0]);
72 gd
->ram_size
= initdram(0);
77 int board_early_init_f(void)
79 fsl_lsch2_early_init_f();
86 struct ccsr_cci400
*cci
= (struct ccsr_cci400
*)CONFIG_SYS_CCI400_ADDR
;
89 * Set CCI-400 control override register to enable barrier
92 out_le32(&cci
->ctrl_ord
, CCI400_CTRLORD_EN_BARRIER
);
95 init_final_memctl_regs();
98 #ifdef CONFIG_ENV_IS_NOWHERE
99 gd
->env_addr
= (ulong
)&default_environment
[0];
102 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
103 enable_layerscape_ns_access();
113 int config_board_mux(void)
115 struct ccsr_scfg
*scfg
= (struct ccsr_scfg
*)CONFIG_SYS_FSL_SCFG_ADDR
;
118 if (hwconfig("qe-hdlc")) {
119 out_be32(&scfg
->rcwpmuxcr0
,
120 (in_be32(&scfg
->rcwpmuxcr0
) & ~0xff00) | 0x6600);
121 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
122 in_be32(&scfg
->rcwpmuxcr0
));
124 #ifdef CONFIG_HAS_FSL_XHCI_USB
125 out_be32(&scfg
->rcwpmuxcr0
, 0x3333);
126 out_be32(&scfg
->usbdrvvbus_selcr
, SCFG_USBDRVVBUS_SELCR_USB1
);
127 usb_pwrfault
= (SCFG_USBPWRFAULT_DEDICATED
<<
128 SCFG_USBPWRFAULT_USB3_SHIFT
) |
129 (SCFG_USBPWRFAULT_DEDICATED
<<
130 SCFG_USBPWRFAULT_USB2_SHIFT
) |
131 (SCFG_USBPWRFAULT_SHARED
<<
132 SCFG_USBPWRFAULT_USB1_SHIFT
);
133 out_be32(&scfg
->usbpwrfault_selcr
, usb_pwrfault
);
139 #if defined(CONFIG_MISC_INIT_R)
140 int misc_init_r(void)
143 #ifdef CONFIG_SECURE_BOOT
144 /* In case of Secure Boot, the IBR configures the SMMU
145 * to allow only Secure transactions.
146 * SMMU must be reset in bypass mode.
147 * Set the ClientPD bit and Clear the USFCFG Bit
150 val
= (in_le32(SMMU_SCR0
) | SCR0_CLIENTPD_MASK
) & ~(SCR0_USFCFG_MASK
);
151 out_le32(SMMU_SCR0
, val
);
152 val
= (in_le32(SMMU_NSCR0
) | SCR0_CLIENTPD_MASK
) & ~(SCR0_USFCFG_MASK
);
153 out_le32(SMMU_NSCR0
, val
);
155 #ifdef CONFIG_FSL_CAAM
162 void fdt_del_qe(void *blob
)
166 while ((nodeoff
= fdt_node_offset_by_compatible(blob
, 0,
168 fdt_del_node(blob
, nodeoff
);
172 int ft_board_setup(void *blob
, bd_t
*bd
)
174 u64 base
[CONFIG_NR_DRAM_BANKS
];
175 u64 size
[CONFIG_NR_DRAM_BANKS
];
177 /* fixup DT for the two DDR banks */
178 base
[0] = gd
->bd
->bi_dram
[0].start
;
179 size
[0] = gd
->bd
->bi_dram
[0].size
;
180 base
[1] = gd
->bd
->bi_dram
[1].start
;
181 size
[1] = gd
->bd
->bi_dram
[1].size
;
183 fdt_fixup_memory_banks(blob
, base
, size
, 2);
184 ft_cpu_setup(blob
, bd
);
186 #ifdef CONFIG_SYS_DPAA_FMAN
187 fdt_fixup_fman_ethernet(blob
);
191 * qe-hdlc and usb multi-use the pins,
192 * when set hwconfig to qe-hdlc, delete usb node.
194 if (hwconfig("qe-hdlc"))
195 #ifdef CONFIG_HAS_FSL_XHCI_USB
196 fdt_del_node_and_alias(blob
, "usb1");
199 * qe just support qe-uart and qe-hdlc,
200 * if qe-uart and qe-hdlc are not set in hwconfig,
203 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
209 u8
flash_read8(void *addr
)
211 return __raw_readb(addr
+ 1);
214 void flash_write16(u16 val
, void *addr
)
216 u16 shftval
= (((val
>> 8) & 0xff) | ((val
<< 8) & 0xff00));
218 __raw_writew(shftval
, addr
);
221 u16
flash_read16(void *addr
)
223 u16 val
= __raw_readw(addr
);
225 return (((val
) >> 8) & 0x00ff) | (((val
) << 8) & 0xff00);