2 * Copyright 2017 General Electric Company
4 * Based on board/freescale/mx53loco/mx53loco_video.c:
6 * Copyright (C) 2012 Freescale Semiconductor, Inc.
7 * Fabio Estevam <fabio.estevam@freescale.com>
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/list.h>
15 #include <asm/arch/iomux-mx53.h>
17 #include <ipu_pixfmt.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/arch/imx-regs.h>
24 #define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
26 static struct fb_videomode
const nv_spwg
= {
27 .name
= "NV-SPWGRGB888",
39 .vmode
= FB_VMODE_NONINTERLACED
42 void setup_iomux_lcd(void)
44 static const iomux_v3_cfg_t lcd_pads
[] = {
45 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK
,
46 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15
,
47 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2
,
48 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3
,
49 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0
,
50 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1
,
51 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2
,
52 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3
,
53 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4
,
54 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5
,
55 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6
,
56 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7
,
57 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8
,
58 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9
,
59 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10
,
60 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11
,
61 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12
,
62 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13
,
63 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14
,
64 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15
,
65 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16
,
66 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17
,
67 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18
,
68 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19
,
69 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20
,
70 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21
,
71 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22
,
72 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23
,
75 imx_iomux_v3_setup_multiple_pads(lcd_pads
, ARRAY_SIZE(lcd_pads
));
78 static void lcd_enable(void)
80 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
81 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
83 /* Set LDB_DI0 as clock source for IPU_DI0 */
84 clrsetbits_le32(&mxc_ccm
->cscmr2
,
85 MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK
,
86 MXC_CCM_CSCMR2_DI0_CLK_SEL(
87 MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK
));
89 /* Turn on IPU LDB DI0 clocks */
90 setbits_le32(&mxc_ccm
->CCGR6
, MXC_CCM_CCGR6_LDB_DI0(3));
92 /* Turn on IPU DI0 clocks */
93 setbits_le32(&mxc_ccm
->CCGR6
, MXC_CCM_CCGR6_IPU_DI0(3));
96 writel(IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|
97 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
|
98 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0
,
101 /* Enable backlights */
104 /* duty cycle 5000000ns, period: 5000000ns */
105 pwm_config(1, 5000000, 5000000);
107 /* Backlight Power */
108 gpio_direction_output(BACKLIGHT_ENABLE
, 1);
113 static int do_lcd_enable(cmd_tbl_t
*cmdtp
, int flag
, int argc
,
121 ppd_lcd_enable
, 1, 1, do_lcd_enable
,
126 int board_video_skip(void)
130 ret
= ipuv3_fb_init(&nv_spwg
, 0, IPU_PIX_FMT_RGB24
);
132 printf("Display cannot be configured: %d\n", ret
);