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1 /*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36 #include <common.h>
37
38 #ifdef CONFIG_PCI
39 #include <pci.h>
40 #endif
41
42 void flash__init (void);
43 void ether__init (void);
44 void peripheral_power_enable (void);
45
46 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
47 void show_boot_progress(int progress)
48 {
49 printf("Boot reached stage %d\n", progress);
50 }
51 #endif
52
53 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
54
55 static inline void delay (unsigned long loops)
56 {
57 __asm__ volatile ("1:\n"
58 "subs %0, %1, #1\n"
59 "bne 1b":"=r" (loops):"0" (loops));
60 }
61
62 /*
63 * Miscellaneous platform dependent initialisations
64 */
65
66 int board_init (void)
67 {
68 DECLARE_GLOBAL_DATA_PTR;
69
70 /* arch number of Integrator Board */
71 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
72
73 /* adress of boot parameters */
74 gd->bd->bi_boot_params = 0x00000100;
75
76 gd->flags = 0;
77
78 #ifdef CONFIG_CM_REMAP
79 extern void cm_remap(void);
80 cm_remap(); /* remaps writeable memory to 0x00000000 */
81 #endif
82
83 icache_enable ();
84
85 flash__init ();
86 return 0;
87 }
88
89
90 int misc_init_r (void)
91 {
92 #ifdef CONFIG_PCI
93 pci_init();
94 #endif
95 setenv("verify", "n");
96 return (0);
97 }
98
99 /*
100 * Initialize PCI Devices, report devices found.
101 */
102 #ifdef CONFIG_PCI
103
104 #ifndef CONFIG_PCI_PNP
105
106 static struct pci_config_table pci_integrator_config_table[] = {
107 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
108 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
109 PCI_ENET0_MEMADDR,
110 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
111 { }
112 };
113 #endif
114
115 /* V3 access routines */
116 #define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
117 #define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
118
119 #define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
120 #define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
121
122 /* Compute address necessary to access PCI config space for the given */
123 /* bus and device. */
124 #define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \
125 unsigned int __address, __devicebit; \
126 unsigned short __mapaddress; \
127 unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \
128 \
129 if (__bus == 0) { \
130 /* local bus segment so need a type 0 config cycle */ \
131 /* build the PCI configuration "address" with one-hot in A31-A11 */ \
132 __address = PCI_CONFIG_BASE; \
133 __address |= ((__devfn & 0x07) << 8); \
134 __address |= __offset & 0xFF; \
135 __mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \
136 __devicebit = (1 << (__dev + 11)); \
137 \
138 if ((__devicebit & 0xFF000000) != 0) { \
139 /* high order bits are handled by the MAP register */ \
140 __mapaddress |= (__devicebit >> 16); \
141 } else { \
142 /* low order bits handled directly in the address */ \
143 __address |= __devicebit; \
144 } \
145 } else { /* bus !=0 */ \
146 /* not the local bus segment so need a type 1 config cycle */ \
147 /* A31-A24 are don't care (so clear to 0) */ \
148 __mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \
149 __address = PCI_CONFIG_BASE; \
150 __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \
151 __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \
152 __address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number */ \
153 __address |= __offset & 0xFF; /* bits 7..0 = register number */ \
154 } \
155 _V3Write16 (V3_LB_MAP1, __mapaddress); \
156 __address; \
157 })
158
159 /* _V3OpenConfigWindow - open V3 configuration window */
160 #define _V3OpenConfigWindow() { \
161 /* Set up base0 to see all 512Mbytes of memory space (not */ \
162 /* prefetchable), this frees up base1 for re-use by configuration*/ \
163 /* memory */ \
164 \
165 _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
166 0x90 | V3_LB_BASE_M_ENABLE)); \
167 /* Set up base1 to point into configuration space, note that MAP1 */ \
168 /* register is set up by pciMakeConfigAddress(). */ \
169 \
170 _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \
171 0x40 | V3_LB_BASE_M_ENABLE)); \
172 }
173
174 /* _V3CloseConfigWindow - close V3 configuration window */
175 #define _V3CloseConfigWindow() { \
176 /* Reassign base1 for use by prefetchable PCI memory */ \
177 _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \
178 | 0x84 | V3_LB_BASE_M_ENABLE)); \
179 _V3Write16 (V3_LB_MAP1, \
180 (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \
181 \
182 /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \
183 \
184 _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
185 0x80 | V3_LB_BASE_M_ENABLE)); \
186 }
187
188 static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev,
189 int offset, unsigned char *val)
190 {
191 _V3OpenConfigWindow ();
192 *val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
193 PCI_FUNC (dev),
194 offset);
195 _V3CloseConfigWindow ();
196
197 return 0;
198 }
199
200 static int pci_integrator_read__word (struct pci_controller *hose,
201 pci_dev_t dev, int offset,
202 unsigned short *val)
203 {
204 _V3OpenConfigWindow ();
205 *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
206 PCI_FUNC (dev),
207 offset);
208 _V3CloseConfigWindow ();
209
210 return 0;
211 }
212
213 static int pci_integrator_read_dword (struct pci_controller *hose,
214 pci_dev_t dev, int offset,
215 unsigned int *val)
216 {
217 _V3OpenConfigWindow ();
218 *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
219 PCI_FUNC (dev),
220 offset);
221 *val |= (*(volatile unsigned int *)
222 PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev),
223 (offset + 2))) << 16;
224 _V3CloseConfigWindow ();
225
226 return 0;
227 }
228
229 static int pci_integrator_write_byte (struct pci_controller *hose,
230 pci_dev_t dev, int offset,
231 unsigned char val)
232 {
233 _V3OpenConfigWindow ();
234 *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
235 PCI_FUNC (dev),
236 offset) = val;
237 _V3CloseConfigWindow ();
238
239 return 0;
240 }
241
242 static int pci_integrator_write_word (struct pci_controller *hose,
243 pci_dev_t dev, int offset,
244 unsigned short val)
245 {
246 _V3OpenConfigWindow ();
247 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
248 PCI_FUNC (dev),
249 offset) = val;
250 _V3CloseConfigWindow ();
251
252 return 0;
253 }
254
255 static int pci_integrator_write_dword (struct pci_controller *hose,
256 pci_dev_t dev, int offset,
257 unsigned int val)
258 {
259 _V3OpenConfigWindow ();
260 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
261 PCI_FUNC (dev),
262 offset) = (val & 0xFFFF);
263 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
264 PCI_FUNC (dev),
265 (offset + 2)) = ((val >> 16) & 0xFFFF);
266 _V3CloseConfigWindow ();
267
268 return 0;
269 }
270 /******************************
271 * PCI initialisation
272 ******************************/
273
274 struct pci_controller integrator_hose = {
275 #ifndef CONFIG_PCI_PNP
276 config_table: pci_integrator_config_table,
277 #endif
278 };
279
280 void pci_init_board (void)
281 {
282 volatile int i, j;
283 struct pci_controller *hose = &integrator_hose;
284
285 /* setting this register will take the V3 out of reset */
286
287 *(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1;
288
289 /* wait a few usecs to settle the device and the PCI bus */
290
291 for (i = 0; i < 100; i++)
292 j = i + 1;
293
294 /* Now write the Base I/O Address Word to V3_BASE + 0x6C */
295
296 *(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) =
297 (unsigned short) (V3_BASE >> 16);
298
299 do {
300 *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA;
301 *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) =
302 0x55;
303 } while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA
304 || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA +
305 4) != 0x55);
306
307 /* Make sure that V3 register access is not locked, if it is, unlock it */
308
309 if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &
310 V3_SYSTEM_M_LOCK)
311 == V3_SYSTEM_M_LOCK)
312 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F;
313
314 /* Ensure that the slave accesses from PCI are disabled while we */
315 /* setup windows */
316
317 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &=
318 ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
319
320 /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
321
322 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &=
323 ~V3_SYSTEM_M_RST_OUT;
324
325 /* Make all accesses from PCI space retry until we're ready for them */
326
327 *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |=
328 V3_PCI_CFG_M_RETRY_EN;
329
330 /* Set up any V3 PCI Configuration Registers that we absolutely have to */
331 /* LB_CFG controls Local Bus protocol. */
332 /* Enable LocalBus byte strobes for READ accesses too. */
333 /* set bit 7 BE_IMODE and bit 6 BE_OMODE */
334
335 *(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0;
336
337 /* PCI_CMD controls overall PCI operation. */
338 /* Enable PCI bus master. */
339
340 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04;
341
342 /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */
343
344 *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) =
345 (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M |
346 V3_PCI_MAP_M_REG_EN |
347 V3_PCI_MAP_M_ENABLE);
348
349 /* PCI_BASE0 is the PCI address of the start of the window */
350
351 *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) =
352 INTEGRATOR_BOOT_ROM_BASE;
353
354 /* PCI_MAP1 is LOCAL address of the start of the window */
355
356 *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) =
357 (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M |
358 V3_PCI_MAP_M_REG_EN |
359 V3_PCI_MAP_M_ENABLE);
360
361 /* PCI_BASE1 is the PCI address of the start of the window */
362
363 *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) =
364 INTEGRATOR_HDR0_SDRAM_BASE;
365
366 /* Set up the windows from local bus memory into PCI configuration, */
367 /* I/O and Memory. */
368 /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
369
370 *(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) =
371 ((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
372 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0;
373
374 /* PCI Configuration, use LB_BASE1/LB_MAP1. */
375
376 /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
377 /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
378 /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
379
380 *(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) =
381 INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
382
383 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) =
384 ((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
385
386 /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
387
388 *(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) =
389 INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
390
391 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) =
392 (((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
393
394 /* Allow accesses to PCI Configuration space */
395 /* and set up A1, A0 for type 1 config cycles */
396
397 *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) =
398 ((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) &
399 ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) |
400 V3_PCI_CFG_M_AD_LOW0;
401
402 /* now we can allow in PCI MEMORY accesses */
403
404 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) =
405 (*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) |
406 V3_COMMAND_M_MEM_EN;
407
408 /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
409 /* initialise and lock the V3 system register so that no one else */
410 /* can play with it */
411
412 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
413 (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
414 V3_SYSTEM_M_RST_OUT;
415
416 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
417 (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
418 V3_SYSTEM_M_LOCK;
419
420 /*
421 * Register the hose
422 */
423 hose->first_busno = 0;
424 hose->last_busno = 0xff;
425
426 /* System memory space */
427 pci_set_region (hose->regions + 0,
428 0x00000000, 0x40000000, 0x01000000,
429 PCI_REGION_MEM | PCI_REGION_MEMORY);
430
431 /* PCI Memory - config space */
432 pci_set_region (hose->regions + 1,
433 0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM);
434
435 /* PCI V3 regs */
436 pci_set_region (hose->regions + 2,
437 0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM);
438
439 /* PCI I/O space */
440 pci_set_region (hose->regions + 3,
441 0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO);
442
443 pci_set_ops (hose,
444 pci_integrator_read_byte,
445 pci_integrator_read__word,
446 pci_integrator_read_dword,
447 pci_integrator_write_byte,
448 pci_integrator_write_word, pci_integrator_write_dword);
449
450 hose->region_count = 4;
451
452 pci_register_hose (hose);
453
454 pciauto_config_init (hose);
455 pciauto_config_device (hose, 0);
456
457 hose->last_busno = pci_hose_scan (hose);
458 }
459 #endif
460
461 /******************************
462 Routine:
463 Description:
464 ******************************/
465 void flash__init (void)
466 {
467 }
468 /*************************************************************
469 Routine:ether__init
470 Description: take the Ethernet controller out of reset and wait
471 for the EEPROM load to complete.
472 *************************************************************/
473 void ether__init (void)
474 {
475 }
476
477 /******************************
478 Routine:
479 Description:
480 ******************************/
481 int dram_init (void)
482 {
483 DECLARE_GLOBAL_DATA_PTR;
484
485 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
486 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
487
488 #ifdef CONFIG_CM_SPD_DETECT
489 {
490 extern void dram_query(void);
491 unsigned long cm_reg_sdram;
492 unsigned long sdram_shift;
493
494 dram_query(); /* Assembler accesses to CM registers */
495 /* Queries the SPD values */
496
497 /* Obtain the SDRAM size from the CM SDRAM register */
498
499 cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
500 /* Register SDRAM size
501 *
502 * 0xXXXXXXbbb000bb 16 MB
503 * 0xXXXXXXbbb001bb 32 MB
504 * 0xXXXXXXbbb010bb 64 MB
505 * 0xXXXXXXbbb011bb 128 MB
506 * 0xXXXXXXbbb100bb 256 MB
507 *
508 */
509 sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
510 gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
511
512 }
513 #endif /* CM_SPD_DETECT */
514
515 return 0;
516 }
517
518 /* The Integrator/AP timer1 is clocked at 24MHz
519 * can be divided by 16 or 256
520 * and is a 16-bit counter
521 */
522 /* U-Boot expects a 32 bit timer running at CFG_HZ*/
523 static ulong timestamp; /* U-Boot ticks since startup */
524 static ulong total_count = 0; /* Total timer count */
525 static ulong lastdec; /* Timer reading at last call */
526 static ulong div_clock = 256; /* Divisor applied to the timer clock */
527 static ulong div_timer = 1; /* Divisor to convert timer reading
528 * change to U-Boot ticks
529 */
530 /* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */
531
532 #define TIMER_LOAD_VAL 0x0000FFFFL
533 #define READ_TIMER ((*(volatile ulong *)(CFG_TIMERBASE+4)) & 0x0000FFFFL)
534
535 /* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec
536 * - unless otherwise stated
537 */
538
539 /* starts a counter
540 * - the Integrator/AP timer issues an interrupt
541 * each time it reaches zero
542 */
543 int interrupt_init (void)
544 {
545 /* Load timer with initial value */
546 *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
547 /* Set timer to be
548 * enabled 1
549 * free-running 0
550 * XX 00
551 * divider 256 10
552 * XX 00
553 */
554 *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x00000088;
555 total_count = 0;
556 /* init the timestamp and lastdec value */
557 reset_timer_masked();
558
559 div_timer = CFG_HZ_CLOCK / CFG_HZ;
560 div_timer /= div_clock;
561
562 return (0);
563 }
564
565 /*
566 * timer without interrupts
567 */
568 void reset_timer (void)
569 {
570 reset_timer_masked ();
571 }
572
573 ulong get_timer (ulong base_ticks)
574 {
575 return get_timer_masked () - base_ticks;
576 }
577
578 void set_timer (ulong ticks)
579 {
580 timestamp = ticks;
581 total_count = ticks * div_timer;
582 reset_timer_masked();
583 }
584
585 /* delay x useconds */
586 void udelay (unsigned long usec)
587 {
588 ulong tmo, tmp;
589
590 /* Convert to U-Boot ticks */
591 tmo = usec * CFG_HZ;
592 tmo /= (1000000L);
593
594 tmp = get_timer_masked(); /* get current timestamp */
595 tmo += tmp; /* wake up timestamp */
596
597 while (get_timer_masked () < tmo) { /* loop till event */
598 /*NOP*/;
599 }
600 }
601
602 void reset_timer_masked (void)
603 {
604 /* reset time */
605 lastdec = READ_TIMER; /* capture current decrementer value */
606 timestamp = 0; /* start "advancing" time stamp from 0 */
607 }
608
609 /* converts the timer reading to U-Boot ticks */
610 /* the timestamp is the number of ticks since reset */
611 /* This routine does not detect wraps unless called regularly
612 ASSUMES a call at least every 16 seconds to detect every reload */
613 ulong get_timer_masked (void)
614 {
615 ulong now = READ_TIMER; /* current count */
616
617 if (now > lastdec) {
618 /* Must have wrapped */
619 total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
620 } else {
621 total_count += lastdec - now;
622 }
623 lastdec = now;
624 timestamp = total_count/div_timer;
625
626 return timestamp;
627 }
628
629 /* waits specified delay value and resets timestamp */
630 void udelay_masked (unsigned long usec)
631 {
632 udelay(usec);
633 }
634
635 /*
636 * This function is derived from PowerPC code (read timebase as long long).
637 * On ARM it just returns the timer value.
638 */
639 unsigned long long get_ticks(void)
640 {
641 return get_timer(0);
642 }
643
644 /*
645 * Return the timebase clock frequency
646 * i.e. how often the timer decrements
647 */
648 ulong get_tbclk (void)
649 {
650 return CFG_HZ_CLOCK/div_clock;
651 }
652
653 /* The Integrator/AP timer1 is clocked at 24MHz
654 * can be divided by 16 or 256
655 * and is a 16-bit counter
656 */
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