board/integratorap/platform.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2004, ARM Ltd.
   5  * Philippe Robin, <philippe.robin@arm.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <config.h>
  27 #include <version.h>
  28
  29         /* Reset using CM control register */
  30 .global reset_cpu
  31 reset_cpu:
  32         mov     r0, #CM_BASE
  33         ldr     r1,[r0,#OS_CTRL]
  34         orr     r1,r1,#CMMASK_RESET
  35         str     r1,[r0,#OS_CTRL]
  36
  37 reset_failed:
  38         b       reset_failed
  39
  40 /* set up the platform, once the cpu has been initialized */
  41 .globl platformsetup
  42 platformsetup:
  43         /* If U-Boot has been run after the ARM boot monitor
  44          * then all the necessary actions have been done
  45          * otherwise we are running from user flash mapped to 0x00000000
  46          * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
  47          * Changes to the (possibly soft) reset defaults of the processor
  48          * itself should be performed in cpu/arm<>/start.S
  49          * This function affects only the core module or board settings
  50          */
  51
  52 #ifdef CONFIG_CM_INIT
  53         /* CM has an initialization register
  54          * - bits in it are wired into test-chip pins to force
  55          *   reset defaults
  56          * - may need to change its contents for U-Boot
  57          */
  58
  59         /* set the desired CM specific value */
  60         mov     r2,#CMMASK_LOWVEC       /* Vectors at 0x00000000 for all */
  61
  62 #if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
  63         orr     r2,r2,#CMMASK_INIT_102
  64 #else
  65
  66 #if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
  67      !defined (CONFIG_CM940T)
  68
  69 #ifdef  CONFIG_CM_MULTIPLE_SSRAM
  70         /* set simple mapping             */
  71         and     r2,r2,#CMMASK_MAP_SIMPLE
  72 #endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
  73
  74 #ifdef  CONFIG_CM_TCRAM
  75         /* disable TCRAM                  */
  76         and     r2,r2,#CMMASK_TCRAM_DISABLE
  77 #endif /* #ifdef CONFIG_CM_TCRAM          */
  78
  79 #if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
  80             defined (CONFIG_CM1136JF_S)
  81
  82         and     r2,r2,#CMMASK_LE
  83
  84 #endif /* cpu with little endian initialization */
  85
  86         orr     r2,r2,#CMMASK_CMxx6_COMMON
  87
  88 #endif /* CMxx6 code */
  89
  90 #endif /* ARM102xxE value */
  91
  92         /* read CM_INIT    */
  93         mov     r0, #CM_BASE
  94         ldr     r1, [r0, #OS_INIT]
  95         /* check against desired bit setting */
  96         and     r3,r1,r2
  97         cmp     r3,r2
  98         beq     init_reg_OK
  99
 100         /* lock for change */
 101         mov     r3, #CMVAL_LOCK1
 102         add     r3,r3,#CMVAL_LOCK2
 103         str     r3, [r0, #OS_LOCK]
 104         /* set desired value */
 105         orr     r1,r1,r2
 106         /* write & relock CM_INIT */
 107         str     r1, [r0, #OS_INIT]
 108         mov     r1, #CMVAL_UNLOCK
 109         str     r1, [r0, #OS_LOCK]
 110
 111         /* soft reset so new values used */
 112         b       reset_cpu
 113
 114 init_reg_OK:
 115
 116 #endif /* CONFIG_CM_INIT */
 117
 118         mov     pc, lr
 119
 120 #ifdef  CONFIG_CM_SPD_DETECT
 121         /* Fast memory is available for the DRAM data
 122          * - ensure it has been transferred, then summarize the data
 123          *   into a CM register
 124          */
 125 .globl dram_query
 126 dram_query:
 127         stmfd   r13!,{r4-r6,lr}
 128         /* set up SDRAM info                              */
 129         /* - based on example code from the CM User Guide */
 130         mov     r0, #CM_BASE
 131
 132 readspdbit:
 133         ldr     r1, [r0, #OS_SDRAM]     /* read the SDRAM register */
 134         and     r1, r1, #0x20           /* mask SPD bit (5)        */
 135         cmp     r1, #0x20               /* test if set             */
 136         bne     readspdbit
 137
 138 setupsdram:
 139         add     r0, r0, #OS_SPD         /* address the copy of the SDP data */
 140         ldrb    r1, [r0, #3]            /* number of row address lines      */
 141         ldrb    r2, [r0, #4]            /* number of column address lines   */
 142         ldrb    r3, [r0, #5]            /* number of banks                  */
 143         ldrb    r4, [r0, #31]           /* module bank density              */
 144         mul     r5, r4, r3              /* size of SDRAM (MB divided by 4)  */
 145         mov     r5, r5, ASL#2           /* size in MB                       */
 146         mov     r0, #CM_BASE            /* reload for later code            */
 147         cmp     r5, #0x10               /* is it 16MB?                      */
 148         bne     not16
 149         mov     r6, #0x2                /* store size and CAS latency of 2  */
 150         b       writesize
 151
 152 not16:
 153         cmp     r5, #0x20               /* is it  32MB? */
 154         bne     not32
 155         mov     r6, #0x6
 156         b       writesize
 157
 158 not32:
 159         cmp     r5, #0x40               /* is it  64MB? */
 160         bne     not64
 161         mov     r6, #0xa
 162         b       writesize
 163
 164 not64:
 165         cmp     r5, #0x80               /* is it 128MB? */
 166         bne     not128
 167         mov     r6, #0xe
 168         b       writesize
 169
 170 not128:
 171         /* if it is none of these sizes then it is either 256MB, or
 172          * there is no SDRAM fitted so default to 256MB
 173          */
 174         mov     r6, #0x12
 175
 176 writesize:
 177         mov     r1, r1, ASL#8           /* row addr lines from SDRAM reg */
 178         orr     r2, r1, r2, ASL#12      /* OR in column address lines    */
 179         orr     r3, r2, r3, ASL#16      /* OR in number of banks         */
 180         orr     r6, r6, r3              /* OR in size and CAS latency    */
 181         str     r6, [r0, #OS_SDRAM]     /* store SDRAM parameters        */
 182
 183 #endif /* #ifdef CONFIG_CM_SPD_DETECT */
 184
 185         ldmfd   r13!,{r4-r6,pc}                 /* back to caller */
 186
 187 #ifdef  CONFIG_CM_REMAP
 188         /* CM remap bit is operational
 189          * - use it to map writeable memory at 0x00000000, in place of flash
 190          */
 191 .globl cm_remap
 192 cm_remap:
 193         stmfd   r13!,{r4-r10,lr}
 194
 195         mov     r0, #CM_BASE
 196         ldr     r1, [r0, #OS_CTRL]
 197         orr     r1, r1, #CMMASK_REMAP   /* set remap and led bits */
 198         str     r1, [r0, #OS_CTRL]
 199
 200         /* Now 0x00000000 is writeable, replace the vectors  */
 201         ldr     r0, =_start     /* r0 <- start of vectors           */
 202         ldr     r2, =_armboot_start     /* r2 <- past vectors               */
 203         sub     r1,r1,r1                /* destination 0x00000000           */
 204
 205 copy_vec:
 206         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 207         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 208         cmp     r0, r2                  /* until source end address [r2]    */
 209         ble     copy_vec
 210
 211         ldmfd   r13!,{r4-r10,pc}        /* back to caller                   */
 212
 213 #endif /* #ifdef CONFIG_CM_REMAP */