board/mosaixtech/icon/icon.c

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/ppc4xx.h>
  10 #include <i2c.h>
  11 #include <libfdt.h>
  12 #include <fdt_support.h>
  13 #include <netdev.h>
  14 #include <video.h>
  15 #include <asm/processor.h>
  16 #include <asm/io.h>
  17 #include <asm/ppc4xx-gpio.h>
  18 #include <asm/4xx_pcie.h>
  19 #include <linux/errno.h>
  20 #include <asm/mmu.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 int board_early_init_f(void)
  25 {
  26         unsigned long mfr;
  27
  28         /*
  29          * Interrupt controller setup for the ICON 440SPe board.
  30          *
  31          *--------------------------------------------------------------------
  32          * IRQ    | Source                            | Pol.  | Sensi.| Crit.
  33          *--------+-----------------------------------+-------+-------+-------
  34          * IRQ 00 | UART0                             | High  | Level | Non
  35          * IRQ 01 | UART1                             | High  | Level | Non
  36          * IRQ 02 | IIC0                              | High  | Level | Non
  37          * IRQ 03 | IIC1                              | High  | Level | Non
  38          * IRQ 04 | PCI0X0 MSG IN                     | High  | Level | Non
  39          * IRQ 05 | PCI0X0 CMD Write                  | High  | Level | Non
  40          * IRQ 06 | PCI0X0 Power Mgt                  | High  | Level | Non
  41          * IRQ 07 | PCI0X0 VPD Access                 | Rising| Edge  | Non
  42          * IRQ 08 | PCI0X0 MSI level 0                | High  | Lvl/ed| Non
  43          * IRQ 09 | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non
  44          * IRQ 10 | UIC2 Non-critical Int.            | NA    | NA    | Non
  45          * IRQ 11 | UIC2 Critical Interrupt           | NA    | NA    | Crit
  46          * IRQ 12 | PCI Express MSI Level 0           | Rising| Edge  | Non
  47          * IRQ 13 | PCI Express MSI Level 1           | Rising| Edge  | Non
  48          * IRQ 14 | PCI Express MSI Level 2           | Rising| Edge  | Non
  49          * IRQ 15 | PCI Express MSI Level 3           | Rising| Edge  | Non
  50          * IRQ 16 | UIC3 Non-critical Int.            | NA    | NA    | Non
  51          * IRQ 17 | UIC3 Critical Interrupt           | NA    | NA    | Crit
  52          * IRQ 18 | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non
  53          * IRQ 19 | DMA Channel 0 FIFO Full           | High  | Level | Non
  54          * IRQ 20 | DMA Channel 0 Stat FIFO           | High  | Level | Non
  55          * IRQ 21 | DMA Channel 1 FIFO Full           | High  | Level | Non
  56          * IRQ 22 | DMA Channel 1 Stat FIFO           | High  | Level | Non
  57          * IRQ 23 | I2O Inbound Doorbell              | High  | Level | Non
  58          * IRQ 24 | Inbound Post List FIFO Not Empt   | High  | Level | Non
  59          * IRQ 25 | I2O Region 0 LL PLB Write         | High  | Level | Non
  60          * IRQ 26 | I2O Region 1 LL PLB Write         | High  | Level | Non
  61          * IRQ 27 | I2O Region 0 HB PLB Write         | High  | Level | Non
  62          * IRQ 28 | I2O Region 1 HB PLB Write         | High  | Level | Non
  63          * IRQ 29 | GPT Down Count Timer              | Rising| Edge  | Non
  64          * IRQ 30 | UIC1 Non-critical Int.            | NA    | NA    | Non
  65          * IRQ 31 | UIC1 Critical Interrupt           | NA    | NA    | Crit.
  66          *--------------------------------------------------------------------
  67          * IRQ 32 | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non
  68          * IRQ 33 | MAL Serr                          | High  | Level | Non
  69          * IRQ 34 | MAL Txde                          | High  | Level | Non
  70          * IRQ 35 | MAL Rxde                          | High  | Level | Non
  71          * IRQ 36 | DMC CE or DMC UE                  | High  | Level | Non
  72          * IRQ 37 | EBC or UART2                      | High  |Lvl Edg| Non
  73          * IRQ 38 | MAL TX EOB                        | High  | Level | Non
  74          * IRQ 39 | MAL RX EOB                        | High  | Level | Non
  75          * IRQ 40 | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non
  76          * IRQ 41 | PCIX0 MSI level 2                 | High  |Lvl Edg| Non
  77          * IRQ 42 | PCIX0 MSI level 3                 | High  |Lvl Edg| Non
  78          * IRQ 43 | L2 Cache                          | Risin | Edge  | Non
  79          * IRQ 44 | GPT Compare Timer 0               | Risin | Edge  | Non
  80          * IRQ 45 | GPT Compare Timer 1               | Risin | Edge  | Non
  81          * IRQ 46 | GPT Compare Timer 2               | Risin | Edge  | Non
  82          * IRQ 47 | GPT Compare Timer 3               | Risin | Edge  | Non
  83          * IRQ 48 | GPT Compare Timer 4               | Risin | Edge  | Non
  84          * IRQ 49 | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non
  85          * IRQ 50 | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non
  86          * IRQ 51 | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non
  87          * IRQ 52 | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non
  88          * IRQ 53 | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non
  89          * IRQ 54 | DMA Error                         | High  | Level | Non
  90          * IRQ 55 | DMA I2O Error                     | High  | Level | Non
  91          * IRQ 56 | Serial ROM                        | High  | Level | Non
  92          * IRQ 57 | PCIX0 Error                       | High  | Edge  | Non
  93          * IRQ 58 | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non
  94          * IRQ 59 | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non
  95          * IRQ 60 | EMAC0 Interrupt                   | High  | Level | Non
  96          * IRQ 61 | EMAC0 Wake-up                     | High  | Level | Non
  97          * IRQ 62 | Reserved                          | High  | Level | Non
  98          * IRQ 63 | XOR                               | High  | Level | Non
  99          *--------------------------------------------------------------------
 100          * IRQ 64 | PE0 AL                            | High  | Level | Non
 101          * IRQ 65 | PE0 VPD Access                    | Risin | Edge  | Non
 102          * IRQ 66 | PE0 Hot Reset Request             | Risin | Edge  | Non
 103          * IRQ 67 | PE0 Hot Reset Request             | Falli | Edge  | Non
 104          * IRQ 68 | PE0 TCR                           | High  | Level | Non
 105          * IRQ 69 | PE0 BusMaster VCO                 | Falli | Edge  | Non
 106          * IRQ 70 | PE0 DCR Error                     | High  | Level | Non
 107          * IRQ 71 | Reserved                          | N/A   | N/A   | Non
 108          * IRQ 72 | PE1 AL                            | High  | Level | Non
 109          * IRQ 73 | PE1 VPD Access                    | Risin | Edge  | Non
 110          * IRQ 74 | PE1 Hot Reset Request             | Risin | Edge  | Non
 111          * IRQ 75 | PE1 Hot Reset Request             | Falli | Edge  | Non
 112          * IRQ 76 | PE1 TCR                           | High  | Level | Non
 113          * IRQ 77 | PE1 BusMaster VCO                 | Falli | Edge  | Non
 114          * IRQ 78 | PE1 DCR Error                     | High  | Level | Non
 115          * IRQ 79 | Reserved                          | N/A   | N/A   | Non
 116          * IRQ 80 | PE2 AL                            | High  | Level | Non
 117          * IRQ 81 | PE2 VPD Access                    | Risin | Edge  | Non
 118          * IRQ 82 | PE2 Hot Reset Request             | Risin | Edge  | Non
 119          * IRQ 83 | PE2 Hot Reset Request             | Falli | Edge  | Non
 120          * IRQ 84 | PE2 TCR                           | High  | Level | Non
 121          * IRQ 85 | PE2 BusMaster VCO                 | Falli | Edge  | Non
 122          * IRQ 86 | PE2 DCR Error                     | High  | Level | Non
 123          * IRQ 87 | Reserved                          | N/A   | N/A   | Non
 124          * IRQ 88 | External IRQ(5)                   | Progr | Progr | Non
 125          * IRQ 89 | External IRQ 4 - Ethernet         | Progr | Progr | Non
 126          * IRQ 90 | External IRQ 3 - PCI-X            | Progr | Progr | Non
 127          * IRQ 91 | External IRQ 2 - PCI-X            | Progr | Progr | Non
 128          * IRQ 92 | External IRQ 1 - PCI-X            | Progr | Progr | Non
 129          * IRQ 93 | External IRQ 0 - PCI-X            | Progr | Progr | Non
 130          * IRQ 94 | Reserved                          | N/A   | N/A   | Non
 131          * IRQ 95 | Reserved                          | N/A   | N/A   | Non
 132          *--------------------------------------------------------------------
 133          * IRQ 96 | PE0 INTA                          | High  | Level | Non
 134          * IRQ 97 | PE0 INTB                          | High  | Level | Non
 135          * IRQ 98 | PE0 INTC                          | High  | Level | Non
 136          * IRQ 99 | PE0 INTD                          | High  | Level | Non
 137          * IRQ 100| PE1 INTA                          | High  | Level | Non
 138          * IRQ 101| PE1 INTB                          | High  | Level | Non
 139          * IRQ 102| PE1 INTC                          | High  | Level | Non
 140          * IRQ 103| PE1 INTD                          | High  | Level | Non
 141          * IRQ 104| PE2 INTA                          | High  | Level | Non
 142          * IRQ 105| PE2 INTB                          | High  | Level | Non
 143          * IRQ 106| PE2 INTC                          | High  | Level | Non
 144          * IRQ 107| PE2 INTD                          | Risin | Edge  | Non
 145          * IRQ 108| PCI Express MSI Level 4           | Risin | Edge  | Non
 146          * IRQ 109| PCI Express MSI Level 5           | Risin | Edge  | Non
 147          * IRQ 110| PCI Express MSI Level 6           | Risin | Edge  | Non
 148          * IRQ 111| PCI Express MSI Level 7           | Risin | Edge  | Non
 149          * IRQ 116| PCI Express MSI Level 12          | Risin | Edge  | Non
 150          * IRQ 112| PCI Express MSI Level 8           | Risin | Edge  | Non
 151          * IRQ 113| PCI Express MSI Level 9           | Risin | Edge  | Non
 152          * IRQ 114| PCI Express MSI Level 10          | Risin | Edge  | Non
 153          * IRQ 115| PCI Express MSI Level 11          | Risin | Edge  | Non
 154          * IRQ 117| PCI Express MSI Level 13          | Risin | Edge  | Non
 155          * IRQ 118| PCI Express MSI Level 14          | Risin | Edge  | Non
 156          * IRQ 119| PCI Express MSI Level 15          | Risin | Edge  | Non
 157          * IRQ 120| PCI Express MSI Level 16          | Risin | Edge  | Non
 158          * IRQ 121| PCI Express MSI Level 17          | Risin | Edge  | Non
 159          * IRQ 122| PCI Express MSI Level 18          | Risin | Edge  | Non
 160          * IRQ 123| PCI Express MSI Level 19          | Risin | Edge  | Non
 161          * IRQ 124| PCI Express MSI Level 20          | Risin | Edge  | Non
 162          * IRQ 125| PCI Express MSI Level 21          | Risin | Edge  | Non
 163          * IRQ 126| PCI Express MSI Level 22          | Risin | Edge  | Non
 164          * IRQ 127| PCI Express MSI Level 23          | Risin | Edge  | Non
 165          */
 166
 167         /*
 168          * Put UICs in PowerPC 440SPe mode.
 169          * Initialise UIC registers. Clear all interrupts. Disable all
 170          * interrupts. Set critical interrupt values. Set interrupt polarities.
 171          * Set interrupt trigger levels. Make bit 0 High priority. Clear all
 172          * interrupts again.
 173          */
 174         mtdcr(UIC3SR, 0xffffffff);      /* Clear all interrupts */
 175         mtdcr(UIC3ER, 0x00000000);      /* disable all interrupts */
 176         mtdcr(UIC3CR, 0x00000000);      /* Set Critical / Non Critical IRQs */
 177         mtdcr(UIC3PR, 0xffffffff);      /* Set Interrupt Polarities*/
 178         mtdcr(UIC3TR, 0x001fffff);      /* Set Interrupt Trigger Levels */
 179         mtdcr(UIC3VR, 0x00000001);      /* Set Vect base=0,INT31 Highest prio */
 180         mtdcr(UIC3SR, 0x00000000);      /* clear all  interrupts*/
 181         mtdcr(UIC3SR, 0xffffffff);      /* clear all  interrupts*/
 182
 183         mtdcr(UIC2SR, 0xffffffff);      /* Clear all interrupts */
 184         mtdcr(UIC2ER, 0x00000000);      /* disable all interrupts*/
 185         mtdcr(UIC2CR, 0x00000000);      /* Set Critical / Non Critical IRQs */
 186         mtdcr(UIC2PR, 0xebebebff);      /* Set Interrupt Polarities*/
 187         mtdcr(UIC2TR, 0x74747400);      /* Set Interrupt Trigger Levels */
 188         mtdcr(UIC2VR, 0x00000001);      /* Set Vect base=0,INT31 Highest prio */
 189         mtdcr(UIC2SR, 0x00000000);      /* clear all interrupts */
 190         mtdcr(UIC2SR, 0xffffffff);      /* clear all interrupts */
 191
 192         mtdcr(UIC1SR, 0xffffffff);      /* Clear all interrupts*/
 193         mtdcr(UIC1ER, 0x00000000);      /* disable all interrupts*/
 194         mtdcr(UIC1CR, 0x00000000);      /* Set Critical / Non Critical IRQs */
 195         mtdcr(UIC1PR, 0xffffffff);      /* Set Interrupt Polarities */
 196         mtdcr(UIC1TR, 0x001f8040);      /* Set Interrupt Trigger Levels*/
 197         mtdcr(UIC1VR, 0x00000001);      /* Set Vect base=0,INT31 Highest prio */
 198         mtdcr(UIC1SR, 0x00000000);      /* clear all interrupts*/
 199         mtdcr(UIC1SR, 0xffffffff);      /* clear all interrupts*/
 200
 201         mtdcr(UIC0SR, 0xffffffff);      /* Clear all interrupts */
 202         mtdcr(UIC0ER, 0x00000000);      /* disable all int. excepted cascade */
 203         mtdcr(UIC0CR, 0x00104001);      /* Set Critical / Non Critical IRQs */
 204         mtdcr(UIC0PR, 0xffffffff);      /* Set Interrupt Polarities*/
 205         mtdcr(UIC0TR, 0x010f0004);      /* Set Interrupt Trigger Levels */
 206         mtdcr(UIC0VR, 0x00000001);      /* Set Vect base=0,INT31 Highest prio */
 207         mtdcr(UIC0SR, 0x00000000);      /* clear all interrupts*/
 208         mtdcr(UIC0SR, 0xffffffff);      /* clear all interrupts*/
 209
 210         mfsdr(SDR0_MFR, mfr);
 211         mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */
 212         mtsdr(SDR0_MFR, mfr);
 213
 214         mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
 215
 216         out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR);
 217         out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
 218         out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
 219
 220         return 0;
 221 }
 222
 223 int board_early_init_r(void)
 224 {
 225         /*
 226          * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 227          * boot EBC mapping only supports a maximum of 16MBytes
 228          * (4.ff00.0000 - 4.ffff.ffff).
 229          * To solve this problem, the FLASH has to get remapped to another
 230          * EBC address which accepts bigger regions:
 231          *
 232          * 0xfc00.0000 -> 4.ec00.0000
 233          */
 234
 235         /* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */
 236         mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 237
 238         /* Remove TLB entry of boot EBC mapping */
 239         remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
 240
 241         /* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */
 242         program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
 243                     CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
 244
 245         /*
 246          * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
 247          * 0xfc00.0000 is possible
 248          */
 249
 250         /*
 251          * Clear potential errors resulting from auto-calibration.
 252          * If not done, then we could get an interrupt later on when
 253          * exceptions are enabled.
 254          */
 255         set_mcsr(get_mcsr());
 256
 257         return 0;
 258 }
 259
 260 int checkboard(void)
 261 {
 262         char buf[64];
 263         int i = getenv_f("serial#", buf, sizeof(buf));
 264
 265         printf("Board: ICON");
 266         if (i > 0) {
 267                 puts(", serial# ");
 268                 puts(buf);
 269         }
 270         putc('\n');
 271
 272         return 0;
 273 }
 274
 275 /*
 276  * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
 277  * board specific values.
 278  *
 279  * Tested successfully with the following SODIMM:
 280  * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
 281  *
 282  * Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state,
 283  * directly after power-up. Only after running for more than 10 minutes
 284  * real stable auto-calibration windows could be found.
 285  */
 286 u32 ddr_wrdtr(u32 default_val)
 287 {
 288         return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV;
 289 }
 290
 291 u32 ddr_clktr(u32 default_val)
 292 {
 293         return SDRAM_CLKTR_CLKP_180_DEG_ADV;
 294 }
 295
 296 /*
 297  * Override the weak default implementation and return the
 298  * last PCIe slot number (max number - 1).
 299  */
 300 int board_pcie_last(void)
 301 {
 302         /* Only 2 PCIe ports used on ICON, so the last one is 1 */
 303         return 1;
 304 }
 305
 306 /*
 307  * Video
 308  */
 309 #ifdef CONFIG_VIDEO_SM501
 310 #include <sm501.h>
 311
 312 #define DISPLAY_WIDTH   640
 313 #define DISPLAY_HEIGHT  480
 314
 315 static const SMI_REGS sm502_init_regs[] = {
 316         {0x00004, 0x0},
 317         {0x00040, 0x00021847},
 318         {0x00044, 0x091a0a01}, /* 24 MHz pixclk */
 319         {0x00054, 0x0},
 320         {0x00048, 0x00021847},
 321         {0x0004C, 0x091a0a01},
 322         {0x00054, 0x1},
 323         {0x80004, 0xc428bb17},
 324         {0x8000C, 0x00000000},
 325         {0x80010, 0x0a000a00},
 326         {0x80014, 0x02800000},
 327         {0x80018, 0x01e00000},
 328         {0x8001C, 0x00000000},
 329         {0x80020, 0x01e00280},
 330         {0x80024, 0x02fa027f},
 331         {0x80028, 0x004a0280},
 332         {0x8002C, 0x020c01df},
 333         {0x80030, 0x000201e7},
 334         {0x80200, 0x00010000},
 335         {0x00008, 0x20000000}, /* gpio29 is pwm0, LED_PWM */
 336         {0x0000C, 0x3f000000}, /* gpio56 - gpio61 as flat panel data pins */
 337         {0x10020, 0x25725728}, /* 20 kHz pwm0, 50 % duty cycle, disabled */
 338         {0x80000, 0x0f010106}, /* vsync & hsync pos, disp on */
 339         {0, 0}
 340 };
 341
 342 /*
 343  * Return a pointer to the register initialization table.
 344  */
 345 const SMI_REGS *board_get_regs(void)
 346 {
 347         return sm502_init_regs;
 348 }
 349
 350 int board_get_width(void)
 351 {
 352         return DISPLAY_WIDTH;
 353 }
 354
 355 int board_get_height(void)
 356 {
 357         return DISPLAY_HEIGHT;
 358 }
 359
 360 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 361 /*
 362  * Return text to be printed besides the logo.
 363  */
 364 void video_get_info_str(int line_number, char *info)
 365 {
 366         if (line_number == 1)
 367                 strcpy(info, " Board: ICON");
 368         else
 369                 info[0] = '\0';
 370 }
 371 #endif
 372
 373 #endif /* CONFIG_VIDEO_SM501 */