2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
16 #include <asm/omap_sec_common.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/dra7xx_iodelay.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sata.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/omap.h>
27 #include <environment.h>
29 #include <linux/usb/gadget.h>
30 #include <dwc3-uboot.h>
31 #include <dwc3-omap-uboot.h>
32 #include <ti-usb-phy-uboot.h>
34 #include "../common/board_detect.h"
37 #define board_is_x15() board_ti_is("BBRDX15_")
38 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
39 !strncmp("B.10", board_ti_get_rev(), 3))
40 #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
41 !strncmp("C.00", board_ti_get_rev(), 3))
42 #define board_is_am572x_evm() board_ti_is("AM572PM_")
43 #define board_is_am572x_evm_reva3() \
44 (board_ti_is("AM572PM_") && \
45 !strncmp("A.30", board_ti_get_rev(), 3))
46 #define board_is_am572x_idk() board_ti_is("AM572IDK")
47 #define board_is_am571x_idk() board_ti_is("AM571IDK")
49 #ifdef CONFIG_DRIVER_TI_CPSW
53 DECLARE_GLOBAL_DATA_PTR
;
55 #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
57 #define GPIO_DDR_VTT_EN 203
59 /* Touch screen controller to identify the LCD */
60 #define OSD_TS_FT_BUS_ADDRESS 0
61 #define OSD_TS_FT_CHIP_ADDRESS 0x38
62 #define OSD_TS_FT_REG_ID 0xA3
64 * Touchscreen IDs for various OSD panels
65 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
67 /* Used on newer osd101t2587 Panels */
68 #define OSD_TS_FT_ID_5x46 0x54
69 /* Used on older osd101t2045 Panels */
70 #define OSD_TS_FT_ID_5606 0x08
72 #define SYSINFO_BOARD_NAME_MAX_LEN 45
74 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
75 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
77 const struct omap_sysinfo sysinfo
= {
78 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
81 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs
= {
82 .dmm_lisa_map_3
= 0x80740300,
86 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs
= {
87 .dmm_lisa_map_3
= 0x80640100,
91 void emif_get_dmm_regs(const struct dmm_lisa_map_regs
**dmm_lisa_regs
)
93 if (board_is_am571x_idk())
94 *dmm_lisa_regs
= &am571x_idk_lisa_regs
;
96 *dmm_lisa_regs
= &beagle_x15_lisa_regs
;
99 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs
= {
100 .sdram_config_init
= 0x61851b32,
101 .sdram_config
= 0x61851b32,
102 .sdram_config2
= 0x08000000,
103 .ref_ctrl
= 0x000040F1,
104 .ref_ctrl_final
= 0x00001035,
105 .sdram_tim1
= 0xcccf36ab,
106 .sdram_tim2
= 0x308f7fda,
107 .sdram_tim3
= 0x409f88a8,
108 .read_idle_ctrl
= 0x00050000,
109 .zq_config
= 0x5007190b,
110 .temp_alert_config
= 0x00000000,
111 .emif_ddr_phy_ctlr_1_init
= 0x0024400b,
112 .emif_ddr_phy_ctlr_1
= 0x0e24400b,
113 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
114 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
115 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
116 .emif_ddr_ext_phy_ctrl_4
= 0x009b009b,
117 .emif_ddr_ext_phy_ctrl_5
= 0x009e009e,
118 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
119 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
120 .emif_rd_wr_lvl_ctl
= 0x00000000,
121 .emif_rd_wr_exec_thresh
= 0x00000305
124 /* Ext phy ctrl regs 1-35 */
125 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
[] = {
163 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs
= {
164 .sdram_config_init
= 0x61851b32,
165 .sdram_config
= 0x61851b32,
166 .sdram_config2
= 0x08000000,
167 .ref_ctrl
= 0x000040F1,
168 .ref_ctrl_final
= 0x00001035,
169 .sdram_tim1
= 0xcccf36b3,
170 .sdram_tim2
= 0x308f7fda,
171 .sdram_tim3
= 0x407f88a8,
172 .read_idle_ctrl
= 0x00050000,
173 .zq_config
= 0x5007190b,
174 .temp_alert_config
= 0x00000000,
175 .emif_ddr_phy_ctlr_1_init
= 0x0024400b,
176 .emif_ddr_phy_ctlr_1
= 0x0e24400b,
177 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
178 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
179 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
180 .emif_ddr_ext_phy_ctrl_4
= 0x009b009b,
181 .emif_ddr_ext_phy_ctrl_5
= 0x009e009e,
182 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
183 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
184 .emif_rd_wr_lvl_ctl
= 0x00000000,
185 .emif_rd_wr_exec_thresh
= 0x00000305
188 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
[] = {
226 void emif_get_reg_dump(u32 emif_nr
, const struct emif_regs
**regs
)
230 *regs
= &beagle_x15_emif1_ddr3_532mhz_emif_regs
;
233 *regs
= &beagle_x15_emif2_ddr3_532mhz_emif_regs
;
238 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr
, const u32
**regs
, u32
*size
)
242 *regs
= beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
;
243 *size
= ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
);
246 *regs
= beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
;
247 *size
= ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
);
252 struct vcores_data beagle_x15_volts
= {
253 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
254 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
255 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
256 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
257 .mpu
.pmic
= &tps659038
,
258 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
260 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
261 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
262 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
263 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
264 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
265 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
266 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
267 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
268 .eve
.pmic
= &tps659038
,
269 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
271 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
272 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
273 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
274 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
275 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
276 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
277 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
278 .gpu
.addr
= TPS659038_REG_ADDR_SMPS45
,
279 .gpu
.pmic
= &tps659038
,
280 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
282 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
283 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
284 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
285 .core
.addr
= TPS659038_REG_ADDR_SMPS6
,
286 .core
.pmic
= &tps659038
,
288 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
289 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
290 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
291 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
292 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
293 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
294 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
295 .iva
.addr
= TPS659038_REG_ADDR_SMPS45
,
296 .iva
.pmic
= &tps659038
,
297 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
300 struct vcores_data am572x_idk_volts
= {
301 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
302 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
303 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
304 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
305 .mpu
.pmic
= &tps659038
,
306 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
308 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
309 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
310 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
311 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
312 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
313 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
314 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
315 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
316 .eve
.pmic
= &tps659038
,
317 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
319 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
320 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
321 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
322 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
323 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
324 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
325 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
326 .gpu
.addr
= TPS659038_REG_ADDR_SMPS6
,
327 .gpu
.pmic
= &tps659038
,
328 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
330 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
331 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
332 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
333 .core
.addr
= TPS659038_REG_ADDR_SMPS7
,
334 .core
.pmic
= &tps659038
,
336 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
337 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
338 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
339 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
340 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
341 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
342 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
343 .iva
.addr
= TPS659038_REG_ADDR_SMPS8
,
344 .iva
.pmic
= &tps659038
,
345 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
348 struct vcores_data am571x_idk_volts
= {
349 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
350 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
351 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
352 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
353 .mpu
.pmic
= &tps659038
,
354 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
356 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
357 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
358 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
359 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
360 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
361 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
362 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
363 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
364 .eve
.pmic
= &tps659038
,
365 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
367 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
368 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
369 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
370 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
371 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
372 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
373 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
374 .gpu
.addr
= TPS659038_REG_ADDR_SMPS6
,
375 .gpu
.pmic
= &tps659038
,
376 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
378 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
379 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
380 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
381 .core
.addr
= TPS659038_REG_ADDR_SMPS7
,
382 .core
.pmic
= &tps659038
,
384 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
385 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
386 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
387 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
388 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
389 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
390 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
391 .iva
.addr
= TPS659038_REG_ADDR_SMPS45
,
392 .iva
.pmic
= &tps659038
,
393 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
396 int get_voltrail_opp(int rail_offset
)
400 switch (rail_offset
) {
411 opp
= DRA7_DSPEVE_OPP
;
424 #ifdef CONFIG_SPL_BUILD
425 /* No env to setup for SPL */
426 static inline void setup_board_eeprom_env(void) { }
428 /* Override function to read eeprom information */
429 void do_board_detect(void)
433 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
434 CONFIG_EEPROM_CHIP_ADDRESS
);
436 printf("ti_i2c_eeprom_init failed %d\n", rc
);
439 #else /* CONFIG_SPL_BUILD */
441 /* Override function to read eeprom information: actual i2c read done by SPL*/
442 void do_board_detect(void)
447 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
448 CONFIG_EEPROM_CHIP_ADDRESS
);
450 printf("ti_i2c_eeprom_init failed %d\n", rc
);
453 bname
= "BeagleBoard X15";
454 else if (board_is_am572x_evm())
455 bname
= "AM572x EVM";
456 else if (board_is_am572x_idk())
457 bname
= "AM572x IDK";
458 else if (board_is_am571x_idk())
459 bname
= "AM571x IDK";
462 snprintf(sysinfo
.board_string
, SYSINFO_BOARD_NAME_MAX_LEN
,
463 "Board: %s REV %s\n", bname
, board_ti_get_rev());
466 static void setup_board_eeprom_env(void)
468 char *name
= "beagle_x15";
471 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
472 CONFIG_EEPROM_CHIP_ADDRESS
);
476 if (board_is_x15()) {
477 if (board_is_x15_revb1())
478 name
= "beagle_x15_revb1";
479 else if (board_is_x15_revc())
480 name
= "beagle_x15_revc";
483 } else if (board_is_am572x_evm()) {
484 if (board_is_am572x_evm_reva3())
485 name
= "am57xx_evm_reva3";
488 } else if (board_is_am572x_idk()) {
490 } else if (board_is_am571x_idk()) {
493 printf("Unidentified board claims %s in eeprom header\n",
494 board_ti_get_name());
498 set_board_info_env(name
);
501 #endif /* CONFIG_SPL_BUILD */
503 void vcores_init(void)
505 if (board_is_am572x_idk())
506 *omap_vcores
= &am572x_idk_volts
;
507 else if (board_is_am571x_idk())
508 *omap_vcores
= &am571x_idk_volts
;
510 *omap_vcores
= &beagle_x15_volts
;
513 void hw_data_init(void)
515 *prcm
= &dra7xx_prcm
;
516 *dplls_data
= &dra7xx_dplls
;
517 *ctrl
= &dra7xx_ctrl
;
520 bool am571x_idk_needs_lcd(void)
524 gpio_request(GPIO_ETH_LCD
, "nLCD_Detect");
525 if (gpio_get_value(GPIO_ETH_LCD
))
530 gpio_free(GPIO_ETH_LCD
);
538 gd
->bd
->bi_boot_params
= (CONFIG_SYS_SDRAM_BASE
+ 0x100);
543 void am57x_idk_lcd_detect(void)
546 char *idk_lcd
= "no";
549 /* Only valid for IDKs */
550 if (board_is_x15() || board_is_am572x_evm())
553 /* Only AM571x IDK has gpio control detect.. so check that */
554 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
557 r
= i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS
);
559 printf("%s: Failed to set bus address to %d: %d\n",
560 __func__
, OSD_TS_FT_BUS_ADDRESS
, r
);
563 r
= i2c_probe(OSD_TS_FT_CHIP_ADDRESS
);
565 /* AM572x IDK has no explicit settings for optional LCD kit */
566 if (board_is_am571x_idk()) {
567 printf("%s: Touch screen detect failed: %d!\n",
574 r
= i2c_read(OSD_TS_FT_CHIP_ADDRESS
, OSD_TS_FT_REG_ID
, 1, &buf
, 1);
576 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
577 __func__
, OSD_TS_FT_BUS_ADDRESS
, OSD_TS_FT_CHIP_ADDRESS
,
578 OSD_TS_FT_REG_ID
, r
);
583 case OSD_TS_FT_ID_5606
:
584 idk_lcd
= "osd101t2045";
586 case OSD_TS_FT_ID_5x46
:
587 idk_lcd
= "osd101t2587";
590 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
592 /* we will let default be "no lcd" */
595 env_set("idk_lcd", idk_lcd
);
599 int board_late_init(void)
601 setup_board_eeprom_env();
605 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
606 * This is the POWERHOLD-in-Low behavior.
608 palmas_i2c_write_u8(TPS65903X_CHIP_P1
, 0xA0, 0x1);
611 * Default FIT boot on HS devices. Non FIT images are not allowed
614 if (get_device_type() == HS_DEVICE
)
615 env_set("boot_fit", "1");
618 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
619 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
620 * PMIC Power off. So to be on the safer side set it back
621 * to POWERHOLD mode irrespective of the current state.
623 palmas_i2c_read_u8(TPS65903X_CHIP_P1
, TPS65903X_PRIMARY_SECONDARY_PAD2
,
625 val
= val
| TPS65903X_PAD2_POWERHOLD_MASK
;
626 palmas_i2c_write_u8(TPS65903X_CHIP_P1
, TPS65903X_PRIMARY_SECONDARY_PAD2
,
629 omap_die_id_serial();
630 omap_set_fastboot_vars();
632 am57x_idk_lcd_detect();
634 #if !defined(CONFIG_SPL_BUILD)
635 board_ti_set_ethaddr(2);
641 void set_muxconf_regs(void)
643 do_set_mux32((*ctrl
)->control_padconf_core_base
,
644 early_padconf
, ARRAY_SIZE(early_padconf
));
647 #ifdef CONFIG_IODELAY_RECALIBRATION
648 void recalibrate_iodelay(void)
650 const struct pad_conf_entry
*pconf
;
651 const struct iodelay_cfg_entry
*iod
, *delta_iod
;
652 int pconf_sz
, iod_sz
, delta_iod_sz
= 0;
655 if (board_is_am572x_idk()) {
656 pconf
= core_padconf_array_essential_am572x_idk
;
657 pconf_sz
= ARRAY_SIZE(core_padconf_array_essential_am572x_idk
);
658 iod
= iodelay_cfg_array_am572x_idk
;
659 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_am572x_idk
);
660 } else if (board_is_am571x_idk()) {
661 pconf
= core_padconf_array_essential_am571x_idk
;
662 pconf_sz
= ARRAY_SIZE(core_padconf_array_essential_am571x_idk
);
663 iod
= iodelay_cfg_array_am571x_idk
;
664 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_am571x_idk
);
666 /* Common for X15/GPEVM */
667 pconf
= core_padconf_array_essential_x15
;
668 pconf_sz
= ARRAY_SIZE(core_padconf_array_essential_x15
);
669 /* There never was an SR1.0 X15.. So.. */
670 if (omap_revision() == DRA752_ES1_1
) {
671 iod
= iodelay_cfg_array_x15_sr1_1
;
672 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1
);
674 /* Since full production should switch to SR2.0 */
675 iod
= iodelay_cfg_array_x15_sr2_0
;
676 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0
);
680 /* Setup I/O isolation */
681 ret
= __recalibrate_iodelay_start();
685 /* Do the muxing here */
686 do_set_mux32((*ctrl
)->control_padconf_core_base
, pconf
, pconf_sz
);
688 /* Now do the weird minor deltas that should be safe */
689 if (board_is_x15() || board_is_am572x_evm()) {
690 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
691 board_is_x15_revc()) {
692 pconf
= core_padconf_array_delta_x15_sr2_0
;
693 pconf_sz
= ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0
);
695 pconf
= core_padconf_array_delta_x15_sr1_1
;
696 pconf_sz
= ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1
);
698 do_set_mux32((*ctrl
)->control_padconf_core_base
, pconf
, pconf_sz
);
701 if (board_is_am571x_idk()) {
702 if (am571x_idk_needs_lcd()) {
703 pconf
= core_padconf_array_vout_am571x_idk
;
704 pconf_sz
= ARRAY_SIZE(core_padconf_array_vout_am571x_idk
);
705 delta_iod
= iodelay_cfg_array_am571x_idk_4port
;
706 delta_iod_sz
= ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port
);
709 pconf
= core_padconf_array_icss1eth_am571x_idk
;
710 pconf_sz
= ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk
);
712 do_set_mux32((*ctrl
)->control_padconf_core_base
, pconf
, pconf_sz
);
715 /* Setup IOdelay configuration */
716 ret
= do_set_iodelay((*ctrl
)->iodelay_config_base
, iod
, iod_sz
);
718 ret
= do_set_iodelay((*ctrl
)->iodelay_config_base
, delta_iod
,
722 /* Closeup.. remove isolation */
723 __recalibrate_iodelay_end(ret
);
727 #if defined(CONFIG_MMC)
728 int board_mmc_init(bd_t
*bis
)
730 omap_mmc_init(0, 0, 0, -1, -1);
731 omap_mmc_init(1, 0, 0, -1, -1);
736 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
737 int spl_start_uboot(void)
739 /* break into full u-boot on 'c' */
740 if (serial_tstc() && serial_getc() == 'c')
743 #ifdef CONFIG_SPL_ENV_SUPPORT
746 if (env_get_yesno("boot_os") != 1)
754 #ifdef CONFIG_USB_DWC3
755 static struct dwc3_device usb_otg_ss2
= {
756 .maximum_speed
= USB_SPEED_HIGH
,
757 .base
= DRA7_USB_OTG_SS2_BASE
,
758 .tx_fifo_resize
= false,
762 static struct dwc3_omap_device usb_otg_ss2_glue
= {
763 .base
= (void *)DRA7_USB_OTG_SS2_GLUE_BASE
,
764 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
768 static struct ti_usb_phy_device usb_phy2_device
= {
769 .usb2_phy_power
= (void *)DRA7_USB2_PHY2_POWER
,
773 int usb_gadget_handle_interrupts(int index
)
777 status
= dwc3_omap_uboot_interrupt_status(index
);
779 dwc3_uboot_handle_interrupt(index
);
783 #endif /* CONFIG_USB_DWC3 */
785 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
786 int omap_xhci_board_usb_init(int index
, enum usb_init_type init
)
788 enable_usb_clocks(index
);
791 if (init
== USB_INIT_DEVICE
) {
792 printf("port %d can't be used as device\n", index
);
793 disable_usb_clocks(index
);
798 if (init
== USB_INIT_DEVICE
) {
799 #ifdef CONFIG_USB_DWC3
800 usb_otg_ss2
.dr_mode
= USB_DR_MODE_PERIPHERAL
;
801 usb_otg_ss2_glue
.vbus_id_status
= OMAP_DWC3_VBUS_VALID
;
802 ti_usb_phy_uboot_init(&usb_phy2_device
);
803 dwc3_omap_uboot_init(&usb_otg_ss2_glue
);
804 dwc3_uboot_init(&usb_otg_ss2
);
807 printf("port %d can't be used as host\n", index
);
808 disable_usb_clocks(index
);
814 printf("Invalid Controller Index\n");
820 int omap_xhci_board_usb_cleanup(int index
, enum usb_init_type init
)
822 #ifdef CONFIG_USB_DWC3
826 if (init
== USB_INIT_DEVICE
) {
827 ti_usb_phy_uboot_exit(index
);
828 dwc3_uboot_exit(index
);
829 dwc3_omap_uboot_exit(index
);
833 printf("Invalid Controller Index\n");
836 disable_usb_clocks(index
);
839 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
841 #ifdef CONFIG_DRIVER_TI_CPSW
843 /* Delay value to add to calibrated value */
844 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
845 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
846 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
847 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
848 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
849 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
850 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
851 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
852 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
853 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
855 static void cpsw_control(int enabled
)
857 /* VTP can be added here */
860 static struct cpsw_slave_data cpsw_slaves
[] = {
862 .slave_reg_ofs
= 0x208,
863 .sliver_reg_ofs
= 0xd80,
867 .slave_reg_ofs
= 0x308,
868 .sliver_reg_ofs
= 0xdc0,
873 static struct cpsw_platform_data cpsw_data
= {
874 .mdio_base
= CPSW_MDIO_BASE
,
875 .cpsw_base
= CPSW_BASE
,
878 .cpdma_reg_ofs
= 0x800,
880 .slave_data
= cpsw_slaves
,
881 .ale_reg_ofs
= 0xd00,
883 .host_port_reg_ofs
= 0x108,
884 .hw_stats_reg_ofs
= 0x900,
885 .bd_ram_ofs
= 0x2000,
886 .mac_control
= (1 << 5),
887 .control
= cpsw_control
,
889 .version
= CPSW_CTRL_VERSION_2
,
892 static u64
mac_to_u64(u8 mac
[6])
897 for (i
= 0; i
< 6; i
++) {
905 static void u64_to_mac(u64 addr
, u8 mac
[6])
915 int board_eth_init(bd_t
*bis
)
919 uint32_t mac_hi
, mac_lo
;
923 u8 mac_addr1
[6], mac_addr2
[6];
926 /* try reading mac address from efuse */
927 mac_lo
= readl((*ctrl
)->control_core_mac_id_0_lo
);
928 mac_hi
= readl((*ctrl
)->control_core_mac_id_0_hi
);
929 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
930 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
931 mac_addr
[2] = mac_hi
& 0xFF;
932 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
933 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
934 mac_addr
[5] = mac_lo
& 0xFF;
936 if (!env_get("ethaddr")) {
937 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
939 if (is_valid_ethaddr(mac_addr
))
940 eth_env_set_enetaddr("ethaddr", mac_addr
);
943 mac_lo
= readl((*ctrl
)->control_core_mac_id_1_lo
);
944 mac_hi
= readl((*ctrl
)->control_core_mac_id_1_hi
);
945 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
946 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
947 mac_addr
[2] = mac_hi
& 0xFF;
948 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
949 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
950 mac_addr
[5] = mac_lo
& 0xFF;
952 if (!env_get("eth1addr")) {
953 if (is_valid_ethaddr(mac_addr
))
954 eth_env_set_enetaddr("eth1addr", mac_addr
);
957 ctrl_val
= readl((*ctrl
)->control_core_control_io1
) & (~0x33);
959 writel(ctrl_val
, (*ctrl
)->control_core_control_io1
);
961 /* The phy address for the AM57xx IDK are different than x15 */
962 if (board_is_am572x_idk() || board_is_am571x_idk()) {
963 cpsw_data
.slave_data
[0].phy_addr
= 0;
964 cpsw_data
.slave_data
[1].phy_addr
= 1;
967 ret
= cpsw_register(&cpsw_data
);
969 printf("Error %d registering CPSW switch\n", ret
);
972 * Export any Ethernet MAC addresses from EEPROM.
973 * On AM57xx the 2 MAC addresses define the address range
975 board_ti_get_eth_mac_addr(0, mac_addr1
);
976 board_ti_get_eth_mac_addr(1, mac_addr2
);
978 if (is_valid_ethaddr(mac_addr1
) && is_valid_ethaddr(mac_addr2
)) {
979 mac1
= mac_to_u64(mac_addr1
);
980 mac2
= mac_to_u64(mac_addr2
);
982 /* must contain an address range */
983 num_macs
= mac2
- mac1
+ 1;
984 /* <= 50 to protect against user programming error */
985 if (num_macs
> 0 && num_macs
<= 50) {
986 for (i
= 0; i
< num_macs
; i
++) {
987 u64_to_mac(mac1
+ i
, mac_addr
);
988 if (is_valid_ethaddr(mac_addr
)) {
989 eth_env_set_enetaddr_by_index("eth",
1001 #ifdef CONFIG_BOARD_EARLY_INIT_F
1002 /* VTT regulator enable */
1003 static inline void vtt_regulator_enable(void)
1005 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL
)
1008 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
1009 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
1012 int board_early_init_f(void)
1014 vtt_regulator_enable();
1019 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1020 int ft_board_setup(void *blob
, bd_t
*bd
)
1022 ft_cpu_setup(blob
, bd
);
1028 #ifdef CONFIG_SPL_LOAD_FIT
1029 int board_fit_config_name_match(const char *name
)
1031 if (board_is_x15()) {
1032 if (board_is_x15_revb1()) {
1033 if (!strcmp(name
, "am57xx-beagle-x15-revb1"))
1035 } else if (!strcmp(name
, "am57xx-beagle-x15")) {
1038 } else if (board_is_am572x_evm() &&
1039 !strcmp(name
, "am57xx-beagle-x15")) {
1041 } else if (board_is_am572x_idk() && !strcmp(name
, "am572x-idk")) {
1043 } else if (board_is_am571x_idk() && !strcmp(name
, "am571x-idk")) {
1051 #ifdef CONFIG_TI_SECURE_DEVICE
1052 void board_fit_image_post_process(void **p_image
, size_t *p_size
)
1054 secure_boot_verify_image(p_image
, p_size
);
1057 void board_tee_image_process(ulong tee_image
, size_t tee_size
)
1059 secure_tee_install((u32
)tee_image
);
1062 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE
, board_tee_image_process
);