3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <common.h> /* core U-Boot definitions */
26 #include <spartan2.h> /* Spartan-II device family */
28 #if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2))
30 /* Define FPGA_DEBUG to get debug printf's */
32 #define PRINTF(fmt,args...) printf (fmt ,##args)
34 #define PRINTF(fmt,args...)
37 #undef CFG_FPGA_CHECK_BUSY
38 #define CFG_FPGA_PROG_FEEDBACK
40 /* Note: The assumption is that we cannot possibly run fast enough to
41 * overrun the device (the Slave Parallel mode can free run at 50MHz).
42 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
43 * the board config file to slow things down.
45 #ifndef CONFIG_FPGA_DELAY
46 #define CONFIG_FPGA_DELAY()
50 #define CFG_FPGA_WAIT 10
53 static int Spartan2_sp_load( Xilinx_desc
*desc
, void *buf
, size_t bsize
);
54 static int Spartan2_sp_dump( Xilinx_desc
*desc
, void *buf
, size_t bsize
);
55 /* static int Spartan2_sp_info( Xilinx_desc *desc ); */
56 static int Spartan2_sp_reloc( Xilinx_desc
*desc
, ulong reloc_offset
);
58 static int Spartan2_ss_load( Xilinx_desc
*desc
, void *buf
, size_t bsize
);
59 static int Spartan2_ss_dump( Xilinx_desc
*desc
, void *buf
, size_t bsize
);
60 /* static int Spartan2_ss_info( Xilinx_desc *desc ); */
61 static int Spartan2_ss_reloc( Xilinx_desc
*desc
, ulong reloc_offset
);
63 /* ------------------------------------------------------------------------- */
64 /* Spartan-II Generic Implementation */
65 int Spartan2_load (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
67 int ret_val
= FPGA_FAIL
;
69 switch (desc
->iface
) {
71 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__
);
72 ret_val
= Spartan2_ss_load (desc
, buf
, bsize
);
76 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__
);
77 ret_val
= Spartan2_sp_load (desc
, buf
, bsize
);
81 printf ("%s: Unsupported interface type, %d\n",
82 __FUNCTION__
, desc
->iface
);
88 int Spartan2_dump (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
90 int ret_val
= FPGA_FAIL
;
92 switch (desc
->iface
) {
94 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__
);
95 ret_val
= Spartan2_ss_dump (desc
, buf
, bsize
);
99 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__
);
100 ret_val
= Spartan2_sp_dump (desc
, buf
, bsize
);
104 printf ("%s: Unsupported interface type, %d\n",
105 __FUNCTION__
, desc
->iface
);
111 int Spartan2_info( Xilinx_desc
*desc
)
117 int Spartan2_reloc (Xilinx_desc
* desc
, ulong reloc_offset
)
119 int ret_val
= FPGA_FAIL
; /* assume a failure */
121 if (desc
->family
!= Xilinx_Spartan2
) {
122 printf ("%s: Unsupported family type, %d\n",
123 __FUNCTION__
, desc
->family
);
126 switch (desc
->iface
) {
128 ret_val
= Spartan2_ss_reloc (desc
, reloc_offset
);
132 ret_val
= Spartan2_sp_reloc (desc
, reloc_offset
);
136 printf ("%s: Unsupported interface type, %d\n",
137 __FUNCTION__
, desc
->iface
);
144 /* ------------------------------------------------------------------------- */
145 /* Spartan-II Slave Parallel Generic Implementation */
147 static int Spartan2_sp_load (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
149 int ret_val
= FPGA_FAIL
; /* assume the worst */
150 Xilinx_Spartan2_Slave_Parallel_fns
*fn
= desc
->iface_fns
;
152 PRINTF ("%s: start with interface functions @ 0x%p\n",
156 size_t bytecount
= 0;
157 unsigned char *data
= (unsigned char *) buf
;
158 int cookie
= desc
->cookie
; /* make a local copy */
159 unsigned long ts
; /* timestamp */
161 PRINTF ("%s: Function Table:\n"
172 "write data:\t0x%p\n"
176 __FUNCTION__
, &fn
, fn
, fn
->pre
, fn
->pgm
, fn
->init
, fn
->err
,
177 fn
->clk
, fn
->cs
, fn
->wr
, fn
->rdata
, fn
->wdata
, fn
->busy
,
178 fn
->abort
, fn
->post
);
181 * This code is designed to emulate the "Express Style"
182 * Continuous Data Loading in Slave Parallel Mode for
183 * the Spartan-II Family.
185 #ifdef CFG_FPGA_PROG_FEEDBACK
186 printf ("Loading FPGA Device %d...\n", cookie
);
189 * Run the pre configuration function if there is one.
195 /* Establish the initial state */
196 (*fn
->pgm
) (TRUE
, TRUE
, cookie
); /* Assert the program, commit */
198 /* Get ready for the burn */
199 CONFIG_FPGA_DELAY ();
200 (*fn
->pgm
) (FALSE
, TRUE
, cookie
); /* Deassert the program, commit */
202 ts
= get_timer (0); /* get current time */
203 /* Now wait for INIT and BUSY to go high */
205 CONFIG_FPGA_DELAY ();
206 if (get_timer (ts
) > CFG_FPGA_WAIT
) { /* check the time */
207 puts ("** Timeout waiting for INIT to clear.\n");
208 (*fn
->abort
) (cookie
); /* abort the burn */
211 } while ((*fn
->init
) (cookie
) && (*fn
->busy
) (cookie
));
213 (*fn
->wr
) (TRUE
, TRUE
, cookie
); /* Assert write, commit */
214 (*fn
->cs
) (TRUE
, TRUE
, cookie
); /* Assert chip select, commit */
215 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
218 while (bytecount
< bsize
) {
219 /* XXX - do we check for an Ctrl-C press in here ??? */
220 /* XXX - Check the error bit? */
222 (*fn
->wdata
) (data
[bytecount
++], TRUE
, cookie
); /* write the data */
223 CONFIG_FPGA_DELAY ();
224 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
225 CONFIG_FPGA_DELAY ();
226 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
228 #ifdef CFG_FPGA_CHECK_BUSY
229 ts
= get_timer (0); /* get current time */
230 while ((*fn
->busy
) (cookie
)) {
231 /* XXX - we should have a check in here somewhere to
232 * make sure we aren't busy forever... */
234 CONFIG_FPGA_DELAY ();
235 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
236 CONFIG_FPGA_DELAY ();
237 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
239 if (get_timer (ts
) > CFG_FPGA_WAIT
) { /* check the time */
240 puts ("** Timeout waiting for BUSY to clear.\n");
241 (*fn
->abort
) (cookie
); /* abort the burn */
247 #ifdef CFG_FPGA_PROG_FEEDBACK
248 if (bytecount
% (bsize
/ 40) == 0)
249 putc ('.'); /* let them know we are alive */
253 CONFIG_FPGA_DELAY ();
254 (*fn
->cs
) (FALSE
, TRUE
, cookie
); /* Deassert the chip select */
255 (*fn
->wr
) (FALSE
, TRUE
, cookie
); /* Deassert the write pin */
257 #ifdef CFG_FPGA_PROG_FEEDBACK
258 putc ('\n'); /* terminate the dotted line */
261 /* now check for done signal */
262 ts
= get_timer (0); /* get current time */
263 ret_val
= FPGA_SUCCESS
;
264 while ((*fn
->done
) (cookie
) == FPGA_FAIL
) {
265 /* XXX - we should have a check in here somewhere to
266 * make sure we aren't busy forever... */
268 CONFIG_FPGA_DELAY ();
269 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
270 CONFIG_FPGA_DELAY ();
271 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
273 if (get_timer (ts
) > CFG_FPGA_WAIT
) { /* check the time */
274 puts ("** Timeout waiting for DONE to clear.\n");
275 (*fn
->abort
) (cookie
); /* abort the burn */
281 if (ret_val
== FPGA_SUCCESS
) {
282 #ifdef CFG_FPGA_PROG_FEEDBACK
287 * Run the post configuration function if there is one.
290 (*fn
->post
) (cookie
);
294 #ifdef CFG_FPGA_PROG_FEEDBACK
300 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
306 static int Spartan2_sp_dump (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
308 int ret_val
= FPGA_FAIL
; /* assume the worst */
309 Xilinx_Spartan2_Slave_Parallel_fns
*fn
= desc
->iface_fns
;
312 unsigned char *data
= (unsigned char *) buf
;
313 size_t bytecount
= 0;
314 int cookie
= desc
->cookie
; /* make a local copy */
316 printf ("Starting Dump of FPGA Device %d...\n", cookie
);
318 (*fn
->cs
) (TRUE
, TRUE
, cookie
); /* Assert chip select, commit */
319 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
322 while (bytecount
< bsize
) {
323 /* XXX - do we check for an Ctrl-C press in here ??? */
325 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
326 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
327 (*fn
->rdata
) (&(data
[bytecount
++]), cookie
); /* read the data */
328 #ifdef CFG_FPGA_PROG_FEEDBACK
329 if (bytecount
% (bsize
/ 40) == 0)
330 putc ('.'); /* let them know we are alive */
334 (*fn
->cs
) (FALSE
, FALSE
, cookie
); /* Deassert the chip select */
335 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
336 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
338 #ifdef CFG_FPGA_PROG_FEEDBACK
339 putc ('\n'); /* terminate the dotted line */
343 /* XXX - checksum the data? */
345 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
352 static int Spartan2_sp_reloc (Xilinx_desc
* desc
, ulong reloc_offset
)
354 int ret_val
= FPGA_FAIL
; /* assume the worst */
355 Xilinx_Spartan2_Slave_Parallel_fns
*fn_r
, *fn
=
356 (Xilinx_Spartan2_Slave_Parallel_fns
*) (desc
->iface_fns
);
361 /* Get the relocated table address */
362 addr
= (ulong
) fn
+ reloc_offset
;
363 fn_r
= (Xilinx_Spartan2_Slave_Parallel_fns
*) addr
;
365 if (!fn_r
->relocated
) {
367 if (memcmp (fn_r
, fn
,
368 sizeof (Xilinx_Spartan2_Slave_Parallel_fns
))
370 /* good copy of the table, fix the descriptor pointer */
371 desc
->iface_fns
= fn_r
;
373 PRINTF ("%s: Invalid function table at 0x%p\n",
378 PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__
,
381 addr
= (ulong
) (fn
->pre
) + reloc_offset
;
382 fn_r
->pre
= (Xilinx_pre_fn
) addr
;
384 addr
= (ulong
) (fn
->pgm
) + reloc_offset
;
385 fn_r
->pgm
= (Xilinx_pgm_fn
) addr
;
387 addr
= (ulong
) (fn
->init
) + reloc_offset
;
388 fn_r
->init
= (Xilinx_init_fn
) addr
;
390 addr
= (ulong
) (fn
->done
) + reloc_offset
;
391 fn_r
->done
= (Xilinx_done_fn
) addr
;
393 addr
= (ulong
) (fn
->clk
) + reloc_offset
;
394 fn_r
->clk
= (Xilinx_clk_fn
) addr
;
396 addr
= (ulong
) (fn
->err
) + reloc_offset
;
397 fn_r
->err
= (Xilinx_err_fn
) addr
;
399 addr
= (ulong
) (fn
->cs
) + reloc_offset
;
400 fn_r
->cs
= (Xilinx_cs_fn
) addr
;
402 addr
= (ulong
) (fn
->wr
) + reloc_offset
;
403 fn_r
->wr
= (Xilinx_wr_fn
) addr
;
405 addr
= (ulong
) (fn
->rdata
) + reloc_offset
;
406 fn_r
->rdata
= (Xilinx_rdata_fn
) addr
;
408 addr
= (ulong
) (fn
->wdata
) + reloc_offset
;
409 fn_r
->wdata
= (Xilinx_wdata_fn
) addr
;
411 addr
= (ulong
) (fn
->busy
) + reloc_offset
;
412 fn_r
->busy
= (Xilinx_busy_fn
) addr
;
414 addr
= (ulong
) (fn
->abort
) + reloc_offset
;
415 fn_r
->abort
= (Xilinx_abort_fn
) addr
;
417 addr
= (ulong
) (fn
->post
) + reloc_offset
;
418 fn_r
->post
= (Xilinx_post_fn
) addr
;
420 fn_r
->relocated
= TRUE
;
423 /* this table has already been moved */
424 /* XXX - should check to see if the descriptor is correct */
425 desc
->iface_fns
= fn_r
;
428 ret_val
= FPGA_SUCCESS
;
430 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
437 /* ------------------------------------------------------------------------- */
439 static int Spartan2_ss_load (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
441 printf ("%s: Slave Serial Loading is still unsupported\n",
446 static int Spartan2_ss_dump (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
448 printf ("%s: Slave Serial Dumping is still unsupported\n",
453 static int Spartan2_ss_reloc (Xilinx_desc
* desc
, ulong reloc_offset
)
455 int ret_val
= FPGA_FAIL
; /* assume the worst */
456 Xilinx_Spartan2_Slave_Serial_fns
*fn
=
457 (Xilinx_Spartan2_Slave_Serial_fns
*) (desc
->iface_fns
);
460 printf ("%s: Slave Serial Loading is still unsupported\n",
463 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);